1 | |
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2 | /* SOCLIB_LGPL_HEADER_BEGIN |
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3 | * |
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4 | * This file is part of SoCLib, GNU LGPLv2.1. |
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5 | * |
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6 | * SoCLib is free software; you can redistribute it and/or modify it |
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7 | * under the terms of the GNU Lesser General Public License as published |
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8 | * by the Free Software Foundation; version 2.1 of the License. |
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9 | * |
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10 | * SoCLib is distributed in the hope that it will be useful, but |
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11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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13 | * Lesser General Public License for more details. |
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14 | * |
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15 | * You should have received a copy of the GNU Lesser General Public |
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16 | * License along with SoCLib; if not, write to the Free Software |
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17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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18 | * 02110-1301 USA |
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19 | * |
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20 | * SOCLIB_LGPL_HEADER_END |
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21 | * |
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22 | * Author : Abdelmalek SI MERABET |
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23 | * Date : Februrary 2011 |
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24 | * Copyright: UPMC - LIP6 |
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25 | */ |
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26 | #ifndef DSPIN_HALF_GATEWAY_INITIATOR_FAST_H |
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27 | #define DSPIN_HALF_GATEWAY_INITIATOR_FAST_H |
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28 | |
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29 | #include "caba_base_module.h" |
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30 | #include "generic_fifo.h" |
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31 | #include "mapping_table.h" |
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32 | #include "ring_signals_fast.h" |
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33 | #include "dspin_interface.h" |
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34 | |
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35 | #define BRDCST_TGT_MASK 0xFFFFFFFFE1ULL |
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36 | #define HI_DEBUG |
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37 | |
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38 | namespace soclib { namespace caba { |
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39 | |
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40 | namespace { |
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41 | |
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42 | const char *ring_cmd_fsm_state_str_hi[] = { |
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43 | "CMD_IDLE", |
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44 | "OWNER", |
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45 | "BDC_FIRST", |
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46 | "BDC_SECOND", |
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47 | "SENDING", |
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48 | }; |
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49 | |
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50 | #ifdef HI_DEBUG |
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51 | |
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52 | const char *ring_rsp_fsm_state_str_hi[] = { |
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53 | "RSP_IDLE", |
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54 | "ALLOC", |
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55 | "NALLOC", |
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56 | }; |
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57 | #endif |
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58 | |
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59 | } |
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60 | template<typename vci_param, int ring_cmd_data_size, int ring_rsp_data_size> |
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61 | class DspinHalfGatewayInitiatorFastC |
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62 | { |
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63 | |
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64 | typedef LocalRingSignals ring_signal_t; |
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65 | typedef DspinInput<ring_cmd_data_size> cmd_in_t; |
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66 | typedef DspinOutput<ring_rsp_data_size> rsp_out_t; |
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67 | |
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68 | private: |
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69 | |
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70 | enum ring_rsp_fsm_state_e { |
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71 | RSP_IDLE, // waiting for first flit of a response packet |
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72 | ALLOC, // next flit of a local rsp packet |
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73 | NALLOC, // next flit of a ring rsp packet |
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74 | }; |
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75 | |
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76 | enum ring_cmd_fsm_state_e { |
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77 | CMD_IDLE, |
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78 | OWNER, |
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79 | BDC_FIRST, |
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80 | BDC_SECOND, |
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81 | SENDING, |
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82 | PREEMPT, |
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83 | }; |
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84 | |
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85 | // structural parameters |
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86 | std::string m_name; |
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87 | bool m_alloc_init; |
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88 | |
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89 | |
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90 | // internal fifos |
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91 | GenericFifo<uint64_t > m_cmd_fifo; // fifo for the local command packet |
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92 | GenericFifo<uint64_t > m_rsp_fifo; // fifo for the local response packet |
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93 | |
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94 | // routing table |
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95 | soclib::common::AddressDecodingTable<uint32_t, bool> m_lt; |
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96 | |
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97 | uint64_t r_brdcst_save; |
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98 | uint32_t m_srcid; |
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99 | uint32_t m_nb_target; |
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100 | uint32_t m_x_width; |
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101 | uint32_t m_y_width; |
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102 | |
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103 | // internal registers |
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104 | sc_core::sc_signal<bool> r_preempt; // ring preempted, priority to gate init. |
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105 | sc_core::sc_signal<uint32_t> r_cpt_tgt; // target id for sequential broadcast |
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106 | sc_core::sc_signal<uint32_t> r_ring_cmd_fsm; // ring command packet FSM (distributed) |
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107 | sc_core::sc_signal<uint32_t> r_ring_rsp_fsm; // ring response packet FSM |
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108 | |
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109 | public : |
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110 | |
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111 | #define __renRegGateInit(x) x((((std::string) name)+"_" #x).c_str()) |
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112 | |
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113 | DspinHalfGatewayInitiatorFastC( |
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114 | const char *name, |
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115 | bool alloc_init, |
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116 | const int &wrapper_fifo_depth, |
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117 | const soclib::common::MappingTable &mt, |
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118 | const soclib::common::IntTab &ringid, |
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119 | const uint32_t &nb_target, |
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120 | const uint32_t &x_width, |
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121 | const uint32_t &y_width) |
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122 | : m_name(name), |
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123 | m_alloc_init(alloc_init), |
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124 | m_cmd_fifo(((std::string) name)+"m_cmd_fifo", wrapper_fifo_depth), |
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125 | m_rsp_fifo(((std::string) name)+"m_rsp_fifo", wrapper_fifo_depth), |
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126 | m_lt(mt.getIdLocalityTable(ringid)), |
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127 | m_nb_target(nb_target), |
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128 | m_x_width(x_width), |
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129 | m_y_width(y_width), |
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130 | __renRegGateInit(r_cpt_tgt), |
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131 | __renRegGateInit(r_ring_cmd_fsm), |
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132 | __renRegGateInit(r_ring_rsp_fsm) |
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133 | { } // end constructor |
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134 | |
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135 | |
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136 | void reset() |
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137 | { |
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138 | if(m_alloc_init) |
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139 | r_ring_cmd_fsm = OWNER; |
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140 | else |
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141 | r_ring_cmd_fsm = CMD_IDLE; |
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142 | |
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143 | r_ring_rsp_fsm = RSP_IDLE; |
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144 | m_cmd_fifo.init(); |
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145 | m_rsp_fifo.init(); |
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146 | |
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147 | } |
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148 | |
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149 | void transition(const cmd_in_t &p_gate_cmd_in, const rsp_out_t &p_gate_rsp_out, const ring_signal_t p_ring_in, cmd_str &init_cmd, bool &init_rsp_val, const bool tga) |
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150 | { |
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151 | |
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152 | bool cmd_fifo_get = false; |
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153 | bool cmd_fifo_put = false; |
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154 | uint64_t cmd_fifo_data = 0; |
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155 | |
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156 | bool rsp_fifo_put = false; |
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157 | uint64_t rsp_fifo_data = 0; |
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158 | |
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159 | |
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160 | //////////// VCI CMD FSM ///////////////////////// |
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161 | |
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162 | if (p_gate_cmd_in.write.read()) { |
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163 | cmd_fifo_data = (uint64_t) p_gate_cmd_in.data.read(); |
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164 | cmd_fifo_put = m_cmd_fifo.wok(); |
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165 | } |
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166 | |
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167 | bool rsp_fifo_get = p_gate_rsp_out.read.read(); |
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168 | |
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169 | //////////// RING CMD FSM ///////////////////////// |
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170 | switch( r_ring_cmd_fsm ) |
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171 | { |
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172 | case CMD_IDLE: |
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173 | { |
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174 | |
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175 | // tga : target gate allocated |
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176 | if(m_cmd_fifo.rok()) |
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177 | { |
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178 | #ifdef HI_DEBUG |
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179 | std::cout << std::dec << sc_time_stamp() << " - " << m_name |
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180 | << " - ring_cmd_fsm = " << ring_cmd_fsm_state_str_hi[r_ring_cmd_fsm] |
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181 | << " - fifo ROK : " << m_cmd_fifo.rok() |
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182 | << " - fifo _data : " << std::hex << m_cmd_fifo.read() |
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183 | << " - in grant : " << p_ring_in.cmd_grant |
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184 | << " - in tga : " << tga |
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185 | << " - in wok : " << p_ring_in.cmd_r |
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186 | << " - in data : " << p_ring_in.cmd_data |
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187 | |
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188 | << std::endl; |
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189 | #endif |
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190 | r_preempt = tga; |
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191 | |
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192 | if (m_cmd_fifo.read() & 0x1 == 0x1) // broadcast |
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193 | { |
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194 | if (tga || p_ring_in.cmd_grant) |
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195 | { |
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196 | r_cpt_tgt = 0; |
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197 | r_brdcst_save = m_cmd_fifo.read() & BRDCST_TGT_MASK; // save first flit of brdcst |
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198 | r_ring_cmd_fsm = BDC_FIRST; |
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199 | } |
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200 | } |
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201 | else if(tga || p_ring_in.cmd_grant) |
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202 | { |
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203 | cmd_fifo_get = tga && p_ring_in.cmd_r; |
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204 | r_ring_cmd_fsm = SENDING; |
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205 | } |
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206 | |
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207 | } |
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208 | } |
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209 | break; |
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210 | |
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211 | case OWNER: |
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212 | if ( m_cmd_fifo.rok()) // && p_ring_in.cmd_wok.read() ) |
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213 | { |
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214 | #ifdef HI_DEBUG |
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215 | std::cout << std::dec << sc_time_stamp() << " - " << m_name |
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216 | << " - ring_cmd_fsm = " << ring_cmd_fsm_state_str_hi[r_ring_cmd_fsm] |
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217 | << " - fifo ROK : " << m_cmd_fifo.rok() |
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218 | << " - in grant : " << p_ring_in.cmd_grant |
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219 | << " - in wok : " << p_ring_in.cmd_r |
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220 | << " - fifo data : " << std::hex << m_cmd_fifo.read() |
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221 | << std::endl; |
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222 | #endif |
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223 | |
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224 | bool eop = ( (int) ((m_cmd_fifo.read() >> (ring_cmd_data_size - 1) ) & 0x1) == 1); |
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225 | |
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226 | if (m_cmd_fifo.read() & 0x1 == 0x1) // broadcast |
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227 | { |
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228 | r_cpt_tgt = 0; |
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229 | r_brdcst_save = m_cmd_fifo.read() & BRDCST_TGT_MASK; // save first flit of brdcst |
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230 | r_ring_cmd_fsm = BDC_FIRST; |
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231 | } |
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232 | // |
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233 | else |
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234 | { |
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235 | if ( eop && p_ring_in.cmd_r ) |
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236 | { |
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237 | cmd_fifo_get = true; |
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238 | if ( p_ring_in.cmd_grant ) |
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239 | r_ring_cmd_fsm = OWNER; |
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240 | else |
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241 | r_ring_cmd_fsm = CMD_IDLE; |
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242 | } |
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243 | |
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244 | if (!eop || !p_ring_in.cmd_r) |
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245 | { |
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246 | cmd_fifo_get = p_ring_in.cmd_r; |
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247 | r_ring_cmd_fsm = SENDING; |
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248 | } |
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249 | |
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250 | } |
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251 | |
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252 | } |
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253 | else if ( !p_ring_in.cmd_grant) |
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254 | r_ring_cmd_fsm = CMD_IDLE; |
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255 | break; |
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256 | |
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257 | case BDC_FIRST: |
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258 | |
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259 | #ifdef HI_DEBUG |
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260 | std::cout << std::dec << sc_time_stamp() << " - " << m_name |
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261 | << " - ring_cmd_fsm = " << ring_cmd_fsm_state_str_hi[r_ring_cmd_fsm] |
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262 | << " - fifo ROK : " << m_cmd_fifo.rok() |
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263 | << " - in grant : " << p_ring_in.cmd_grant |
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264 | << " - preempt : " << r_preempt |
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265 | << " - in wok : " << p_ring_in.cmd_r |
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266 | << " - cpt_tgt : " << r_cpt_tgt.read() |
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267 | << " - fifo data : " << std::hex << m_cmd_fifo.read() |
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268 | << std::endl; |
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269 | |
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270 | #endif |
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271 | |
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272 | if (p_ring_in.cmd_r) |
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273 | { |
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274 | if (r_cpt_tgt.read() == 0) |
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275 | { |
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276 | cmd_fifo_get = true; |
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277 | } |
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278 | r_ring_cmd_fsm = BDC_SECOND; |
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279 | } |
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280 | break; |
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281 | |
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282 | case BDC_SECOND: |
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283 | #ifdef HI_DEBUG |
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284 | std::cout << std::dec << sc_time_stamp() << " - " << m_name |
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285 | << " - ring_cmd_fsm = " << ring_cmd_fsm_state_str_hi[r_ring_cmd_fsm] |
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286 | << " - fifo ROK : " << m_cmd_fifo.rok() |
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287 | << " - in grant : " << p_ring_in.cmd_grant |
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288 | << " - preempt : " << r_preempt |
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289 | << " - in wok : " << p_ring_in.cmd_r |
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290 | << " - fifo data : " << std::hex << m_cmd_fifo.read() |
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291 | << std::endl; |
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292 | |
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293 | #endif |
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294 | |
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295 | if(m_cmd_fifo.rok() && p_ring_in.cmd_r) |
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296 | { |
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297 | if(r_cpt_tgt.read() == m_nb_target - 1) |
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298 | { |
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299 | cmd_fifo_get = true; |
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300 | |
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301 | if ( !r_preempt && p_ring_in.cmd_grant ) |
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302 | { |
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303 | r_ring_cmd_fsm = OWNER; |
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304 | } |
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305 | else //r_preempt || !p_ring_in.cmd_grant |
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306 | { |
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307 | r_ring_cmd_fsm = CMD_IDLE; |
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308 | } |
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309 | } |
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310 | else |
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311 | { |
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312 | r_cpt_tgt = r_cpt_tgt + 1; |
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313 | r_ring_cmd_fsm = BDC_FIRST; |
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314 | } |
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315 | |
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316 | } |
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317 | break; |
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318 | |
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319 | case SENDING: |
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320 | #ifdef HI_DEBUG |
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321 | if(m_cmd_fifo.rok()) |
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322 | std::cout << std::dec << sc_time_stamp() << " - " << m_name |
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323 | << " - ring_cmd_fsm = " << ring_cmd_fsm_state_str_hi[r_ring_cmd_fsm] |
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324 | << " - fifo ROK : " << m_cmd_fifo.rok() |
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325 | << " - in grant : " << p_ring_in.cmd_grant |
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326 | << " - in wok : " << p_ring_in.cmd_r |
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327 | << " - fifo data : " << std::hex << m_cmd_fifo.read() |
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328 | << std::endl; |
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329 | #endif |
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330 | |
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331 | |
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332 | if(m_cmd_fifo.rok() && p_ring_in.cmd_r ) |
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333 | { |
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334 | cmd_fifo_get = true; |
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335 | bool eop = ((int) (m_cmd_fifo.read() >> (ring_cmd_data_size - 1) ) & 0x1) == 1; |
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336 | if (eop) |
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337 | { |
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338 | if (!r_preempt && p_ring_in.cmd_grant ) |
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339 | r_ring_cmd_fsm = OWNER; |
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340 | else |
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341 | r_ring_cmd_fsm = CMD_IDLE; |
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342 | } |
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343 | } |
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344 | break; |
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345 | |
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346 | } // end switch ring cmd fsm |
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347 | |
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348 | /////////// RING RSP FSM //////////////////////// |
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349 | |
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350 | switch( r_ring_rsp_fsm ) |
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351 | { |
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352 | case RSP_IDLE: |
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353 | |
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354 | { |
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355 | uint32_t rsrcid = (uint32_t) ((sc_dt::sc_uint<vci_param::S>) ((p_ring_in.rsp_data >> (ring_rsp_data_size-m_x_width-m_y_width - 1)) << (vci_param::S-m_x_width-m_y_width))); |
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356 | bool islocal = !m_lt[rsrcid]; |
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357 | bool reop = ((p_ring_in.rsp_data >> (ring_rsp_data_size - 1)) & 0x1) == 1; |
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358 | |
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359 | |
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360 | |
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361 | if (p_ring_in.rsp_w) |
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362 | { |
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363 | #ifdef HI_DEBUG |
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364 | std::cout << std::dec << sc_time_stamp() << " - " << m_name |
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365 | << " - ring_rsp_fsm = " << ring_rsp_fsm_state_str_hi[r_ring_rsp_fsm] |
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366 | << " - in preempt : " << p_ring_in.rsp_preempt |
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367 | << " - in rok : " << p_ring_in.rsp_w |
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368 | << " - in data : " << std::hex << p_ring_in.rsp_data |
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369 | << " - rsrcid : " << rsrcid |
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370 | << " - isloc : " << islocal |
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371 | << " - in wok : " << p_ring_in.rsp_r |
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372 | << " - fifo wok : " << m_rsp_fifo.wok() |
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373 | << " - reop : " << reop |
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374 | << std::endl; |
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375 | #endif |
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376 | if(islocal) |
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377 | { |
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378 | rsp_fifo_put = m_rsp_fifo.wok(); |
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379 | rsp_fifo_data = p_ring_in.rsp_data; |
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380 | |
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381 | if (reop && m_rsp_fifo.wok()) |
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382 | r_ring_rsp_fsm = RSP_IDLE; |
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383 | else |
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384 | r_ring_rsp_fsm = ALLOC; |
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385 | } |
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386 | |
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387 | else // !islocal |
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388 | { |
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389 | |
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390 | if (reop && p_ring_in.rsp_r) |
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391 | r_ring_rsp_fsm = RSP_IDLE; |
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392 | else |
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393 | r_ring_rsp_fsm = NALLOC; |
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394 | } |
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395 | } |
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396 | else // !p_ring_in.rsp_w |
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397 | r_ring_rsp_fsm = RSP_IDLE; |
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398 | } |
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399 | break; |
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400 | |
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401 | case ALLOC: |
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402 | { |
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403 | bool reop = ((p_ring_in.rsp_data >> (ring_rsp_data_size - 1)) & 0x1) == 1; |
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404 | #ifdef HI_DEBUG |
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405 | if(p_ring_in.rsp_w || p_ring_in.rsp_preempt) |
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406 | std::cout << std::dec << sc_time_stamp() << " - " << m_name |
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407 | << " - ring_rsp_fsm = " << ring_rsp_fsm_state_str_hi[r_ring_rsp_fsm] |
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408 | << " - in preempt : " << p_ring_in.rsp_preempt |
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409 | << " - in rok : " << p_ring_in.rsp_w |
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410 | << " - in wok : " << p_ring_in.rsp_r |
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411 | << " - in data : " << std::hex << p_ring_in.rsp_data |
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412 | << " - fifo wok : " << m_rsp_fifo.wok() |
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413 | << " - reop : " << reop |
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414 | << std::endl; |
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415 | #endif |
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416 | |
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417 | |
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418 | if(p_ring_in.rsp_preempt) break; |
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419 | |
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420 | if (p_ring_in.rsp_w && m_rsp_fifo.wok() && reop) |
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421 | { |
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422 | |
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423 | rsp_fifo_put = true; |
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424 | rsp_fifo_data = p_ring_in.rsp_data; |
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425 | |
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426 | if(p_ring_in.rsp_palloc) |
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427 | r_ring_rsp_fsm = NALLOC; |
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428 | else |
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429 | r_ring_rsp_fsm = RSP_IDLE; |
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430 | } |
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431 | else // !p_ring_in.rsp_w || !m_rsp_fifo.wok() || !reop |
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432 | { |
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433 | |
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434 | rsp_fifo_put = p_ring_in.rsp_w && m_rsp_fifo.wok(); |
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435 | rsp_fifo_data = p_ring_in.rsp_data; |
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436 | r_ring_rsp_fsm = ALLOC; |
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437 | } |
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438 | } |
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439 | break; |
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440 | |
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441 | case NALLOC: |
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442 | { |
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443 | |
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444 | #ifdef HI_DEBUG |
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445 | if(p_ring_in.rsp_w) |
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446 | std::cout << std::dec << sc_time_stamp() << " - " << m_name |
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447 | << " - ring_rsp_fsm = " << ring_rsp_fsm_state_str_hi[r_ring_rsp_fsm] |
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448 | << " - in rok : " << p_ring_in.rsp_w |
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449 | << " - fifo wok : " << m_rsp_fifo.wok() |
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450 | << " - in wok : " << p_ring_in.rsp_r |
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451 | << " - in data : " << std::hex << p_ring_in.rsp_data |
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452 | << std::endl; |
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453 | #endif |
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454 | |
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455 | bool reop = ((p_ring_in.rsp_data >> (ring_rsp_data_size - 1)) & 0x1) == 1; |
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456 | |
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457 | |
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458 | if (p_ring_in.rsp_w && reop && p_ring_in.rsp_r) |
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459 | { |
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460 | r_ring_rsp_fsm = RSP_IDLE; |
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461 | } |
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462 | else |
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463 | { |
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464 | r_ring_rsp_fsm = NALLOC; |
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465 | } |
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466 | } |
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467 | break; |
---|
468 | |
---|
469 | } // end switch rsp fsm |
---|
470 | |
---|
471 | |
---|
472 | //////////////////////// |
---|
473 | // fifos update // |
---|
474 | //////////////////////// |
---|
475 | |
---|
476 | //-- keep trace on ring traffic |
---|
477 | init_cmd.cmdval = cmd_fifo_get; |
---|
478 | init_cmd.flit = m_cmd_fifo.read(); |
---|
479 | init_cmd.state = ring_cmd_fsm_state_str_hi[r_ring_cmd_fsm]; |
---|
480 | |
---|
481 | //init_cmd_val = cmd_fifo_get; |
---|
482 | init_rsp_val = rsp_fifo_put; |
---|
483 | // local cmd fifo update |
---|
484 | if ( cmd_fifo_put && cmd_fifo_get ) m_cmd_fifo.put_and_get(cmd_fifo_data); |
---|
485 | else if ( cmd_fifo_put && !cmd_fifo_get ) m_cmd_fifo.simple_put(cmd_fifo_data); |
---|
486 | else if ( !cmd_fifo_put && cmd_fifo_get ) m_cmd_fifo.simple_get(); |
---|
487 | |
---|
488 | // local rsp fifo update |
---|
489 | if ( rsp_fifo_put && rsp_fifo_get ) m_rsp_fifo.put_and_get(rsp_fifo_data); |
---|
490 | else if ( rsp_fifo_put && !rsp_fifo_get ) m_rsp_fifo.simple_put(rsp_fifo_data); |
---|
491 | else if ( !rsp_fifo_put && rsp_fifo_get ) m_rsp_fifo.simple_get(); |
---|
492 | |
---|
493 | } // end Transition() |
---|
494 | |
---|
495 | /////////////////////////////////////////////////////////////////// |
---|
496 | void genMoore(cmd_in_t &p_gate_cmd_in, rsp_out_t &p_gate_rsp_out) |
---|
497 | /////////////////////////////////////////////////////////////////// |
---|
498 | { |
---|
499 | p_gate_rsp_out.write = m_rsp_fifo.rok(); |
---|
500 | p_gate_rsp_out.data = (sc_dt::sc_uint<ring_rsp_data_size>) m_rsp_fifo.read(); |
---|
501 | |
---|
502 | p_gate_cmd_in.read= m_cmd_fifo.wok(); |
---|
503 | |
---|
504 | } // end genMoore |
---|
505 | |
---|
506 | ///////////////////////////////////////////////////////////////////////////////////////////////// |
---|
507 | void update_ring_signals(ring_signal_t p_ring_in, ring_signal_t &p_ring_out, bool tga, bool &iga) |
---|
508 | ///////////////////////////////////////////////////////////////////////////////////////////////// |
---|
509 | // palloc may have 2 values : |
---|
510 | // palloc = 2 : means Target Gate still allocated |
---|
511 | // global state for targets : TG TL0 TL1 TL2 ... TLn |
---|
512 | // A N N P2 N |
---|
513 | // A N N N N |
---|
514 | // palloc = 1 : means Target Gate free (not allocated) |
---|
515 | // global state for targets : TG TL0 TL1 TL2 ... TLn |
---|
516 | // A N N P2 N |
---|
517 | // N N N P1 N |
---|
518 | // I I I I I |
---|
519 | // TLi not allocated, in case of preempt and last flit, needs to test value of palloc |
---|
520 | // if palloc=1 => next state : IDLE (TG not allocated) |
---|
521 | // else (palloc2=2) => next state : NALLOC (TG still Allocated) |
---|
522 | { |
---|
523 | switch( r_ring_cmd_fsm ) |
---|
524 | { |
---|
525 | case CMD_IDLE: |
---|
526 | { |
---|
527 | bool brdcst = (m_cmd_fifo.read() & 0x1 == 0x1); |
---|
528 | |
---|
529 | p_ring_out.cmd_grant = !m_cmd_fifo.rok() && p_ring_in.cmd_grant; |
---|
530 | |
---|
531 | if (m_cmd_fifo.rok() && tga && !brdcst) |
---|
532 | { |
---|
533 | p_ring_out.cmd_preempt = 1; |
---|
534 | p_ring_out.cmd_palloc = 1; |
---|
535 | p_ring_out.cmd_header = 1; |
---|
536 | p_ring_out.cmd_w = 1; |
---|
537 | p_ring_out.cmd_data = m_cmd_fifo.read(); |
---|
538 | } |
---|
539 | else |
---|
540 | { |
---|
541 | p_ring_out.cmd_preempt = 0; |
---|
542 | p_ring_out.cmd_palloc = 0; |
---|
543 | p_ring_out.cmd_header = 0; |
---|
544 | p_ring_out.cmd_w = p_ring_in.cmd_w; |
---|
545 | p_ring_out.cmd_data = p_ring_in.cmd_data; |
---|
546 | } |
---|
547 | |
---|
548 | } |
---|
549 | break; |
---|
550 | |
---|
551 | case OWNER: |
---|
552 | { |
---|
553 | bool eop = ((int) ((m_cmd_fifo.read() >> (ring_cmd_data_size - 1) ) & 0x1) == 1); |
---|
554 | bool brdcst = (m_cmd_fifo.read() & 0x1 == 0x1); |
---|
555 | |
---|
556 | p_ring_out.cmd_grant = (!m_cmd_fifo.rok() || (eop && p_ring_in.cmd_r)) ; |
---|
557 | |
---|
558 | p_ring_out.cmd_preempt = 0; |
---|
559 | p_ring_out.cmd_header = 0; |
---|
560 | p_ring_out.cmd_palloc = 0; |
---|
561 | p_ring_out.cmd_w = m_cmd_fifo.rok() && !brdcst; |
---|
562 | p_ring_out.cmd_data = m_cmd_fifo.read(); |
---|
563 | } |
---|
564 | break; |
---|
565 | |
---|
566 | case BDC_FIRST: |
---|
567 | if(r_preempt) |
---|
568 | { |
---|
569 | p_ring_out.cmd_header = 1; |
---|
570 | p_ring_out.cmd_palloc = 1+(tga ? 1:0); |
---|
571 | p_ring_out.cmd_preempt = 1; |
---|
572 | p_ring_out.cmd_grant = p_ring_in.cmd_grant; |
---|
573 | } |
---|
574 | else |
---|
575 | { |
---|
576 | p_ring_out.cmd_header = 0; |
---|
577 | p_ring_out.cmd_palloc = 0; |
---|
578 | p_ring_out.cmd_preempt = 0; |
---|
579 | p_ring_out.cmd_grant = false; |
---|
580 | } |
---|
581 | |
---|
582 | p_ring_out.cmd_w = true; |
---|
583 | p_ring_out.cmd_data = r_brdcst_save | ((((uint64_t) r_cpt_tgt.read()) & 0xF) << 0x1); |
---|
584 | break; |
---|
585 | |
---|
586 | case BDC_SECOND: |
---|
587 | |
---|
588 | if (r_preempt) |
---|
589 | { |
---|
590 | p_ring_out.cmd_grant = p_ring_in.cmd_grant; |
---|
591 | p_ring_out.cmd_palloc = 1+(tga ? 1:0); |
---|
592 | |
---|
593 | p_ring_out.cmd_preempt = m_cmd_fifo.rok(); //&& tga; |
---|
594 | p_ring_out.cmd_header = 0; |
---|
595 | |
---|
596 | if ( m_cmd_fifo.rok() ) |
---|
597 | { |
---|
598 | p_ring_out.cmd_w = 1; //m_cmd_fifo.rok(); |
---|
599 | p_ring_out.cmd_data = m_cmd_fifo.read(); |
---|
600 | } |
---|
601 | else |
---|
602 | { |
---|
603 | // if init local has finished, tga = 0 |
---|
604 | // init gate remains the only initiator, then w = 0 |
---|
605 | p_ring_out.cmd_w = p_ring_in.cmd_w && tga; |
---|
606 | p_ring_out.cmd_data = p_ring_in.cmd_data; |
---|
607 | } |
---|
608 | } |
---|
609 | else |
---|
610 | { |
---|
611 | // si on est dans cet etat, c'est qu'on n'utilise pas le cmd_preempt mais le gnt. |
---|
612 | p_ring_out.cmd_preempt= 0; |
---|
613 | p_ring_out.cmd_header = 0; |
---|
614 | p_ring_out.cmd_palloc = 0; |
---|
615 | p_ring_out.cmd_w = m_cmd_fifo.rok(); |
---|
616 | p_ring_out.cmd_data = m_cmd_fifo.read(); |
---|
617 | p_ring_out.cmd_grant = m_cmd_fifo.rok() && p_ring_in.cmd_r && (r_cpt_tgt.read() == m_nb_target - 1); |
---|
618 | } |
---|
619 | break; |
---|
620 | |
---|
621 | case SENDING: |
---|
622 | { |
---|
623 | |
---|
624 | if (r_preempt) |
---|
625 | { |
---|
626 | p_ring_out.cmd_grant = p_ring_in.cmd_grant; |
---|
627 | p_ring_out.cmd_palloc = 1+(tga ? 1:0); |
---|
628 | |
---|
629 | p_ring_out.cmd_preempt = m_cmd_fifo.rok(); //&& tga; |
---|
630 | p_ring_out.cmd_header = 0; |
---|
631 | |
---|
632 | if ( m_cmd_fifo.rok() ) |
---|
633 | { |
---|
634 | p_ring_out.cmd_w = 1; //m_cmd_fifo.rok(); |
---|
635 | p_ring_out.cmd_data = m_cmd_fifo.read(); |
---|
636 | } |
---|
637 | else |
---|
638 | { |
---|
639 | // if init local has finished, tga = 0 |
---|
640 | // init gate remains the only initiator, then w = 0 |
---|
641 | p_ring_out.cmd_w = p_ring_in.cmd_w && tga; |
---|
642 | p_ring_out.cmd_data = p_ring_in.cmd_data; |
---|
643 | } |
---|
644 | } |
---|
645 | else |
---|
646 | { |
---|
647 | bool eop = ((int) (m_cmd_fifo.read() >> (ring_cmd_data_size - 1) ) & 0x1) == 1; |
---|
648 | // si on est dans cet etat, c'est qu'on n'utilise pas le cmd_preempt mais le gnt. |
---|
649 | p_ring_out.cmd_preempt= 0; |
---|
650 | p_ring_out.cmd_header = 0; |
---|
651 | p_ring_out.cmd_palloc = 0; |
---|
652 | p_ring_out.cmd_w = m_cmd_fifo.rok(); |
---|
653 | p_ring_out.cmd_data = m_cmd_fifo.read(); |
---|
654 | p_ring_out.cmd_grant = m_cmd_fifo.rok() && p_ring_in.cmd_r && eop; |
---|
655 | } |
---|
656 | } |
---|
657 | break; |
---|
658 | |
---|
659 | } // end switch |
---|
660 | |
---|
661 | p_ring_out.cmd_r = p_ring_in.cmd_r; |
---|
662 | |
---|
663 | p_ring_out.rsp_w = p_ring_in.rsp_w; |
---|
664 | p_ring_out.rsp_data = p_ring_in.rsp_data; |
---|
665 | |
---|
666 | p_ring_out.rsp_grant = p_ring_in.rsp_grant; |
---|
667 | |
---|
668 | p_ring_out.rsp_palloc = p_ring_in.rsp_palloc; |
---|
669 | p_ring_out.rsp_preempt = p_ring_in.rsp_preempt; |
---|
670 | p_ring_out.rsp_header = p_ring_in.rsp_header; |
---|
671 | |
---|
672 | |
---|
673 | switch( r_ring_rsp_fsm ) |
---|
674 | { |
---|
675 | case RSP_IDLE: |
---|
676 | { |
---|
677 | uint32_t rsrcid = (uint32_t) ((sc_dt::sc_uint<vci_param::S>) ((p_ring_in.rsp_data >> (ring_rsp_data_size-m_x_width-m_y_width - 1)) << (vci_param::S-m_x_width-m_y_width))); |
---|
678 | bool islocal = !m_lt[rsrcid]; |
---|
679 | |
---|
680 | iga = false; |
---|
681 | |
---|
682 | if(p_ring_in.rsp_w && islocal) |
---|
683 | p_ring_out.rsp_r = m_rsp_fifo.wok(); |
---|
684 | else |
---|
685 | p_ring_out.rsp_r = p_ring_in.rsp_r; |
---|
686 | } |
---|
687 | break; |
---|
688 | |
---|
689 | case ALLOC: |
---|
690 | iga = true; |
---|
691 | |
---|
692 | if (!p_ring_in.rsp_preempt) |
---|
693 | p_ring_out.rsp_r = m_rsp_fifo.wok(); |
---|
694 | else |
---|
695 | p_ring_out.rsp_r = p_ring_in.rsp_r; |
---|
696 | break; |
---|
697 | |
---|
698 | case NALLOC: |
---|
699 | iga = false; |
---|
700 | p_ring_out.rsp_r = p_ring_in.rsp_r; |
---|
701 | break; |
---|
702 | } // end switch |
---|
703 | |
---|
704 | |
---|
705 | } // end update_ring_signals |
---|
706 | |
---|
707 | }; |
---|
708 | |
---|
709 | }} // end namespace |
---|
710 | |
---|
711 | #endif // DSPIN_HALF_GATEWAY_INITIATOR_FAST_H |
---|
712 | |
---|