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vci_mem_cache.h

Last change on this file was 920, checked in by meunier, 10 years ago
Adding branch wt_ideal -- "ideal" write-through
File size: 29.8 KB

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1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain.greiner@lip6.fr
28	* eric.guthmuller@polytechnique.edu
29	* cesar.fuguet-tortolero@lip6.fr
30	* alexandre.joannou@lip6.fr
31	*/
32
33	#ifndef SOCLIB_CABA_MEM_CACHE_H
34	#define SOCLIB_CABA_MEM_CACHE_H
35
36	#include <inttypes.h>
37	#include <systemc>
38	#include <list>
39	#include <cassert>
40
41	#include "arithmetics.h"
42	#include "alloc_elems.h"
43	#include "caba_base_module.h"
44	#include "vci_target.h"
45	#include "vci_initiator.h"
46	#include "generic_fifo.h"
47	#include "mapping_table.h"
48	#include "int_tab.h"
49	#include "generic_llsc_global_table.h"
50	#include "mem_cache_directory.h"
51	#include "xram_transaction.h"
52	#include "update_tab.h"
53	#include "dspin_interface.h"
54	#include "dspin_wtidl_param.h"
55
56	#include "vci_cc_vcache_wrapper.h"
57	#include "gdbserver.h"
58
59	#define TRT_ENTRIES 4 // Number of entries in TRT
60	#define UPT_ENTRIES 4 // Number of entries in UPT (unused)
61	#define IVT_ENTRIES 4 // Number of entries in IVT (unused)
62	#define HEAP_ENTRIES 1024 // Number of entries in the HEAP (unused)
63
64	namespace soclib { namespace caba {
65
66	using namespace sc_core;
67
68	template<typename vci_param_int,
69	typename vci_param_ext,
70	size_t memc_dspin_in_width,
71	size_t memc_dspin_out_width>
72	class VciMemCache
73	: public soclib::caba::BaseModule
74	{
75	typedef typename vci_param_int::fast_addr_t addr_t;
76	typedef typename sc_dt::sc_uint<64> wide_data_t;
77	typedef uint32_t data_t;
78	typedef uint32_t tag_t;
79	typedef uint32_t be_t;
80	typedef uint32_t copy_t;
81
82	/* States of the TGT_CMD fsm */
83	enum tgt_cmd_fsm_state_e
84	{
85	TGT_CMD_IDLE,
86	TGT_CMD_READ,
87	TGT_CMD_WRITE,
88	TGT_CMD_CAS,
89	TGT_CMD_CONFIG,
90	TGT_CMD_ERROR
91	};
92
93	/* States of the TGT_RSP fsm */
94	enum tgt_rsp_fsm_state_e
95	{
96	TGT_RSP_READ_IDLE,
97	TGT_RSP_WRITE_IDLE,
98	TGT_RSP_CAS_IDLE,
99	TGT_RSP_XRAM_IDLE,
100	TGT_RSP_MULTI_ACK_IDLE,
101	TGT_RSP_CLEANUP_IDLE,
102	TGT_RSP_TGT_CMD_IDLE,
103	TGT_RSP_CONFIG_IDLE,
104	TGT_RSP_READ,
105	TGT_RSP_WRITE,
106	TGT_RSP_CAS,
107	TGT_RSP_XRAM,
108	TGT_RSP_TGT_CMD,
109	TGT_RSP_CONFIG
110	};
111
112	/* States of the CONFIG fsm */
113	enum config_fsm_state_e
114	{
115	CONFIG_IDLE,
116	CONFIG_LOOP,
117	CONFIG_WAIT,
118	CONFIG_RSP,
119	CONFIG_DIR_REQ,
120	CONFIG_DIR_ACCESS,
121	CONFIG_TRT_LOCK,
122	CONFIG_TRT_SET,
123	CONFIG_PUT_REQ
124	};
125
126	/* States of the READ fsm */
127	enum read_fsm_state_e
128	{
129	READ_IDLE,
130	READ_DIR_REQ,
131	READ_DIR_LOCK,
132	READ_DIR_HIT,
133	READ_RSP,
134	READ_TRT_LOCK,
135	READ_TRT_SET,
136	READ_TRT_REQ
137	};
138
139	/* States of the WRITE fsm */
140	enum write_fsm_state_e
141	{
142	WRITE_IDLE,
143	WRITE_NEXT,
144	WRITE_DIR_REQ,
145	WRITE_DIR_LOCK,
146	WRITE_DIR_HIT,
147	WRITE_RSP,
148	WRITE_MISS_TRT_LOCK,
149	WRITE_MISS_TRT_DATA,
150	WRITE_MISS_TRT_SET,
151	WRITE_MISS_XRAM_REQ,
152	WRITE_WAIT
153	};
154
155	/* States of the IXR_RSP fsm */
156	enum ixr_rsp_fsm_state_e
157	{
158	IXR_RSP_IDLE,
159	IXR_RSP_TRT_ERASE,
160	IXR_RSP_TRT_READ
161	};
162
163	/* States of the XRAM_RSP fsm */
164	enum xram_rsp_fsm_state_e
165	{
166	XRAM_RSP_IDLE,
167	XRAM_RSP_TRT_COPY,
168	XRAM_RSP_TRT_DIRTY,
169	XRAM_RSP_DIR_LOCK,
170	XRAM_RSP_DIR_UPDT,
171	XRAM_RSP_DIR_RSP,
172	XRAM_RSP_WRITE_DIRTY,
173	XRAM_RSP_ERROR_ERASE,
174	XRAM_RSP_ERROR_RSP
175	};
176
177	/* States of the IXR_CMD fsm */
178	enum ixr_cmd_fsm_state_e
179	{
180	IXR_CMD_READ_IDLE,
181	IXR_CMD_WRITE_IDLE,
182	IXR_CMD_CAS_IDLE,
183	IXR_CMD_XRAM_IDLE,
184	IXR_CMD_CONFIG_IDLE,
185	IXR_CMD_READ_TRT,
186	IXR_CMD_WRITE_TRT,
187	IXR_CMD_CAS_TRT,
188	IXR_CMD_XRAM_TRT,
189	IXR_CMD_CONFIG_TRT,
190	IXR_CMD_READ_SEND,
191	IXR_CMD_WRITE_SEND,
192	IXR_CMD_CAS_SEND,
193	IXR_CMD_XRAM_SEND,
194	IXR_CMD_CONFIG_SEND
195	};
196
197	/* States of the CAS fsm */
198	enum cas_fsm_state_e
199	{
200	CAS_IDLE,
201	CAS_DIR_REQ,
202	CAS_DIR_LOCK,
203	CAS_DIR_HIT_READ,
204	CAS_DIR_HIT_COMPARE,
205	CAS_DIR_HIT_WRITE,
206	CAS_RSP_FAIL,
207	CAS_RSP_SUCCESS,
208	CAS_MISS_TRT_LOCK,
209	CAS_MISS_TRT_SET,
210	CAS_MISS_XRAM_REQ,
211	CAS_WAIT
212	};
213
214	/* States of the ALLOC_DIR fsm */
215	enum alloc_dir_fsm_state_e
216	{
217	ALLOC_DIR_RESET,
218	ALLOC_DIR_READ,
219	ALLOC_DIR_WRITE,
220	ALLOC_DIR_CAS,
221	ALLOC_DIR_XRAM_RSP,
222	ALLOC_DIR_CONFIG
223	};
224
225	/* States of the ALLOC_TRT fsm */
226	enum alloc_trt_fsm_state_e
227	{
228	ALLOC_TRT_READ,
229	ALLOC_TRT_WRITE,
230	ALLOC_TRT_CAS,
231	ALLOC_TRT_XRAM_RSP,
232	ALLOC_TRT_IXR_RSP,
233	ALLOC_TRT_IXR_CMD,
234	ALLOC_TRT_CONFIG
235	};
236
237	/* transaction type, pktid field */
238	enum transaction_type_e
239	{
240	// b3 unused
241	// b2 READ / NOT READ
242	// Si READ
243	// b1 DATA / INS
244	// b0 UNC / MISS
245	// Si NOT READ
246	// b1 accÃšs table llsc type SW / other
247	// b2 WRITE/CAS/LL/SC
248	TYPE_READ_DATA_UNC = 0x0,
249	TYPE_READ_DATA_MISS = 0x1,
250	TYPE_READ_INS_UNC = 0x2,
251	TYPE_READ_INS_MISS = 0x3,
252	TYPE_WRITE = 0x4,
253	TYPE_CAS = 0x5,
254	TYPE_LL = 0x6,
255	TYPE_SC = 0x7
256	};
257
258	/* SC return values */
259	enum sc_status_type_e
260	{
261	SC_SUCCESS = 0x00000000,
262	SC_FAIL = 0x00000001
263	};
264
265	// debug variables
266	bool m_debug;
267	bool m_debug_previous_valid;
268	size_t m_debug_previous_count;
269	bool m_debug_previous_dirty;
270	data_t * m_debug_previous_data;
271	data_t * m_debug_data;
272
273	// instrumentation counters
274	uint64_t m_cpt_cycles; // Counter of cycles
275	uint64_t m_cpt_reset_count; // Cycle at which the counters were last reset
276
277	// Counters accessible in software (not yet but eventually)
278	uint32_t m_cpt_read_local; // Number of local READ transactions
279	uint32_t m_cpt_read_remote; // number of remote READ transactions
280	uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs
281
282	uint32_t m_cpt_write_local; // Number of local WRITE transactions
283	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
284	uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs
285	uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
286	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs
287
288	uint32_t m_cpt_ll_local; // Number of local LL transactions
289	uint32_t m_cpt_ll_remote; // number of remote LL transactions
290	uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs
291
292	uint32_t m_cpt_sc_local; // Number of local SC transactions
293	uint32_t m_cpt_sc_remote; // number of remote SC transactions
294	uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs
295
296	uint32_t m_cpt_cas_local; // Number of local SC transactions
297	uint32_t m_cpt_cas_remote; // number of remote SC transactions
298	uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs
299
300	uint32_t m_cpt_update; // Number of requests causing an UPDATE
301	uint32_t m_cpt_update_local; // Number of local UPDATE transactions
302	uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions
303	uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT
304
305	uint32_t m_cpt_binval; // Number of BROADCAST INVAL
306
307	// Counters not accessible by software
308	uint32_t m_cpt_read_miss; // Number of MISS READ
309	uint32_t m_cpt_write_miss; // Number of MISS WRITE
310	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
311	uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because of writes
312
313	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
314	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
315
316	uint32_t m_cpt_get;
317	uint32_t m_cpt_put;
318
319	size_t m_prev_count;
320
321	typedef VciCcVCacheWrapper<vci_param_int,
322	memc_dspin_out_width, memc_dspin_in_width,
323	soclib::common::GdbServer<soclib::common::Mips32ElIss> > L1Cache;
324
325	std::list<L1Cache *> m_cc_vcaches;
326
327	protected:
328
329	SC_HAS_PROCESS(VciMemCache);
330
331	public:
332	sc_in<bool> p_clk;
333	sc_in<bool> p_resetn;
334	sc_out<bool> p_irq;
335	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
336	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
337	soclib::caba::DspinInput<memc_dspin_in_width> p_dspin_p2m;
338	soclib::caba::DspinOutput<memc_dspin_out_width> p_dspin_m2p;
339	soclib::caba::DspinOutput<memc_dspin_out_width> p_dspin_clack;
340
341	#if MONITOR_MEMCACHE_FSM == 1
342	sc_out<int> p_read_fsm;
343	sc_out<int> p_write_fsm;
344	sc_out<int> p_xram_rsp_fsm;
345	sc_out<int> p_cas_fsm;
346	sc_out<int> p_config_fsm;
347	sc_out<int> p_alloc_dir_fsm;
348	sc_out<int> p_alloc_trt_fsm;
349	sc_out<int> p_tgt_cmd_fsm;
350	sc_out<int> p_tgt_rsp_fsm;
351	sc_out<int> p_ixr_cmd_fsm;
352	sc_out<int> p_ixr_rsp_fsm;
353	#endif
354
355	VciMemCache(
356	sc_module_name name, // Instance Name
357	const soclib::common::MappingTable &mtp, // Mapping table INT network
358	const soclib::common::MappingTable &mtx, // Mapping table RAM network
359	const soclib::common::IntTab &srcid_x, // global index RAM network
360	const soclib::common::IntTab &tgtid_d, // global index INT network
361	const size_t x_width, // X width in platform
362	const size_t y_width, // Y width in platform
363	const size_t nways, // Number of ways per set
364	const size_t nsets, // Number of sets
365	const size_t nwords, // Number of words per line
366	const size_t max_copies, // max number of copies
367	const size_t heap_size = HEAP_ENTRIES,
368	const size_t trt_lines = TRT_ENTRIES,
369	const size_t upt_lines = UPT_ENTRIES,
370	const size_t ivt_lines = IVT_ENTRIES,
371	const size_t debug_start_cycle = 0,
372	const bool debug_ok = false);
373
374	~VciMemCache();
375
376	void set_vcache_list(std::list<L1Cache *> l1_caches);
377	void cc_vcaches_direct_update(addr_t addr, sc_signal<uint32_t> * data, sc_signal<uint32_t> * be, int32_t srcid);
378	void cc_vcaches_direct_update(addr_t addr, uint32_t data, uint32_t be, int32_t srcid);
379	void reset_counters();
380	void print_stats(bool activity_counters = true, bool stats = true);
381	void print_trace(size_t detailed = 0);
382	void cache_monitor(addr_t addr, bool single_word = false);
383	void start_monitor(addr_t addr, addr_t length);
384	void stop_monitor();
385
386	private:
387
388	void transition();
389	void genMoore();
390	void check_monitor(addr_t addr, data_t data, bool read);
391
392	uint32_t req_distance(uint32_t req_srcid);
393	bool is_local_req(uint32_t req_srcid);
394	int read_instrumentation(uint32_t regr, uint32_t & rdata);
395
396	// Component attributes
397	std::list<soclib::common::Segment> m_seglist; // segments allocated
398	size_t m_nseg; // number of segments
399	soclib::common::Segment **m_seg; // array of segments pointers
400	size_t m_seg_config; // config segment index
401	const size_t m_srcid_x; // global index on RAM network
402	const size_t m_initiators; // Number of initiators
403	const size_t m_ways; // Number of ways in a set
404	const size_t m_sets; // Number of cache sets
405	const size_t m_words; // Number of words in a line
406	size_t m_x_self; // X self coordinate
407	size_t m_y_self; // Y self coordinate
408	const size_t m_x_width; // number of x bits in platform
409	const size_t m_y_width; // number of y bits in platform
410	size_t m_debug_start_cycle;
411	bool m_debug_ok;
412	uint32_t m_trt_lines;
413	TransactionTab m_trt; // xram transaction table
414	CacheDirectory m_cache_directory; // data cache directory
415	CacheData m_cache_data; // data array[set][way][word]
416	GenericLLSCGlobalTable
417	< 32 , // number of slots
418	4096, // number of processors in the system
419	8000, // registration life (# of LL operations)
420	addr_t > m_llsc_table; // ll/sc registration table
421
422	// adress masks
423	const soclib::common::AddressMaskingTable<addr_t> m_x;
424	const soclib::common::AddressMaskingTable<addr_t> m_y;
425	const soclib::common::AddressMaskingTable<addr_t> m_z;
426	const soclib::common::AddressMaskingTable<addr_t> m_nline;
427
428	// broadcast address
429	uint32_t m_broadcast_boundaries;
430
431	// configuration interface constants
432	const uint32_t m_config_addr_mask;
433	const uint32_t m_config_regr_width;
434	const uint32_t m_config_func_width;
435	const uint32_t m_config_regr_idx_mask;
436	const uint32_t m_config_func_idx_mask;
437
438	// Fifo between TGT_CMD fsm and READ fsm
439	GenericFifo<addr_t> m_cmd_read_addr_fifo;
440	GenericFifo<size_t> m_cmd_read_length_fifo;
441	GenericFifo<size_t> m_cmd_read_srcid_fifo;
442	GenericFifo<size_t> m_cmd_read_trdid_fifo;
443	GenericFifo<size_t> m_cmd_read_pktid_fifo;
444
445	// Fifo between TGT_CMD fsm and WRITE fsm
446	GenericFifo<addr_t> m_cmd_write_addr_fifo;
447	GenericFifo<bool> m_cmd_write_eop_fifo;
448	GenericFifo<size_t> m_cmd_write_srcid_fifo;
449	GenericFifo<size_t> m_cmd_write_trdid_fifo;
450	GenericFifo<size_t> m_cmd_write_pktid_fifo;
451	GenericFifo<data_t> m_cmd_write_data_fifo;
452	GenericFifo<be_t> m_cmd_write_be_fifo;
453
454	// Fifo between TGT_CMD fsm and CAS fsm
455	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
456	GenericFifo<bool> m_cmd_cas_eop_fifo;
457	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
458	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
459	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
460	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
461
462	// Buffer between TGT_CMD fsm and TGT_RSP fsm
463	// (segmentation violation response request)
464	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
465
466	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
467	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
468	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
469	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
470	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
471
472	sc_signal<addr_t> r_tgt_cmd_config_addr;
473	sc_signal<size_t> r_tgt_cmd_config_cmd;
474
475	//////////////////////////////////////////////////
476	// Registers controlled by the TGT_CMD fsm
477	//////////////////////////////////////////////////
478
479	sc_signal<int> r_tgt_cmd_fsm;
480
481	///////////////////////////////////////////////////////
482	// Registers controlled by the CONFIG fsm
483	///////////////////////////////////////////////////////
484
485	sc_signal<int> r_config_fsm; // FSM state
486	sc_signal<bool> r_config_lock; // lock protecting exclusive access
487	sc_signal<int> r_config_cmd; // config request type
488	sc_signal<addr_t> r_config_address; // target buffer physical address
489	sc_signal<size_t> r_config_srcid; // config request srcid
490	sc_signal<size_t> r_config_trdid; // config request trdid
491	sc_signal<size_t> r_config_pktid; // config request pktid
492	sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled
493	sc_signal<size_t> r_config_rsp_lines; // number of lines not completed
494	sc_signal<size_t> r_config_dir_way; // DIR: selected way
495	sc_signal<bool> r_config_dir_lock; // DIR: locked entry
496	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
497	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast)
498	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
499	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
500	sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP
501	sc_signal<size_t> r_config_trt_index; // selected entry in TRT
502
503	// Buffer between CONFIG fsm and IXR_CMD fsm
504	sc_signal<bool> r_config_to_ixr_cmd_req; // valid request
505	sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
506
507	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
508	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
509	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
510	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
511	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
512	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
513
514	///////////////////////////////////////////////////////
515	// Registers controlled by the READ fsm
516	///////////////////////////////////////////////////////
517
518	sc_signal<int> r_read_fsm; // FSM state
519	sc_signal<size_t> r_read_copy; // Srcid of the first copy
520	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
521	sc_signal<bool> r_read_copy_inst; // Type of the first copy
522	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
523	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
524	sc_signal<bool> r_read_lock; // lock bit (in directory)
525	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
526	sc_signal<size_t> r_read_count; // number of copies
527	sc_signal<data_t> * r_read_data; // data (one cache line)
528	sc_signal<size_t> r_read_way; // associative way (in cache)
529	sc_signal<size_t> r_read_trt_index; // Transaction Table index
530	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
531	sc_signal<bool> r_read_last_free; // Last free entry
532	sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table
533
534	// Buffer between READ fsm and IXR_CMD fsm
535	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
536	sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index
537
538	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
539	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
540	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
541	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
542	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
543	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
544	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
545	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
546	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
547
548	///////////////////////////////////////////////////////////////
549	// Registers controlled by the WRITE fsm
550	///////////////////////////////////////////////////////////////
551
552	sc_signal<int> r_write_fsm; // FSM state
553	sc_signal<addr_t> r_write_address; // first word address
554	sc_signal<size_t> r_write_word_index; // first word index in line
555	sc_signal<size_t> r_write_word_count; // number of words in line
556	sc_signal<size_t> r_write_srcid; // transaction srcid
557	sc_signal<size_t> r_write_trdid; // transaction trdid
558	sc_signal<size_t> r_write_pktid; // transaction pktid
559	sc_signal<data_t> * r_write_data; // data (one cache line)
560	sc_signal<be_t> * r_write_be; // one byte enable per word
561	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
562	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
563	sc_signal<bool> r_write_lock; // lock bit (in directory)
564	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
565	sc_signal<size_t> r_write_copy; // first owner of the line
566	sc_signal<size_t> r_write_copy_cache; // first owner of the line
567	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
568	sc_signal<size_t> r_write_count; // number of copies
569	sc_signal<bool> r_write_to_dec; // need to decrement update counter
570	sc_signal<size_t> r_write_way; // way of the line
571	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
572	sc_signal<bool> r_write_sc_fail; // sc command failed
573	sc_signal<data_t> r_write_sc_key; // sc command key
574	sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer
575
576	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
577	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
578	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
579	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
580	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
581	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
582
583	// Buffer between WRITE fsm and IXR_CMD fsm
584	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
585	sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index
586
587	///////////////////////////////////////////////////////
588	// Registers controlled by CAS fsm
589	///////////////////////////////////////////////////////
590
591	sc_signal<int> r_cas_fsm; // FSM state
592	sc_signal<data_t> r_cas_wdata; // write data word
593	sc_signal<data_t> * r_cas_rdata; // read data word
594	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
595	sc_signal<size_t> r_cas_cpt; // size of command
596	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
597	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
598	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
599	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
600	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
601	sc_signal<size_t> r_cas_way; // way in directory
602	sc_signal<size_t> r_cas_set; // set in directory
603	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
604	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
605	sc_signal<data_t> * r_cas_data; // cache line data
606
607	// Buffer between CAS fsm and IXR_CMD fsm
608	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
609	sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index
610
611	// Buffer between CAS fsm and TGT_RSP fsm
612	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
613	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
614	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
615	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
616	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
617
618	////////////////////////////////////////////////////
619	// Registers controlled by the IXR_RSP fsm
620	////////////////////////////////////////////////////
621
622	sc_signal<int> r_ixr_rsp_fsm; // FSM state
623	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
624	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
625
626	// Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM)
627	sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit
628
629	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
630	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry
631
632	////////////////////////////////////////////////////
633	// Registers controlled by the XRAM_RSP fsm
634	////////////////////////////////////////////////////
635
636	sc_signal<int> r_xram_rsp_fsm; // FSM state
637	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
638	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
639	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
640	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
641	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
642	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
643	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
644	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
645	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
646	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
647	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
648	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
649	sc_signal<bool> r_xram_rsp_rerror_irq; // WRITE MISS rerror irq
650	sc_signal<bool> r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable
651	sc_signal<addr_t> r_xram_rsp_rerror_address; // WRITE MISS rerror address
652	sc_signal<size_t> r_xram_rsp_rerror_rsrcid; // WRITE MISS rerror srcid
653
654	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
655	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
656	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
657	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
658	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
659	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
660	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
661	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
662	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
663	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
664
665	// Buffer between XRAM_RSP fsm and IXR_CMD fsm
666	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
667	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index
668
669	////////////////////////////////////////////////////
670	// Registers controlled by the IXR_CMD fsm
671	////////////////////////////////////////////////////
672
673	sc_signal<int> r_ixr_cmd_fsm;
674	sc_signal<size_t> r_ixr_cmd_word; // word index for a put
675	sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value
676	sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM
677	sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer
678	sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET)
679
680	////////////////////////////////////////////////////
681	// Registers controlled by TGT_RSP fsm
682	////////////////////////////////////////////////////
683
684	sc_signal<int> r_tgt_rsp_fsm;
685	sc_signal<size_t> r_tgt_rsp_cpt;
686	sc_signal<bool> r_tgt_rsp_key_sent;
687
688	////////////////////////////////////////////////////
689	// Registers controlled by ALLOC_DIR fsm
690	////////////////////////////////////////////////////
691
692	sc_signal<int> r_alloc_dir_fsm;
693	sc_signal<unsigned> r_alloc_dir_reset_cpt;
694
695	////////////////////////////////////////////////////
696	// Registers controlled by ALLOC_TRT fsm
697	////////////////////////////////////////////////////
698
699	sc_signal<int> r_alloc_trt_fsm;
700
701	}; // end class VciMemCache
702
703	}}
704
705	#endif
706
707	// Local Variables:
708	// tab-width: 2
709	// c-basic-offset: 2
710	// c-file-offsets:((innamespace . 0)(inline-open . 0))
711	// indent-tabs-mode: nil
712	// End:
713
714	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
715

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source: branches/wt_ideal/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

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