1 | /* -*- c++ -*- |
---|
2 | * File : vci_cc_vcache_wrapper_v1.h |
---|
3 | * Copyright (c) UPMC, Lip6, SoC |
---|
4 | * Authors : Alain GREINER, Yang GAO |
---|
5 | * |
---|
6 | * SOCLIB_LGPL_HEADER_BEGIN |
---|
7 | * |
---|
8 | * This file is part of SoCLib, GNU LGPLv2.1. |
---|
9 | * |
---|
10 | * SoCLib is free software; you can redistribute it and/or modify it |
---|
11 | * under the terms of the GNU Lesser General Public License as published |
---|
12 | * by the Free Software Foundation; version 2.1 of the License. |
---|
13 | * |
---|
14 | * SoCLib is distributed in the hope that it will be useful, but |
---|
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
17 | * Lesser General Public License for more details. |
---|
18 | * |
---|
19 | * You should have received a copy of the GNU Lesser General Public |
---|
20 | * License along with SoCLib; if not, write to the Free Software |
---|
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
---|
22 | * 02110-1301 USA |
---|
23 | * |
---|
24 | * SOCLIB_LGPL_HEADER_END |
---|
25 | */ |
---|
26 | |
---|
27 | #ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V1_H |
---|
28 | #define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V1_H |
---|
29 | |
---|
30 | #include <inttypes.h> |
---|
31 | #include <systemc> |
---|
32 | #include "caba_base_module.h" |
---|
33 | #include "write_buffer.h" |
---|
34 | #include "generic_cache.h" |
---|
35 | #include "vci_initiator.h" |
---|
36 | #include "vci_target.h" |
---|
37 | #include "mapping_table.h" |
---|
38 | #include "generic_tlb.h" |
---|
39 | #include "static_assert.h" |
---|
40 | |
---|
41 | namespace soclib { |
---|
42 | namespace caba { |
---|
43 | |
---|
44 | using namespace sc_core; |
---|
45 | |
---|
46 | //////////////////////////////////////////// |
---|
47 | template<typename vci_param, typename iss_t> |
---|
48 | class VciCcVCacheWrapperV1 |
---|
49 | //////////////////////////////////////////// |
---|
50 | : public soclib::caba::BaseModule |
---|
51 | { |
---|
52 | typedef uint32_t vaddr_t; |
---|
53 | typedef uint32_t data_t; |
---|
54 | typedef uint32_t tag_t; |
---|
55 | typedef uint32_t type_t; |
---|
56 | typedef typename iss_t::DataOperationType data_op_t; |
---|
57 | |
---|
58 | typedef typename vci_param::addr_t paddr_t; |
---|
59 | typedef typename vci_param::be_t vci_be_t; |
---|
60 | typedef typename vci_param::srcid_t vci_srcid_t; |
---|
61 | typedef typename vci_param::trdid_t vci_trdid_t; |
---|
62 | typedef typename vci_param::pktid_t vci_pktid_t; |
---|
63 | typedef typename vci_param::plen_t vci_plen_t; |
---|
64 | |
---|
65 | enum icache_fsm_state_e { |
---|
66 | ICACHE_IDLE, // 00 |
---|
67 | ICACHE_BIS, // 01 |
---|
68 | ICACHE_TLB1_READ, // 02 |
---|
69 | ICACHE_TLB1_LL_WAIT, // 03 |
---|
70 | ICACHE_TLB1_SC_WAIT, // 04 |
---|
71 | ICACHE_TLB1_UPDT_SEL, // 05 |
---|
72 | ICACHE_TLB1_UPDT, // 06 |
---|
73 | ICACHE_TLB2_READ, // 07 |
---|
74 | ICACHE_TLB2_LL_WAIT, // 08 |
---|
75 | ICACHE_TLB2_SC_WAIT, // 09 |
---|
76 | ICACHE_TLB2_UPDT_SEL, // 0a |
---|
77 | ICACHE_TLB2_UPDT, // 0b |
---|
78 | ICACHE_TLB_FLUSH, // 0c |
---|
79 | ICACHE_CACHE_FLUSH, // 0d |
---|
80 | ICACHE_TLB_INVAL, // 0e |
---|
81 | ICACHE_CACHE_INVAL, // 0f |
---|
82 | ICACHE_CACHE_INVAL_PA, // 10 |
---|
83 | ICACHE_MISS_WAIT, // 11 |
---|
84 | ICACHE_UNC_WAIT, // 12 |
---|
85 | ICACHE_MISS_UPDT, // 13 |
---|
86 | ICACHE_ERROR, // 14 |
---|
87 | ICACHE_CC_INVAL, // 15 |
---|
88 | ICACHE_TLB_CC_INVAL, // 16 |
---|
89 | }; |
---|
90 | |
---|
91 | enum dcache_fsm_state_e { |
---|
92 | DCACHE_IDLE, // 00 |
---|
93 | DCACHE_BIS, // 01 |
---|
94 | DCACHE_TLB1_READ, // 02 |
---|
95 | DCACHE_TLB1_LL_WAIT, // 03 |
---|
96 | DCACHE_TLB1_SC_WAIT, // 04 |
---|
97 | DCACHE_TLB1_UPDT_SEL, // 05 |
---|
98 | DCACHE_TLB1_UPDT, // 06 |
---|
99 | DCACHE_TLB2_READ, // 07 |
---|
100 | DCACHE_TLB2_LL_WAIT, // 08 |
---|
101 | DCACHE_TLB2_SC_WAIT, // 09 |
---|
102 | DCACHE_TLB2_UPDT_SEL, // 0a |
---|
103 | DCACHE_TLB2_UPDT, // 0b |
---|
104 | DCACHE_CTXT_SWITCH, // 0c |
---|
105 | DCACHE_ICACHE_FLUSH, // 0d |
---|
106 | DCACHE_DCACHE_FLUSH, // 0e |
---|
107 | DCACHE_ITLB_INVAL, // 0f |
---|
108 | DCACHE_DTLB_INVAL, // 10 |
---|
109 | DCACHE_ICACHE_INVAL, // 11 |
---|
110 | DCACHE_DCACHE_INVAL, // 12 |
---|
111 | DCACHE_ICACHE_INVAL_PA, // 13 |
---|
112 | DCACHE_DCACHE_INVAL_PA, // 14 |
---|
113 | DCACHE_DCACHE_SYNC, // 15 |
---|
114 | DCACHE_LL_DIRTY_WAIT, // 16 |
---|
115 | DCACHE_SC_DIRTY_WAIT, // 17 |
---|
116 | DCACHE_WRITE_UPDT, // 18 |
---|
117 | DCACHE_WRITE_DIRTY, // 19 |
---|
118 | DCACHE_WRITE_REQ, // 1a |
---|
119 | DCACHE_MISS_WAIT, // 1b |
---|
120 | DCACHE_MISS_UPDT, // 1c |
---|
121 | DCACHE_UNC_WAIT, // 1d |
---|
122 | DCACHE_ERROR, // 1e |
---|
123 | DCACHE_CC_CHECK, // 1f |
---|
124 | DCACHE_CC_INVAL, // 20 |
---|
125 | DCACHE_CC_UPDT, // 21 |
---|
126 | DCACHE_CC_NOP, // 22 |
---|
127 | DCACHE_TLB_CC_INVAL, // 23 |
---|
128 | }; |
---|
129 | |
---|
130 | enum cmd_fsm_state_e { |
---|
131 | CMD_IDLE, // 00 |
---|
132 | CMD_ITLB_READ, // 01 |
---|
133 | CMD_ITLB_ACC_LL, // 02 |
---|
134 | CMD_ITLB_ACC_SC, // 03 |
---|
135 | CMD_INS_MISS, // 04 |
---|
136 | CMD_INS_UNC, // 05 |
---|
137 | CMD_DTLB_READ, // 06 |
---|
138 | CMD_DTLB_ACC_LL, // 07 |
---|
139 | CMD_DTLB_ACC_SC, // 08 |
---|
140 | CMD_DTLB_DIRTY_LL, // 09 |
---|
141 | CMD_DTLB_DIRTY_SC, // 0a |
---|
142 | CMD_DATA_UNC, // 0b |
---|
143 | CMD_DATA_MISS, // 0c |
---|
144 | CMD_DATA_WRITE, // 0d |
---|
145 | CMD_INS_CLEANUP, // 0e |
---|
146 | CMD_DATA_CLEANUP, // 0f |
---|
147 | }; |
---|
148 | |
---|
149 | enum rsp_fsm_state_e { |
---|
150 | RSP_IDLE, // 00 |
---|
151 | RSP_ITLB_READ, // 01 |
---|
152 | RSP_ITLB_ACC_LL, // 02 |
---|
153 | RSP_ITLB_ACC_SC, // 03 |
---|
154 | RSP_INS_MISS, // 04 |
---|
155 | RSP_INS_UNC, // 05 |
---|
156 | RSP_DTLB_READ, // 06 |
---|
157 | RSP_DTLB_ACC_LL, // 07 |
---|
158 | RSP_DTLB_ACC_SC, // 08 |
---|
159 | RSP_DTLB_DIRTY_LL, // 09 |
---|
160 | RSP_DTLB_DIRTY_SC, // 0a |
---|
161 | RSP_DATA_MISS, // 0b |
---|
162 | RSP_DATA_UNC, // 0c |
---|
163 | RSP_DATA_WRITE, // 0d |
---|
164 | RSP_INS_CLEANUP, // 0e |
---|
165 | RSP_DATA_CLEANUP, // 0f |
---|
166 | }; |
---|
167 | |
---|
168 | enum tgt_fsm_state_e { |
---|
169 | TGT_IDLE, // 00 |
---|
170 | TGT_UPDT_WORD, // 01 |
---|
171 | TGT_UPDT_DATA, // 02 |
---|
172 | TGT_REQ_BROADCAST, // 03 |
---|
173 | TGT_REQ_ICACHE, // 04 |
---|
174 | TGT_REQ_DCACHE, // 05 |
---|
175 | TGT_RSP_BROADCAST, // 06 |
---|
176 | TGT_RSP_ICACHE, // 07 |
---|
177 | TGT_RSP_DCACHE, // 08 |
---|
178 | }; |
---|
179 | |
---|
180 | enum inval_itlb_fsm_state_e { |
---|
181 | INVAL_ITLB_IDLE, // 00 |
---|
182 | INVAL_ITLB_CHECK, // 01 |
---|
183 | INVAL_ITLB_INVAL, // 02 |
---|
184 | INVAL_ITLB_CLEAR, // 03 |
---|
185 | }; |
---|
186 | |
---|
187 | enum inval_dtlb_fsm_state_e { |
---|
188 | INVAL_DTLB_IDLE, // 00 |
---|
189 | INVAL_DTLB_CHECK, // 01 |
---|
190 | INVAL_DTLB_INVAL, // 02 |
---|
191 | INVAL_DTLB_CLEAR, // 03 |
---|
192 | }; |
---|
193 | |
---|
194 | // TLB Mode ITLB / DTLB / ICACHE / DCACHE |
---|
195 | enum { |
---|
196 | ALL_DEACTIVE = 0x0000, // TLBs disactive caches disactive |
---|
197 | INS_TLB_MASK = 0x8, |
---|
198 | DATA_TLB_MASK = 0x4, |
---|
199 | INS_CACHE_MASK = 0x2, |
---|
200 | DATA_CACHE_MASK = 0x1, |
---|
201 | }; |
---|
202 | |
---|
203 | // Error Type |
---|
204 | enum mmu_error_type_e { |
---|
205 | MMU_NONE = 0x0000, // None |
---|
206 | MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write access of Page fault on Page Table 1 (non fatal error) |
---|
207 | MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write access of Page fault on Page Table 2 (non fatal error) |
---|
208 | MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode (user error) |
---|
209 | MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access of write access to a non writable page (user error) |
---|
210 | MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write access of undefined external access address (user error) |
---|
211 | MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write access of Bus Error accessing Table 1 (kernel error) |
---|
212 | MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write access of Bus Error accessing Table 2 (kernel error) |
---|
213 | MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access (kernel error) |
---|
214 | MMU_READ_PT1_UNMAPPED = 0x1001, // Read access of Page fault on Page Table 1 (non fatal error) |
---|
215 | MMU_READ_PT2_UNMAPPED = 0x1002, // Read access of Page fault on Page Table 2 (non fatal error) |
---|
216 | MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read access of Protected access in user mode (user error) |
---|
217 | MMU_READ_EXEC_VIOLATION = 0x1010, // Exec access to a non exec page (user error) |
---|
218 | MMU_READ_UNDEFINED_XTN = 0x1020, // Read access of Undefined external access address (user error) |
---|
219 | MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read access of Bus Error in Table1 access (kernel error) |
---|
220 | MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read access of Bus Error in Table2 access (kernel error) |
---|
221 | MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read access of Bus Error in cache access (kernel error) |
---|
222 | }; |
---|
223 | |
---|
224 | // Cleanup Type |
---|
225 | enum { |
---|
226 | NONE, // reset |
---|
227 | CACHE_CLEANUP, // cache cleanup |
---|
228 | TLB_CLEANUP, // TLB cleanup |
---|
229 | }; |
---|
230 | |
---|
231 | public: |
---|
232 | sc_in<bool> p_clk; |
---|
233 | sc_in<bool> p_resetn; |
---|
234 | sc_in<bool> p_irq[iss_t::n_irq]; |
---|
235 | soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; |
---|
236 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
---|
237 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
---|
238 | |
---|
239 | private: |
---|
240 | // STRUCTURAL PARAMETERS |
---|
241 | soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table; |
---|
242 | const soclib::common::Segment m_segment; |
---|
243 | iss_t m_iss; |
---|
244 | const vci_srcid_t m_srcid_rw; |
---|
245 | const vci_srcid_t m_srcid_c; |
---|
246 | |
---|
247 | const size_t m_itlb_ways; |
---|
248 | const size_t m_itlb_sets; |
---|
249 | |
---|
250 | const size_t m_dtlb_ways; |
---|
251 | const size_t m_dtlb_sets; |
---|
252 | |
---|
253 | const size_t m_icache_ways; |
---|
254 | const size_t m_icache_sets; |
---|
255 | const size_t m_icache_yzmask; |
---|
256 | const size_t m_icache_words; |
---|
257 | |
---|
258 | const size_t m_dcache_ways; |
---|
259 | const size_t m_dcache_sets; |
---|
260 | const size_t m_dcache_yzmask; |
---|
261 | const size_t m_dcache_words; |
---|
262 | |
---|
263 | const size_t m_write_buf_size; |
---|
264 | const size_t m_paddr_nbits; |
---|
265 | |
---|
266 | // instruction and data vcache tlb instances |
---|
267 | soclib::caba::GenericCcTlb<paddr_t> icache_tlb; |
---|
268 | soclib::caba::GenericCcTlb<paddr_t> dcache_tlb; |
---|
269 | |
---|
270 | sc_signal<vaddr_t> r_mmu_ptpr; // page table pointer register |
---|
271 | sc_signal<int> r_mmu_mode; // tlb mode register |
---|
272 | sc_signal<int> r_mmu_params; // mmu parameters register |
---|
273 | sc_signal<int> r_mmu_release; // mmu release register |
---|
274 | sc_signal<int> r_mmu_word_lo; // mmu misc data low |
---|
275 | sc_signal<int> r_mmu_word_hi; // mmu mmu misc data hight |
---|
276 | |
---|
277 | // DCACHE FSM REGISTERS |
---|
278 | sc_signal<int> r_dcache_fsm; // state register |
---|
279 | sc_signal<paddr_t> r_dcache_paddr_save; // physical address |
---|
280 | sc_signal<data_t> r_dcache_wdata_save; // write data |
---|
281 | sc_signal<data_t> r_dcache_rdata_save; // read data |
---|
282 | sc_signal<type_t> r_dcache_type_save; // access type |
---|
283 | sc_signal<vci_be_t> r_dcache_be_save; // byte enable |
---|
284 | sc_signal<bool> r_dcache_cached_save; // used by the write buffer |
---|
285 | sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of tlb miss |
---|
286 | sc_signal<bool> r_dcache_dirty_save; // used for TLB dirty bit update |
---|
287 | sc_signal<size_t> r_dcache_tlb_set_save; // used for TLB dirty bit update |
---|
288 | sc_signal<size_t> r_dcache_tlb_way_save; // used for TLB dirty bit update |
---|
289 | sc_signal<vaddr_t> r_dcache_id1_save; // used by the PT1 bypass |
---|
290 | sc_signal<paddr_t> r_dcache_ptba_save; // used by the PT1 bypass |
---|
291 | sc_signal<bool> r_dcache_ptba_ok; // used by the PT1 bypass |
---|
292 | sc_signal<data_t> r_dcache_pte_update; // used for page table update |
---|
293 | sc_signal<tag_t> r_dcache_ppn_save; // used for speculative cache access |
---|
294 | sc_signal<tag_t> r_dcache_vpn_save; // used for speculative cache access |
---|
295 | sc_signal<bool> r_dtlb_translation_valid; // used for speculative address |
---|
296 | sc_signal<bool> r_dcache_buf_unc_valid; // used for uncached read |
---|
297 | sc_signal<bool> r_dcache_hit_p_save; // used to save hit_p in case BIS |
---|
298 | |
---|
299 | sc_signal<data_t> r_dcache_error_type; // software visible register |
---|
300 | sc_signal<vaddr_t> r_dcache_bad_vaddr; // software visible register |
---|
301 | |
---|
302 | sc_signal<bool> r_dcache_miss_req; // used for cached read miss |
---|
303 | sc_signal<bool> r_dcache_unc_req; // used for uncached read miss |
---|
304 | sc_signal<bool> r_dcache_write_req; // used for write |
---|
305 | sc_signal<bool> r_dcache_tlb_read_req; // used for tlb ptba or pte read |
---|
306 | sc_signal<bool> r_dcache_tlb_first_req; // used for tlb ptba or pte read |
---|
307 | sc_signal<bool> r_dcache_tlb_ll_acc_req; // used for tlb entry type update |
---|
308 | sc_signal<bool> r_dcache_tlb_sc_acc_req; // used for tlb entry type update |
---|
309 | sc_signal<bool> r_dcache_tlb_ll_dirty_req; // used for tlb dirty bit update |
---|
310 | sc_signal<bool> r_dcache_tlb_sc_dirty_req; // used for tlb dirty bit update |
---|
311 | sc_signal<bool> r_dcache_sc_updt_dirty; // used for tlb dirty bit update |
---|
312 | sc_signal<bool> r_dcache_tlb_sc_fail; // used for tlb entry sc failed |
---|
313 | sc_signal<bool> r_dcache_tlb_ptba_read; // used for tlb ptba read when write dirty bit |
---|
314 | sc_signal<bool> r_dcache_xtn_req; // used for xtn write for ICACHE |
---|
315 | |
---|
316 | // coherence registers |
---|
317 | sc_signal<int> r_dcache_fsm_save; // state save register |
---|
318 | sc_signal<size_t> r_dcache_way; |
---|
319 | sc_signal<size_t> r_dcache_set; |
---|
320 | sc_signal<bool> r_dcache_cleanup_req; |
---|
321 | sc_signal<data_t> r_dcache_cleanup_line; |
---|
322 | sc_signal<int> r_dcache_cleanup_type; |
---|
323 | sc_signal<bool> r_dcache_inval_rsp; |
---|
324 | |
---|
325 | // ICACHE FSM REGISTERS |
---|
326 | sc_signal<int> r_icache_fsm; // state register |
---|
327 | sc_signal<paddr_t> r_icache_paddr_save; // physical address |
---|
328 | sc_signal<vaddr_t> r_icache_id1_save; // used by the PT1 bypass |
---|
329 | sc_signal<paddr_t> r_icache_ptba_save; // used by the PT1 bypass |
---|
330 | sc_signal<bool> r_icache_ptba_ok; // used by the PT1 bypass |
---|
331 | sc_signal<data_t> r_icache_pte_update; // used for page table update |
---|
332 | sc_signal<tag_t> r_icache_ppn_save; // used for speculative cache access |
---|
333 | sc_signal<tag_t> r_icache_vpn_save; // used for speculative cache access |
---|
334 | sc_signal<bool> r_itlb_translation_valid; // used for speculative physical address |
---|
335 | sc_signal<bool> r_icache_buf_unc_valid; // used for uncached read |
---|
336 | sc_signal<vaddr_t> r_icache_vaddr_req; // used by the PT1 bypass |
---|
337 | |
---|
338 | sc_signal<data_t> r_icache_error_type; // software visible registers |
---|
339 | sc_signal<vaddr_t> r_icache_bad_vaddr; // software visible registers |
---|
340 | |
---|
341 | sc_signal<bool> r_icache_miss_req; // used for cached read miss |
---|
342 | sc_signal<bool> r_icache_unc_req; // used for uncached read miss |
---|
343 | sc_signal<bool> r_icache_tlb_read_req; // used for tlb ptba or pte read |
---|
344 | sc_signal<bool> r_icache_tlb_first_req; // used for tlb ptba or pte read |
---|
345 | sc_signal<bool> r_icache_tlb_ll_req; // used for tlb entry type update |
---|
346 | sc_signal<bool> r_icache_tlb_sc_req; // used for tlb entry type update |
---|
347 | sc_signal<bool> r_icache_tlb_sc_fail; // used for tlb entry sc failed |
---|
348 | |
---|
349 | // coherence registers |
---|
350 | sc_signal<int> r_icache_fsm_save; |
---|
351 | sc_signal<size_t> r_icache_way; |
---|
352 | sc_signal<size_t> r_icache_set; |
---|
353 | sc_signal<bool> r_icache_cleanup_req; |
---|
354 | sc_signal<data_t> r_icache_cleanup_line; |
---|
355 | sc_signal<int> r_icache_cleanup_type; |
---|
356 | sc_signal<bool> r_icache_inval_rsp; |
---|
357 | |
---|
358 | // VCI_CMD FSM REGISTERS |
---|
359 | sc_signal<int> r_vci_cmd_fsm; |
---|
360 | sc_signal<size_t> r_vci_cmd_min; |
---|
361 | sc_signal<size_t> r_vci_cmd_max; |
---|
362 | sc_signal<size_t> r_vci_cmd_cpt; |
---|
363 | |
---|
364 | // VCI_RSP FSM REGISTERS |
---|
365 | sc_signal<int> r_vci_rsp_fsm; |
---|
366 | sc_signal<size_t> r_vci_rsp_cpt; |
---|
367 | sc_signal<bool> r_vci_rsp_ins_error; |
---|
368 | sc_signal<bool> r_vci_rsp_data_error; |
---|
369 | |
---|
370 | data_t *r_icache_miss_buf; |
---|
371 | data_t *r_dcache_miss_buf; |
---|
372 | |
---|
373 | // VCI_TGT FSM REGISTERS |
---|
374 | data_t *r_tgt_buf; |
---|
375 | bool *r_tgt_val; |
---|
376 | |
---|
377 | sc_signal<int> r_vci_tgt_fsm; |
---|
378 | sc_signal<paddr_t> r_tgt_addr; |
---|
379 | sc_signal<size_t> r_tgt_word; |
---|
380 | sc_signal<bool> r_tgt_update; |
---|
381 | sc_signal<bool> r_tgt_broadcast; |
---|
382 | sc_signal<vci_srcid_t> r_tgt_srcid; |
---|
383 | sc_signal<vci_pktid_t> r_tgt_pktid; |
---|
384 | sc_signal<vci_trdid_t> r_tgt_trdid; |
---|
385 | sc_signal<vci_plen_t> r_tgt_plen; |
---|
386 | sc_signal<bool> r_tgt_icache_req; |
---|
387 | sc_signal<bool> r_tgt_dcache_req; |
---|
388 | sc_signal<bool> r_tgt_icache_rsp; |
---|
389 | sc_signal<bool> r_tgt_dcache_rsp; |
---|
390 | sc_signal<size_t> r_ccinval_itlb_cpt; |
---|
391 | sc_signal<size_t> r_ccinval_dtlb_cpt; |
---|
392 | |
---|
393 | // INVAL CHECK FSM |
---|
394 | sc_signal<int> r_inval_itlb_fsm; |
---|
395 | sc_signal<bool> r_icache_tlb_inval_req; |
---|
396 | sc_signal<bool> r_itlb_cc_check_end; |
---|
397 | sc_signal<size_t> r_ccinval_itlb_way; |
---|
398 | sc_signal<size_t> r_ccinval_itlb_set; |
---|
399 | sc_signal<bool> r_icache_inval_tlb_rsp; |
---|
400 | sc_signal<paddr_t> r_icache_tlb_nline; |
---|
401 | sc_signal<bool> r_icache_cc_hit_t; |
---|
402 | |
---|
403 | sc_signal<int> r_inval_dtlb_fsm; |
---|
404 | sc_signal<bool> r_dcache_tlb_inval_req; |
---|
405 | sc_signal<bool> r_dtlb_cc_check_end; |
---|
406 | sc_signal<size_t> r_ccinval_dtlb_way; |
---|
407 | sc_signal<size_t> r_ccinval_dtlb_set; |
---|
408 | sc_signal<bool> r_dcache_inval_tlb_rsp; |
---|
409 | sc_signal<paddr_t> r_dcache_tlb_nline; |
---|
410 | sc_signal<bool> r_dcache_cc_hit_t; |
---|
411 | |
---|
412 | WriteBuffer<paddr_t> r_wbuf; |
---|
413 | GenericCache<paddr_t> r_icache; |
---|
414 | GenericCache<paddr_t> r_dcache; |
---|
415 | |
---|
416 | // Activity counters |
---|
417 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
---|
418 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
---|
419 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
---|
420 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
---|
421 | |
---|
422 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
---|
423 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
---|
424 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
---|
425 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
---|
426 | |
---|
427 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
---|
428 | uint32_t m_cpt_total_cycles; // total number of cycles |
---|
429 | |
---|
430 | // Cache activity counters |
---|
431 | uint32_t m_cpt_read; // total number of read data |
---|
432 | uint32_t m_cpt_write; // total number of write data |
---|
433 | uint32_t m_cpt_data_miss; // number of read miss |
---|
434 | uint32_t m_cpt_ins_miss; // number of instruction miss |
---|
435 | uint32_t m_cpt_unc_read; // number of read uncached |
---|
436 | uint32_t m_cpt_write_cached; // number of cached write |
---|
437 | uint32_t m_cpt_ins_read; // number of instruction read |
---|
438 | |
---|
439 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer of cache |
---|
440 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss of cache |
---|
441 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read of cache |
---|
442 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss of cache |
---|
443 | |
---|
444 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
---|
445 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
---|
446 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
---|
447 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
---|
448 | uint32_t m_cpt_icache_unc_transaction; // number of VCI instruction uncached transactions |
---|
449 | |
---|
450 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
---|
451 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
---|
452 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
---|
453 | uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions |
---|
454 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
---|
455 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
---|
456 | |
---|
457 | // TLB activity counters |
---|
458 | uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read |
---|
459 | uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss |
---|
460 | uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc |
---|
461 | uint32_t m_cpt_data_tlb_read; // number of data tlb read |
---|
462 | uint32_t m_cpt_data_tlb_miss; // number of data tlb miss |
---|
463 | uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc |
---|
464 | uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty |
---|
465 | |
---|
466 | uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss |
---|
467 | uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss |
---|
468 | uint32_t m_cost_ins_tlb_update_acc_frz; // number of cycles for instruction tlb flush |
---|
469 | uint32_t m_cost_data_tlb_update_acc_frz; // number of cycles for data tlb flush |
---|
470 | uint32_t m_cost_data_tlb_update_dirty_frz; // number of cycles for instruction cache flush |
---|
471 | |
---|
472 | uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions |
---|
473 | uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions |
---|
474 | uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions |
---|
475 | uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions |
---|
476 | uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions |
---|
477 | uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions |
---|
478 | uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions |
---|
479 | uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions |
---|
480 | |
---|
481 | uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions |
---|
482 | uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions |
---|
483 | uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions |
---|
484 | uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions |
---|
485 | uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions |
---|
486 | uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions |
---|
487 | uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions |
---|
488 | uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions |
---|
489 | |
---|
490 | uint32_t m_cpt_cc_cleanup_ins; |
---|
491 | uint32_t m_cpt_cc_cleanup_data; |
---|
492 | uint32_t m_cpt_icleanup_transaction; |
---|
493 | uint32_t m_cpt_dcleanup_transaction; |
---|
494 | uint32_t m_cost_icleanup_transaction; |
---|
495 | uint32_t m_cost_dcleanup_transaction; |
---|
496 | |
---|
497 | uint32_t m_cpt_cc_update_data; // number of coherence update data packets |
---|
498 | uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets |
---|
499 | uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets |
---|
500 | uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets |
---|
501 | |
---|
502 | protected: |
---|
503 | SC_HAS_PROCESS(VciCcVCacheWrapperV1); |
---|
504 | |
---|
505 | public: |
---|
506 | VciCcVCacheWrapperV1( |
---|
507 | sc_module_name insname, |
---|
508 | int proc_id, |
---|
509 | const soclib::common::MappingTable &mtp, |
---|
510 | const soclib::common::MappingTable &mtc, |
---|
511 | const soclib::common::IntTab &initiator_index_rw, |
---|
512 | const soclib::common::IntTab &initiator_index_c, |
---|
513 | const soclib::common::IntTab &target_index, |
---|
514 | size_t itlb_ways, |
---|
515 | size_t itlb_sets, |
---|
516 | size_t dtlb_ways, |
---|
517 | size_t dtlb_sets, |
---|
518 | size_t icache_ways, |
---|
519 | size_t icache_sets, |
---|
520 | size_t icache_words, |
---|
521 | size_t dcache_ways, |
---|
522 | size_t dcache_sets, |
---|
523 | size_t dcache_words, |
---|
524 | size_t write_buf_size ); |
---|
525 | |
---|
526 | ~VciCcVCacheWrapperV1(); |
---|
527 | |
---|
528 | void print_cpi(); |
---|
529 | void print_stats(); |
---|
530 | |
---|
531 | private: |
---|
532 | void transition(); |
---|
533 | void genMoore(); |
---|
534 | |
---|
535 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
---|
536 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
---|
537 | }; |
---|
538 | |
---|
539 | }} |
---|
540 | |
---|
541 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V1_H */ |
---|
542 | |
---|
543 | // Local Variables: |
---|
544 | // tab-width: 4 |
---|
545 | // c-basic-offset: 4 |
---|
546 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
547 | // indent-tabs-mode: nil |
---|
548 | // End: |
---|
549 | |
---|
550 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
551 | |
---|