Changeset 119 for trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h
- Timestamp:
- Dec 6, 2010, 6:12:46 AM (14 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h
r48 r119 69 69 ICACHE_TLB1_LL_WAIT, // 03 70 70 ICACHE_TLB1_SC_WAIT, // 04 71 ICACHE_TLB1_UPDT, // 05 72 ICACHE_TLB2_READ, // 06 73 ICACHE_TLB2_LL_WAIT, // 07 74 ICACHE_TLB2_SC_WAIT, // 08 75 ICACHE_TLB2_UPDT, // 09 76 ICACHE_TLB_FLUSH, // 0a 77 ICACHE_CACHE_FLUSH, // 0b 78 ICACHE_TLB_INVAL, // 0c 79 ICACHE_CACHE_INVAL, // 0d 80 ICACHE_CACHE_INVAL_PA, // 0e 81 ICACHE_MISS_WAIT, // 0f 82 ICACHE_UNC_WAIT, // 10 83 ICACHE_MISS_UPDT, // 11 84 ICACHE_ERROR, // 12 85 ICACHE_CC_INVAL, // 13 86 ICACHE_TLB_CC_INVAL, // 14 71 ICACHE_TLB1_UPDT_SEL, // 05 72 ICACHE_TLB1_UPDT, // 06 73 ICACHE_TLB2_READ, // 07 74 ICACHE_TLB2_LL_WAIT, // 08 75 ICACHE_TLB2_SC_WAIT, // 09 76 ICACHE_TLB2_UPDT_SEL, // 0a 77 ICACHE_TLB2_UPDT, // 0b 78 ICACHE_TLB_FLUSH, // 0c 79 ICACHE_CACHE_FLUSH, // 0d 80 ICACHE_TLB_INVAL, // 0e 81 ICACHE_CACHE_INVAL, // 0f 82 ICACHE_CACHE_INVAL_PA, // 10 83 ICACHE_MISS_WAIT, // 11 84 ICACHE_UNC_WAIT, // 12 85 ICACHE_MISS_UPDT, // 13 86 ICACHE_ERROR, // 14 87 ICACHE_CC_INVAL, // 15 88 ICACHE_TLB_CC_INVAL, // 16 87 89 }; 88 90 … … 93 95 DCACHE_TLB1_LL_WAIT, // 03 94 96 DCACHE_TLB1_SC_WAIT, // 04 95 DCACHE_TLB1_UPDT, // 05 96 DCACHE_TLB2_READ, // 06 97 DCACHE_TLB2_LL_WAIT, // 07 98 DCACHE_TLB2_SC_WAIT, // 08 99 DCACHE_TLB2_UPDT, // 09 100 DCACHE_CTXT_SWITCH, // 0a 101 DCACHE_ICACHE_FLUSH, // 0b 102 DCACHE_DCACHE_FLUSH, // 0c 103 DCACHE_ITLB_INVAL, // 0d 104 DCACHE_DTLB_INVAL, // 0e 105 DCACHE_ICACHE_INVAL, // 0f 106 DCACHE_DCACHE_INVAL, // 10 107 DCACHE_ICACHE_INVAL_PA, // 0f 108 DCACHE_DCACHE_INVAL_PA, // 10 109 DCACHE_DCACHE_SYNC, // 11 110 DCACHE_LL_DIRTY_WAIT, // 12 111 DCACHE_SC_DIRTY_WAIT, // 13 112 DCACHE_WRITE_UPDT, // 14 113 DCACHE_WRITE_DIRTY, // 15 114 DCACHE_WRITE_REQ, // 16 115 DCACHE_MISS_WAIT, // 17 116 DCACHE_MISS_UPDT, // 18 117 DCACHE_UNC_WAIT, // 19 118 DCACHE_ERROR, // 1a 119 DCACHE_CC_CHECK, // 1b 120 DCACHE_CC_INVAL, // 1c 121 DCACHE_CC_UPDT, // 1d 122 DCACHE_CC_NOP, // 1e 123 DCACHE_TLB_CC_INVAL, // 1f 97 DCACHE_TLB1_UPDT_SEL, // 05 98 DCACHE_TLB1_UPDT, // 06 99 DCACHE_TLB2_READ, // 07 100 DCACHE_TLB2_LL_WAIT, // 08 101 DCACHE_TLB2_SC_WAIT, // 09 102 DCACHE_TLB2_UPDT_SEL, // 0a 103 DCACHE_TLB2_UPDT, // 0b 104 DCACHE_CTXT_SWITCH, // 0c 105 DCACHE_ICACHE_FLUSH, // 0d 106 DCACHE_DCACHE_FLUSH, // 0e 107 DCACHE_ITLB_INVAL, // 0f 108 DCACHE_DTLB_INVAL, // 10 109 DCACHE_ICACHE_INVAL, // 11 110 DCACHE_DCACHE_INVAL, // 12 111 DCACHE_ICACHE_INVAL_PA, // 13 112 DCACHE_DCACHE_INVAL_PA, // 14 113 DCACHE_DCACHE_SYNC, // 15 114 DCACHE_LL_DIRTY_WAIT, // 16 115 DCACHE_SC_DIRTY_WAIT, // 17 116 DCACHE_WRITE_UPDT, // 18 117 DCACHE_WRITE_DIRTY, // 19 118 DCACHE_WRITE_REQ, // 1a 119 DCACHE_MISS_WAIT, // 1b 120 DCACHE_MISS_UPDT, // 1c 121 DCACHE_UNC_WAIT, // 1d 122 DCACHE_ERROR, // 1e 123 DCACHE_CC_CHECK, // 1f 124 DCACHE_CC_INVAL, // 20 125 DCACHE_CC_UPDT, // 21 126 DCACHE_CC_NOP, // 22 127 DCACHE_TLB_CC_INVAL, // 23 124 128 }; 125 129 … … 304 308 sc_signal<bool> r_dcache_tlb_sc_acc_req; // used for tlb entry type update 305 309 sc_signal<bool> r_dcache_tlb_ll_dirty_req; // used for tlb dirty bit update 306 sc_signal<bool> r_dcache_tlb_sc_dirty_req; // used for tlb dirty bit update 310 sc_signal<bool> r_dcache_tlb_sc_dirty_req; // used for tlb dirty bit update 311 sc_signal<bool> r_dcache_sc_updt_dirty; // used for tlb dirty bit update 307 312 sc_signal<bool> r_dcache_tlb_sc_fail; // used for tlb entry sc failed 308 313 sc_signal<bool> r_dcache_tlb_ptba_read; // used for tlb ptba read when write dirty bit
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