[2] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, SoC |
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| 24 | * Alain Greiner <alain.greiner@lip6.fr>, 2008 |
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| 25 | * |
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| 26 | * Maintainers: alain |
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| 27 | */ |
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| 28 | |
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| 29 | #ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H |
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| 30 | #define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H |
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| 31 | |
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| 32 | #include <inttypes.h> |
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| 33 | #include <systemc> |
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| 34 | #include "caba_base_module.h" |
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| 35 | #include "multi_write_buffer.h" |
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| 36 | #include "generic_cache.h" |
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| 37 | #include "vci_initiator.h" |
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| 38 | #include "vci_target.h" |
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| 39 | #include "mapping_table.h" |
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| 40 | #include "static_assert.h" |
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| 41 | |
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| 42 | |
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| 43 | namespace soclib { |
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| 44 | namespace caba { |
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| 45 | |
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| 46 | using namespace sc_core; |
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| 47 | |
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| 48 | //////////////////////////////////////////// |
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| 49 | template<typename vci_param, typename iss_t> |
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| 50 | class VciCcXCacheWrapperMulti |
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| 51 | /////////////////////////////////////////// |
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| 52 | : public soclib::caba::BaseModule |
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| 53 | { |
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| 54 | typedef uint32_t data_t; |
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| 55 | typedef uint32_t be_t; |
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| 56 | typedef typename vci_param::fast_addr_t addr_t; |
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| 57 | |
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| 58 | enum dcache_fsm_state_e { |
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| 59 | DCACHE_IDLE, |
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| 60 | DCACHE_WRITE_UPDT, |
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| 61 | DCACHE_WRITE_REQ, |
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| 62 | DCACHE_MISS_SELECT, |
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| 63 | DCACHE_MISS_CLEANUP, |
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| 64 | DCACHE_MISS_WAIT, |
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| 65 | DCACHE_MISS_UPDT, |
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| 66 | DCACHE_UNC_WAIT, |
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[45] | 67 | DCACHE_UNC_GO, |
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[2] | 68 | DCACHE_INVAL, |
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| 69 | DCACHE_SYNC, |
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| 70 | DCACHE_ERROR, |
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| 71 | DCACHE_CC_CHECK, |
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| 72 | DCACHE_CC_INVAL, |
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| 73 | DCACHE_CC_UPDT, |
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| 74 | }; |
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| 75 | |
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| 76 | enum icache_fsm_state_e { |
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| 77 | ICACHE_IDLE, |
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| 78 | ICACHE_MISS_SELECT, |
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| 79 | ICACHE_MISS_CLEANUP, |
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| 80 | ICACHE_MISS_WAIT, |
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| 81 | ICACHE_MISS_UPDT, |
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| 82 | ICACHE_UNC_WAIT, |
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[45] | 83 | ICACHE_UNC_GO, |
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[2] | 84 | ICACHE_ERROR, |
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| 85 | ICACHE_CC_CHECK, |
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| 86 | ICACHE_CC_INVAL, |
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| 87 | ICACHE_CC_UPDT, |
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| 88 | }; |
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| 89 | |
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| 90 | enum cmd_fsm_state_e { |
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| 91 | CMD_IDLE, |
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| 92 | CMD_INS_MISS, |
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| 93 | CMD_INS_UNC, |
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| 94 | CMD_DATA_MISS, |
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| 95 | CMD_DATA_UNC, |
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| 96 | CMD_DATA_WRITE, |
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| 97 | }; |
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| 98 | |
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| 99 | enum rsp_fsm_state_e { |
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| 100 | RSP_IDLE, |
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| 101 | RSP_INS_MISS, |
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| 102 | RSP_INS_UNC, |
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| 103 | RSP_DATA_MISS, |
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| 104 | RSP_DATA_UNC, |
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| 105 | RSP_DATA_WRITE, |
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| 106 | }; |
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| 107 | |
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| 108 | enum tgt_fsm_state_e { |
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| 109 | TGT_IDLE, |
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| 110 | TGT_UPDT_WORD, |
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| 111 | TGT_UPDT_DATA, |
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| 112 | TGT_REQ_BROADCAST, |
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| 113 | TGT_REQ_ICACHE, |
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| 114 | TGT_REQ_DCACHE, |
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| 115 | TGT_RSP_BROADCAST, |
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| 116 | TGT_RSP_ICACHE, |
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| 117 | TGT_RSP_DCACHE, |
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| 118 | }; |
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| 119 | |
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| 120 | enum cleanup_fsm_state_e { |
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[45] | 121 | CLEANUP_IDLE, |
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| 122 | CLEANUP_DCACHE, |
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| 123 | CLEANUP_ICACHE, |
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[2] | 124 | }; |
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| 125 | |
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| 126 | enum transaction_type_e { |
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| 127 | TYPE_DATA_UNC = 0, |
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| 128 | TYPE_DATA_MISS = 1, |
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| 129 | TYPE_INS_UNC = 2, |
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| 130 | TYPE_INS_MISS = 3, |
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| 131 | }; |
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| 132 | |
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| 133 | public: |
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| 134 | |
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| 135 | // PORTS |
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| 136 | sc_in<bool> p_clk; |
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| 137 | sc_in<bool> p_resetn; |
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| 138 | sc_in<bool> p_irq[iss_t::n_irq]; |
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| 139 | soclib::caba::VciInitiator<vci_param> p_vci_ini_d; |
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| 140 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
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| 141 | soclib::caba::VciTarget<vci_param> p_vci_tgt_c; |
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| 142 | |
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| 143 | private: |
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| 144 | |
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| 145 | // STRUCTURAL PARAMETERS |
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| 146 | const soclib::common::AddressDecodingTable<addr_t, bool> m_cacheability_table; |
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| 147 | const soclib::common::Segment m_segment; |
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| 148 | iss_t m_iss; |
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| 149 | const uint32_t m_srcid_d; |
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| 150 | const uint32_t m_srcid_c; |
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| 151 | |
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| 152 | const size_t m_dcache_ways; |
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| 153 | const size_t m_dcache_words; |
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| 154 | const size_t m_dcache_yzmask; |
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| 155 | const size_t m_icache_ways; |
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| 156 | const size_t m_icache_words; |
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| 157 | const size_t m_icache_yzmask; |
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| 158 | |
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| 159 | // REGISTERS |
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| 160 | sc_signal<int> r_dcache_fsm; // controls the data cache interface |
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| 161 | sc_signal<int> r_dcache_fsm_save; |
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| 162 | sc_signal<addr_t> r_dcache_addr_save; |
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| 163 | sc_signal<data_t> r_dcache_wdata_save; |
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| 164 | sc_signal<data_t> r_dcache_rdata_save; |
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| 165 | sc_signal<int> r_dcache_type_save; |
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| 166 | sc_signal<be_t> r_dcache_be_save; |
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| 167 | sc_signal<addr_t> r_dcache_cleanup_save; // victim line index for cleanup |
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| 168 | sc_signal<size_t> r_dcache_way_save; // selected slot for the replacement |
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| 169 | sc_signal<bool> r_dcache_cleanup_req; // send a cleanup request to CLEANUP FSM |
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| 170 | sc_signal<addr_t> r_dcache_cleanup_line; // define the victim line index |
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| 171 | sc_signal<bool> r_dcache_miss_req; // send a miss request to CMD FSM |
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| 172 | sc_signal<bool> r_dcache_unc_req; // send a uncached request to CMD FSM |
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| 173 | sc_signal<bool> r_dcache_inval_pending; // external inval or update request pending |
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| 174 | |
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| 175 | sc_signal<int> r_icache_fsm; // controls the instruction cache interface |
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| 176 | sc_signal<int> r_icache_fsm_save; |
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| 177 | sc_signal<addr_t> r_icache_addr_save; |
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| 178 | sc_signal<addr_t> r_icache_cleanup_save; // victim line index for cleanup |
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| 179 | sc_signal<size_t> r_icache_way_save; // selected slot for the replacement |
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| 180 | sc_signal<bool> r_icache_miss_req; // send a miss request to to CMD FSM |
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| 181 | sc_signal<bool> r_icache_unc_req; // send an uncached request to CMD FSM |
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| 182 | sc_signal<bool> r_icache_cleanup_req; // send a cleanup request to CLEANUP FSM |
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| 183 | sc_signal<addr_t> r_icache_cleanup_line; // define the victim line index |
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| 184 | sc_signal<bool> r_icache_inval_pending; // external inval or update request pending |
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| 185 | |
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| 186 | sc_signal<int> r_cmd_fsm; // controls the command on the direct network |
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| 187 | sc_signal<size_t> r_cmd_min; |
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| 188 | sc_signal<size_t> r_cmd_max; |
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| 189 | sc_signal<size_t> r_cmd_cpt; |
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| 190 | |
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| 191 | sc_signal<int> r_rsp_fsm; // controls the response on the direct network |
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| 192 | sc_signal<bool> r_rsp_ins_error; // signals an error to the ICACHE FSM |
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| 193 | sc_signal<bool> r_rsp_data_error; // signals an error to the DCACHE FSM |
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| 194 | sc_signal<size_t> r_rsp_cpt; |
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| 195 | sc_signal<bool> r_rsp_ins_ok; // signals an available data to the ICACHE FSM |
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| 196 | sc_signal<bool> r_rsp_data_ok; // signals an available data to the DCACHE FSM; |
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| 197 | |
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| 198 | data_t *r_icache_miss_buf; |
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| 199 | data_t *r_dcache_miss_buf; |
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| 200 | |
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| 201 | data_t *r_tgt_buf; |
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| 202 | bool *r_tgt_val; |
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| 203 | |
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| 204 | sc_signal<int> r_tgt_fsm; // controls the target port of the coherence network |
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| 205 | sc_signal<addr_t> r_tgt_addr; |
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| 206 | sc_signal<size_t> r_tgt_word; |
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| 207 | sc_signal<bool> r_tgt_update; |
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| 208 | sc_signal<bool> r_tgt_data; |
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| 209 | sc_signal<bool> r_tgt_brdcast; |
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| 210 | sc_signal<size_t> r_tgt_srcid; |
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| 211 | sc_signal<size_t> r_tgt_pktid; |
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| 212 | sc_signal<size_t> r_tgt_trdid; |
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| 213 | sc_signal<size_t> r_tgt_plen; |
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| 214 | sc_signal<bool> r_tgt_icache_req; // coherence request from TGT FSM to ICACHE FSM |
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| 215 | sc_signal<bool> r_tgt_dcache_req; // coherence request from TGT FSM to DCACHE FSM |
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| 216 | sc_signal<bool> r_tgt_icache_rsp; // response from ICACHE FSM to TGT FSM : true == hit |
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| 217 | sc_signal<bool> r_tgt_dcache_rsp; // response from DCACHE FSM to TGT FSM : true == hit |
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| 218 | |
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| 219 | sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network |
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| 220 | |
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| 221 | MultiWriteBuffer<addr_t> r_wbuf; |
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| 222 | GenericCache<addr_t> r_icache; |
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| 223 | GenericCache<addr_t> r_dcache; |
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| 224 | |
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| 225 | // Activity counters |
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| 226 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
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| 227 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
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| 228 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
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| 229 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
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| 230 | |
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| 231 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
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| 232 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
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| 233 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
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| 234 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
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| 235 | |
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[45] | 236 | uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets |
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| 237 | uint32_t m_cpt_cc_update_data; // number of coherence data update packets |
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| 238 | uint32_t m_cpt_cc_update_ins; // number of coherence instruction update packets |
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| 239 | uint32_t m_cpt_cc_inval_data; // number of coherence data inval packets |
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| 240 | uint32_t m_cpt_cc_inval_ins; // number of coherence instruction inval packets |
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| 241 | uint32_t m_cpt_cc_cleanup_data; // number of coherence data cleanup packets |
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| 242 | uint32_t m_cpt_cc_cleanup_ins; // number of coherence instruction cleanup packets |
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[2] | 243 | |
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| 244 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
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| 245 | uint32_t m_cpt_total_cycles; // total number of cycles |
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| 246 | |
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[45] | 247 | uint32_t m_cpt_read; // total number of read requests |
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| 248 | uint32_t m_cpt_write; // total number of write requests |
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| 249 | uint32_t m_cpt_write_cached; // number of cached write requests |
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| 250 | uint32_t m_cpt_data_unc; // number of uncachable data requests |
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| 251 | uint32_t m_cpt_ins_unc; // number of uncachable instruction requests |
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| 252 | uint32_t m_cpt_ll; // number of ll requests |
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| 253 | uint32_t m_cpt_sc; // number of sc requests |
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[2] | 254 | uint32_t m_cpt_data_miss; // number of read miss |
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| 255 | uint32_t m_cpt_ins_miss; // number of instruction miss |
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| 256 | |
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| 257 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
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| 258 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
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[45] | 259 | uint32_t m_cost_unc_frz; // number of frozen cycles related to uncached read |
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[2] | 260 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
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| 261 | |
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| 262 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
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| 263 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
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[45] | 264 | uint32_t m_cpt_data_unc_transaction; // number of VCI instruction uncached transactions |
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| 265 | uint32_t m_cpt_ins_unc_transaction; // number of VCI data uncached transactions |
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[2] | 266 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
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| 267 | |
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| 268 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
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| 269 | |
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| 270 | protected: |
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| 271 | SC_HAS_PROCESS(VciCcXCacheWrapperMulti); |
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| 272 | |
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| 273 | public: |
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| 274 | |
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| 275 | VciCcXCacheWrapperMulti( |
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| 276 | sc_module_name insname, |
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| 277 | int proc_id, |
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| 278 | const soclib::common::MappingTable &mtp, |
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| 279 | const soclib::common::MappingTable &mtc, |
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| 280 | const soclib::common::IntTab &initiator_index_p, |
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| 281 | const soclib::common::IntTab &initiator_index_c, |
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| 282 | const soclib::common::IntTab &target_index_c, |
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| 283 | size_t icache_ways, |
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| 284 | size_t icache_sets, |
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| 285 | size_t icache_words, |
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| 286 | size_t dcache_ways, |
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| 287 | size_t dcache_sets, |
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| 288 | size_t dcache_words, |
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| 289 | size_t wbuf_nwords, |
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[45] | 290 | size_t wbuf_nlines, |
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| 291 | size_t wbuf_timeout); |
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[2] | 292 | |
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| 293 | ~VciCcXCacheWrapperMulti(); |
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| 294 | |
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[45] | 295 | void printTrace(size_t mode); |
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| 296 | void printStatistics(); |
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[2] | 297 | |
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| 298 | private: |
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| 299 | |
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| 300 | void transition(); |
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| 301 | void genMoore(); |
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| 302 | |
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[45] | 303 | static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
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| 304 | static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
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[2] | 305 | }; |
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| 306 | |
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| 307 | }} |
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| 308 | |
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| 309 | #endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H */ |
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| 310 | |
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| 311 | // Local Variables: |
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| 312 | // tab-width: 4 |
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| 313 | // c-basic-offset: 4 |
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| 314 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 315 | // indent-tabs-mode: nil |
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| 316 | // End: |
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| 317 | |
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| 318 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 319 | |
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| 320 | |
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| 321 | |
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