Changeset 45 for trunk/modules/vci_cc_xcache_wrapper_multi/caba/source/include/vci_cc_xcache_wrapper_multi.h

Timestamp:

Jun 8, 2010, 5:04:20 PM (14 years ago)

Author:

alain

Message:

Introducing an improved memory consistency in the multi-write-buffer:

• write after write and read after write policy for cachable access
• fully blocking uncachable access (for both read and write requests)

File:

• trunk/modules/vci_cc_xcache_wrapper_multi/caba/source/include/vci_cc_xcache_wrapper_multi.h (modified) (7 diffs)

trunk/modules/vci_cc_xcache_wrapper_multi/caba/source/include/vci_cc_xcache_wrapper_multi.h

@@ -65 +65 @@
         DCACHE_MISS_UPDT,
         DCACHE_UNC_WAIT,
+        DCACHE_UNC_GO,
         DCACHE_INVAL,
         DCACHE_SYNC,
@@ -80 +81 @@
         ICACHE_MISS_UPDT,
         ICACHE_UNC_WAIT,
+        ICACHE_UNC_GO,
         ICACHE_ERROR,
         ICACHE_CC_CHECK,
@@ -117 +119 @@
 
     enum cleanup_fsm_state_e {
-        CLEANUP_CMD,
-        CLEANUP_DCACHE_RSP,
-        CLEANUP_ICACHE_RSP,
+        CLEANUP_IDLE,
+        CLEANUP_DCACHE,
+        CLEANUP_ICACHE,
     };
 
@@ -148 +150 @@
     const uint32_t                                                      m_srcid_c;   
    
-    const size_t                                m_wbuf_nlines; 
     const size_t                                                        m_dcache_ways;
     const size_t                                                        m_dcache_words;
@@ -233 +234 @@
     uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
 
-    uint32_t m_cpt_cc_update;               // number of coherence update packets 
-    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
+    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast packets 
+    uint32_t m_cpt_cc_update_data;          // number of coherence data update packets 
+    uint32_t m_cpt_cc_update_ins;           // number of coherence instruction update packets 
+    uint32_t m_cpt_cc_inval_data;           // number of coherence data inval packets
+    uint32_t m_cpt_cc_inval_ins;            // number of coherence instruction inval packets
+    uint32_t m_cpt_cc_cleanup_data;         // number of coherence data cleanup packets
+    uint32_t m_cpt_cc_cleanup_ins;          // number of coherence instruction cleanup packets
 
     uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
     uint32_t m_cpt_total_cycles;            // total number of cycles 
 
-    uint32_t m_cpt_read;                    // total number of read instructions
-    uint32_t m_cpt_write;                   // total number of write instructions
+    uint32_t m_cpt_read;                    // total number of read requests
+    uint32_t m_cpt_write;                   // total number of write requests
+    uint32_t m_cpt_write_cached;            // number of cached write requests
+    uint32_t m_cpt_data_unc;                // number of uncachable data requests
+    uint32_t m_cpt_ins_unc;                 // number of uncachable instruction requests
+    uint32_t m_cpt_ll;                      // number of ll requests
+    uint32_t m_cpt_sc;                      // number of sc requests
     uint32_t m_cpt_data_miss;               // number of read miss
     uint32_t m_cpt_ins_miss;                // number of instruction miss
-    uint32_t m_cpt_unc_read;                // number of read uncached
-    uint32_t m_cpt_write_cached;            // number of cached write
 
     uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
     uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
-    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_unc_frz;                // number of frozen cycles related to uncached read
     uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
 
     uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
     uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
-    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_data_unc_transaction;    // number of VCI instruction uncached transactions
+    uint32_t m_cpt_ins_unc_transaction;     // number of VCI data uncached transactions
     uint32_t m_cpt_write_transaction;       // number of VCI write transactions
 
@@ -278 +288 @@
                        size_t dcache_words,
                        size_t wbuf_nwords,
-                       size_t wbuf_nlines );
+                       size_t wbuf_nlines,
+                       size_t wbuf_timeout);
 
     ~VciCcXCacheWrapperMulti();
 
-    void print_cpi();
-    void print_stats();
+    void printTrace(size_t mode);
+    void printStatistics();
 
 private:
@@ -290 +301 @@
     void genMoore();
 
-    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
-    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+    static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
 };