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vci_cc_xcache_wrapper_multi.h @ 120

Last change on this file since 120 was 45, checked in by alain, 14 years ago

Introducing an improved memory consistency in the multi-write-buffer:

write after write and read after write policy for cachable access
fully blocking uncachable access (for both read and write requests)

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File size: 12.1 KB

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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, SoC
24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
25	*
26	* Maintainers: alain
27	*/
28
29	#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H
30	#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H
31
32	#include <inttypes.h>
33	#include <systemc>
34	#include "caba_base_module.h"
35	#include "multi_write_buffer.h"
36	#include "generic_cache.h"
37	#include "vci_initiator.h"
38	#include "vci_target.h"
39	#include "mapping_table.h"
40	#include "static_assert.h"
41
42
43	namespace soclib {
44	namespace caba {
45
46	using namespace sc_core;
47
48	////////////////////////////////////////////
49	template<typename vci_param, typename iss_t>
50	class VciCcXCacheWrapperMulti
51	///////////////////////////////////////////
52	: public soclib::caba::BaseModule
53	{
54	typedef uint32_t data_t;
55	typedef uint32_t be_t;
56	typedef typename vci_param::fast_addr_t addr_t;
57
58	enum dcache_fsm_state_e {
59	DCACHE_IDLE,
60	DCACHE_WRITE_UPDT,
61	DCACHE_WRITE_REQ,
62	DCACHE_MISS_SELECT,
63	DCACHE_MISS_CLEANUP,
64	DCACHE_MISS_WAIT,
65	DCACHE_MISS_UPDT,
66	DCACHE_UNC_WAIT,
67	DCACHE_UNC_GO,
68	DCACHE_INVAL,
69	DCACHE_SYNC,
70	DCACHE_ERROR,
71	DCACHE_CC_CHECK,
72	DCACHE_CC_INVAL,
73	DCACHE_CC_UPDT,
74	};
75
76	enum icache_fsm_state_e {
77	ICACHE_IDLE,
78	ICACHE_MISS_SELECT,
79	ICACHE_MISS_CLEANUP,
80	ICACHE_MISS_WAIT,
81	ICACHE_MISS_UPDT,
82	ICACHE_UNC_WAIT,
83	ICACHE_UNC_GO,
84	ICACHE_ERROR,
85	ICACHE_CC_CHECK,
86	ICACHE_CC_INVAL,
87	ICACHE_CC_UPDT,
88	};
89
90	enum cmd_fsm_state_e {
91	CMD_IDLE,
92	CMD_INS_MISS,
93	CMD_INS_UNC,
94	CMD_DATA_MISS,
95	CMD_DATA_UNC,
96	CMD_DATA_WRITE,
97	};
98
99	enum rsp_fsm_state_e {
100	RSP_IDLE,
101	RSP_INS_MISS,
102	RSP_INS_UNC,
103	RSP_DATA_MISS,
104	RSP_DATA_UNC,
105	RSP_DATA_WRITE,
106	};
107
108	enum tgt_fsm_state_e {
109	TGT_IDLE,
110	TGT_UPDT_WORD,
111	TGT_UPDT_DATA,
112	TGT_REQ_BROADCAST,
113	TGT_REQ_ICACHE,
114	TGT_REQ_DCACHE,
115	TGT_RSP_BROADCAST,
116	TGT_RSP_ICACHE,
117	TGT_RSP_DCACHE,
118	};
119
120	enum cleanup_fsm_state_e {
121	CLEANUP_IDLE,
122	CLEANUP_DCACHE,
123	CLEANUP_ICACHE,
124	};
125
126	enum transaction_type_e {
127	TYPE_DATA_UNC = 0,
128	TYPE_DATA_MISS = 1,
129	TYPE_INS_UNC = 2,
130	TYPE_INS_MISS = 3,
131	};
132
133	public:
134
135	// PORTS
136	sc_in<bool> p_clk;
137	sc_in<bool> p_resetn;
138	sc_in<bool> p_irq[iss_t::n_irq];
139	soclib::caba::VciInitiator<vci_param> p_vci_ini_d;
140	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
141	soclib::caba::VciTarget<vci_param> p_vci_tgt_c;
142
143	private:
144
145	// STRUCTURAL PARAMETERS
146	const soclib::common::AddressDecodingTable<addr_t, bool> m_cacheability_table;
147	const soclib::common::Segment m_segment;
148	iss_t m_iss;
149	const uint32_t m_srcid_d;
150	const uint32_t m_srcid_c;
151
152	const size_t m_dcache_ways;
153	const size_t m_dcache_words;
154	const size_t m_dcache_yzmask;
155	const size_t m_icache_ways;
156	const size_t m_icache_words;
157	const size_t m_icache_yzmask;
158
159	// REGISTERS
160	sc_signal<int> r_dcache_fsm; // controls the data cache interface
161	sc_signal<int> r_dcache_fsm_save;
162	sc_signal<addr_t> r_dcache_addr_save;
163	sc_signal<data_t> r_dcache_wdata_save;
164	sc_signal<data_t> r_dcache_rdata_save;
165	sc_signal<int> r_dcache_type_save;
166	sc_signal<be_t> r_dcache_be_save;
167	sc_signal<addr_t> r_dcache_cleanup_save; // victim line index for cleanup
168	sc_signal<size_t> r_dcache_way_save; // selected slot for the replacement
169	sc_signal<bool> r_dcache_cleanup_req; // send a cleanup request to CLEANUP FSM
170	sc_signal<addr_t> r_dcache_cleanup_line; // define the victim line index
171	sc_signal<bool> r_dcache_miss_req; // send a miss request to CMD FSM
172	sc_signal<bool> r_dcache_unc_req; // send a uncached request to CMD FSM
173	sc_signal<bool> r_dcache_inval_pending; // external inval or update request pending
174
175	sc_signal<int> r_icache_fsm; // controls the instruction cache interface
176	sc_signal<int> r_icache_fsm_save;
177	sc_signal<addr_t> r_icache_addr_save;
178	sc_signal<addr_t> r_icache_cleanup_save; // victim line index for cleanup
179	sc_signal<size_t> r_icache_way_save; // selected slot for the replacement
180	sc_signal<bool> r_icache_miss_req; // send a miss request to to CMD FSM
181	sc_signal<bool> r_icache_unc_req; // send an uncached request to CMD FSM
182	sc_signal<bool> r_icache_cleanup_req; // send a cleanup request to CLEANUP FSM
183	sc_signal<addr_t> r_icache_cleanup_line; // define the victim line index
184	sc_signal<bool> r_icache_inval_pending; // external inval or update request pending
185
186	sc_signal<int> r_cmd_fsm; // controls the command on the direct network
187	sc_signal<size_t> r_cmd_min;
188	sc_signal<size_t> r_cmd_max;
189	sc_signal<size_t> r_cmd_cpt;
190
191	sc_signal<int> r_rsp_fsm; // controls the response on the direct network
192	sc_signal<bool> r_rsp_ins_error; // signals an error to the ICACHE FSM
193	sc_signal<bool> r_rsp_data_error; // signals an error to the DCACHE FSM
194	sc_signal<size_t> r_rsp_cpt;
195	sc_signal<bool> r_rsp_ins_ok; // signals an available data to the ICACHE FSM
196	sc_signal<bool> r_rsp_data_ok; // signals an available data to the DCACHE FSM;
197
198	data_t *r_icache_miss_buf;
199	data_t *r_dcache_miss_buf;
200
201	data_t *r_tgt_buf;
202	bool *r_tgt_val;
203
204	sc_signal<int> r_tgt_fsm; // controls the target port of the coherence network
205	sc_signal<addr_t> r_tgt_addr;
206	sc_signal<size_t> r_tgt_word;
207	sc_signal<bool> r_tgt_update;
208	sc_signal<bool> r_tgt_data;
209	sc_signal<bool> r_tgt_brdcast;
210	sc_signal<size_t> r_tgt_srcid;
211	sc_signal<size_t> r_tgt_pktid;
212	sc_signal<size_t> r_tgt_trdid;
213	sc_signal<size_t> r_tgt_plen;
214	sc_signal<bool> r_tgt_icache_req; // coherence request from TGT FSM to ICACHE FSM
215	sc_signal<bool> r_tgt_dcache_req; // coherence request from TGT FSM to DCACHE FSM
216	sc_signal<bool> r_tgt_icache_rsp; // response from ICACHE FSM to TGT FSM : true == hit
217	sc_signal<bool> r_tgt_dcache_rsp; // response from DCACHE FSM to TGT FSM : true == hit
218
219	sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network
220
221	MultiWriteBuffer<addr_t> r_wbuf;
222	GenericCache<addr_t> r_icache;
223	GenericCache<addr_t> r_dcache;
224
225	// Activity counters
226	uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ
227	uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE
228	uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ
229	uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE
230
231	uint32_t m_cpt_icache_data_read; // ICACHE DATA READ
232	uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE
233	uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ
234	uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE
235
236	uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets
237	uint32_t m_cpt_cc_update_data; // number of coherence data update packets
238	uint32_t m_cpt_cc_update_ins; // number of coherence instruction update packets
239	uint32_t m_cpt_cc_inval_data; // number of coherence data inval packets
240	uint32_t m_cpt_cc_inval_ins; // number of coherence instruction inval packets
241	uint32_t m_cpt_cc_cleanup_data; // number of coherence data cleanup packets
242	uint32_t m_cpt_cc_cleanup_ins; // number of coherence instruction cleanup packets
243
244	uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen
245	uint32_t m_cpt_total_cycles; // total number of cycles
246
247	uint32_t m_cpt_read; // total number of read requests
248	uint32_t m_cpt_write; // total number of write requests
249	uint32_t m_cpt_write_cached; // number of cached write requests
250	uint32_t m_cpt_data_unc; // number of uncachable data requests
251	uint32_t m_cpt_ins_unc; // number of uncachable instruction requests
252	uint32_t m_cpt_ll; // number of ll requests
253	uint32_t m_cpt_sc; // number of sc requests
254	uint32_t m_cpt_data_miss; // number of read miss
255	uint32_t m_cpt_ins_miss; // number of instruction miss
256
257	uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
258	uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss
259	uint32_t m_cost_unc_frz; // number of frozen cycles related to uncached read
260	uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss
261
262	uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions
263	uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions
264	uint32_t m_cpt_data_unc_transaction; // number of VCI instruction uncached transactions
265	uint32_t m_cpt_ins_unc_transaction; // number of VCI data uncached transactions
266	uint32_t m_cpt_write_transaction; // number of VCI write transactions
267
268	uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions
269
270	protected:
271	SC_HAS_PROCESS(VciCcXCacheWrapperMulti);
272
273	public:
274
275	VciCcXCacheWrapperMulti(
276	sc_module_name insname,
277	int proc_id,
278	const soclib::common::MappingTable &mtp,
279	const soclib::common::MappingTable &mtc,
280	const soclib::common::IntTab &initiator_index_p,
281	const soclib::common::IntTab &initiator_index_c,
282	const soclib::common::IntTab &target_index_c,
283	size_t icache_ways,
284	size_t icache_sets,
285	size_t icache_words,
286	size_t dcache_ways,
287	size_t dcache_sets,
288	size_t dcache_words,
289	size_t wbuf_nwords,
290	size_t wbuf_nlines,
291	size_t wbuf_timeout);
292
293	~VciCcXCacheWrapperMulti();
294
295	void printTrace(size_t mode);
296	void printStatistics();
297
298	private:
299
300	void transition();
301	void genMoore();
302
303	static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
304	static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
305	};
306
307	}}
308
309	#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H */
310
311	// Local Variables:
312	// tab-width: 4
313	// c-basic-offset: 4
314	// c-file-offsets:((innamespace . 0)(inline-open . 0))
315	// indent-tabs-mode: nil
316	// End:
317
318	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
319
320
321

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