|
Last change
on this file since 975 was
528,
checked in by lambert, 11 years ago
|
|
Introduicing VciEthernetTsar?
This component is modified version of VciEthernet? from soclib
Main differences are :
- DMA access avoid overlapinging cache line boundaries
- Pktid is now 0x4 in write cmd
- IRQ can be reset with the status register
|
|
File size:
425 bytes
|
| Line | |
|---|
| 1 | This files describes the differences between vci_ethernet_tsar and |
|---|
| 2 | vci_ethernet |
|---|
| 3 | |
|---|
| 4 | * Added f->wr_req->setPacket(0x4); for every Write command from vci_ethernet in |
|---|
| 5 | order to respect overloading of vci CMD in pktid of Tsar architecture |
|---|
| 6 | |
|---|
| 7 | * Added overlapping detection in read and write vci CMD. First, vci CMD is now |
|---|
| 8 | made at maximum with the boundary of a cache line (64 alignement) |
|---|
| 9 | |
|---|
| 10 | * Added set and reset for IRQ lines enable |
|---|
Note: See
TracBrowser
for help on using the repository browser.
