[240] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_io_bridge.h |
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| 3 | * Copyright (c) UPMC, Lip6, SoC |
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| 4 | * Date : 16/04/2012 |
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| 5 | * |
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| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 7 | * |
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| 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 9 | * |
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| 10 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU Lesser General Public License as published |
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| 12 | * by the Free Software Foundation; version 2.1 of the License. |
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| 13 | * |
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| 14 | * SoCLib is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * Lesser General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU Lesser General Public |
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| 20 | * License along with SoCLib; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 22 | * 02110-1301 USA |
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| 23 | * |
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| 24 | * SOCLIB_LGPL_HEADER_END |
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| 25 | */ |
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| 26 | |
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| 27 | //////Utilisation Considerations//////////////////////////////////////////////// |
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| 28 | // |
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| 29 | // - IOMMU PTPR pointer must fit in 32 bits (with a classical 2 level 4K page |
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| 30 | // table in a 32 bit virtual space, it means a maximum of 45 bits in physical |
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| 31 | // address) |
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| 32 | // |
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| 33 | // - Physical address must fit in two 32 bit words |
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| 34 | // |
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| 35 | // - Maximal number of flits in a write transaction cannot be bigger than (n° of |
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| 36 | // words in a chache line)/2 |
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| 37 | // |
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| 38 | // - Page Tables must have the format used in TSAR (compatible with component |
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| 39 | // generic_tlb) |
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| 40 | // |
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| 41 | // - IO's segment size must be the same in both networks |
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| 42 | // |
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| 43 | // - Write operations on IOMMU configuration registers (PTPR, ACTIVE) can only |
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| 44 | // be done when DMA_TLB FSM is IDLE. It should, preferably, be done before |
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| 45 | // starting any transfers. Pseudo register INVAL may be modified any time. |
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| 46 | // |
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| 47 | // - Similarly, write operations on the interruptions registers can only be done |
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| 48 | // when the dedicated FSM is IDLE. |
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| 49 | //////////////////////////////////////////////////////////////////////////////// |
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| 50 | |
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| 51 | |
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| 52 | ///////TODO List/////////////////////////////////////////////////////////////// |
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| 53 | // |
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| 54 | // Tableau de correspondance d'adresses physique - IO (pour CONFIG_CMD) |
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| 55 | // |
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| 56 | // Conversion 32 (entree) Ã 64 (sortie) bits (champ data). Dans les deux senses (CMD et RSP) |
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| 57 | // |
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| 58 | // Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit |
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| 59 | // (seulement 'data' et 'be') |
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| 60 | /////////////////////////////////////////////////////////////////////////////// |
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| 61 | |
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| 62 | #ifndef SOCLIB_CABA_VCI_IO_BRIDGE_H |
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| 63 | #define SOCLIB_CABA_VCI_IO_BRIDGE_H |
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| 64 | |
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| 65 | #include <inttypes.h> |
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| 66 | #include <systemc> |
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| 67 | #include "caba_base_module.h" |
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| 68 | #include "generic_fifo.h" |
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| 69 | #include "generic_tlb.h" |
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| 70 | #include "mapping_table.h" |
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| 71 | #include "address_decoding_table.h" |
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| 72 | #include "static_assert.h" |
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| 73 | #include "transaction_tab_io.h" |
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| 74 | #include "vci_initiator.h" |
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| 75 | #include "vci_target.h" |
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| 76 | |
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| 77 | namespace soclib { |
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| 78 | namespace caba { |
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| 79 | |
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| 80 | using namespace soclib::common; |
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| 81 | |
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| 82 | //////////////////////////////////////////// |
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| 83 | template<typename vci_param_d,typename vci_param_x, typename vci_param_io > |
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| 84 | class VciIoBridge |
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| 85 | //////////////////////////////////////////// |
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| 86 | : public soclib::caba::BaseModule |
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| 87 | { |
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| 88 | typedef uint32_t tag_t; |
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| 89 | typedef uint32_t type_t; |
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| 90 | |
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| 91 | // Address field may change between direct, extenal and IO network |
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| 92 | typedef typename vci_param_d::addr_t paddr_t; |
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| 93 | typedef typename vci_param_x::addr_t paddr_t_x; // Just the cache line, for example |
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| 94 | typedef typename vci_param_io::addr_t vaddr_t; |
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| 95 | |
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| 96 | // Data field may change for external network |
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| 97 | typedef typename vci_param_x::data_t vci_data_t_x; |
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| 98 | // Srcid field may change for external network |
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| 99 | typedef typename vci_param_x::srcid_t vci_srcid_t_x; |
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| 100 | |
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| 101 | // Other fields must coincide |
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| 102 | typedef typename vci_param_d::srcid_t vci_srcid_t; |
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| 103 | typedef typename vci_param_d::data_t vci_data_t; |
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| 104 | typedef typename vci_param_d::be_t vci_be_t; |
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| 105 | typedef typename vci_param_d::trdid_t vci_trdid_t; |
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| 106 | typedef typename vci_param_d::pktid_t vci_pktid_t; |
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| 107 | typedef typename vci_param_d::plen_t vci_plen_t; |
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| 108 | typedef typename vci_param_d::cmd_t vci_cmd_t; |
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| 109 | typedef typename vci_param_d::contig_t vci_contig_t; |
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| 110 | typedef typename vci_param_d::eop_t vci_eop_t; |
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| 111 | typedef typename vci_param_d::const_t vci_cons_t; |
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| 112 | typedef typename vci_param_d::wrap_t vci_wrap_t; |
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| 113 | typedef typename vci_param_d::clen_t vci_clen_t; |
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| 114 | typedef typename vci_param_d::cfixed_t vci_cfixed_t; |
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| 115 | |
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| 116 | typedef typename vci_param_d::rerror_t vci_rerror_t; |
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| 117 | |
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| 118 | enum { |
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| 119 | CACHE_LINE_MASK = 0xFFFFFFFFC0, |
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| 120 | PPN1_MASK = 0x0007FFFF, |
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| 121 | PPN2_MASK = 0x0FFFFFFF, |
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| 122 | K_PAGE_OFFSET_MASK = 0x00000FFF, |
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| 123 | M_PAGE_OFFSET_MASK = 0x001FFFFF, |
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| 124 | PTE2_LINE_OFFSET = 0x00007000, // bits 12,13,14. |
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| 125 | PTE1_LINE_OFFSET = 0x01E00000, // bits 21,22,23,24 |
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| 126 | }; |
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| 127 | |
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| 128 | //DMA (from Peripherals to XRAM) |
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| 129 | enum dma_cmd_fsm_state { |
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| 130 | DMA_CMD_IDLE, |
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| 131 | DMA_CMD_TRT_LOCK, |
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| 132 | DMA_CMD_TRT_WAIT, |
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| 133 | DMA_CMD_TRT_SET, |
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| 134 | DMA_CMD_FIFO_PUT, |
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| 135 | DMA_CMD_FIFO_MISS_PUT, |
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| 136 | DMA_CMD_TLB_MISS_WAIT, |
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| 137 | DMA_CMD_TLB_MISS_STORE, |
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| 138 | DMA_CMD_ERROR, |
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| 139 | }; |
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| 140 | |
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| 141 | enum dma_rsp_fsm_state { |
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| 142 | DMA_RSP_IDLE, |
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| 143 | DMA_RSP_TRT_LOCK, |
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| 144 | DMA_RSP_FIFO_PUT, |
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| 145 | DMA_RSP_FIFO_ERROR_PUT, |
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| 146 | }; |
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| 147 | |
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| 148 | // Allocates the transaction_tab_dma |
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| 149 | enum alloc_trt_dma_fsm_state { |
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| 150 | ALLOC_TRT_DMA_CMD, |
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| 151 | ALLOC_TRT_DMA_RSP |
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| 152 | }; |
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| 153 | |
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| 154 | |
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| 155 | enum dma_tlb_fsm_state { |
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| 156 | DMA_TLB_IDLE, |
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| 157 | DMA_TLB_MISS, |
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| 158 | DMA_TLB_PTE1_GET, |
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| 159 | DMA_TLB_PTE1_SELECT, |
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| 160 | DMA_TLB_PTE1_UPDT, |
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| 161 | DMA_TLB_PTE2_GET, |
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| 162 | DMA_TLB_PTE2_SELECT, |
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| 163 | DMA_TLB_PTE2_UPDT, |
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| 164 | DMA_TLB_WAIT_TRANSACTION, |
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| 165 | DMA_TLB_RETURN, |
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| 166 | // Treatment of CONFIG FSM request |
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| 167 | DMA_TLB_INVAL_CHECK, |
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| 168 | DMA_TLB_INVAL_SCAN |
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| 169 | }; |
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| 170 | |
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| 171 | //CONFIG (from Direct Network to Peripherals) |
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| 172 | enum config_cmd_fsm_state { |
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| 173 | CONFIG_CMD_IDLE, |
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| 174 | CONFIG_CMD_TRT_LOCK, |
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| 175 | CONFIG_CMD_TRT_WAIT, |
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| 176 | CONFIG_CMD_TRT_SET, |
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| 177 | CONFIG_CMD_FIFO_PUT, |
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| 178 | |
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| 179 | // IOB private configuration segment |
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| 180 | CONFIG_CMD_PTPR_WRITE, |
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| 181 | CONFIG_CMD_PTPR_READ, |
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| 182 | CONFIG_CMD_ACTIVE_WRITE, |
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| 183 | CONFIG_CMD_ACTIVE_READ, |
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| 184 | CONFIG_CMD_BVAR_READ, |
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| 185 | CONFIG_CMD_ETR_READ, |
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| 186 | CONFIG_CMD_BAD_ID_READ, |
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| 187 | CONFIG_CMD_INVAL_REQ, |
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| 188 | CONFIG_CMD_INVAL, |
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| 189 | CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1, |
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| 190 | CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2, |
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| 191 | CONFIG_CMD_IT_ADDR_IOMMU_READ_1, |
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| 192 | CONFIG_CMD_IT_ADDR_IOMMU_READ_2, |
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| 193 | CONFIG_CMD_IT_ADDR_WRITE_1, |
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| 194 | CONFIG_CMD_IT_ADDR_WRITE_2, |
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| 195 | CONFIG_CMD_IT_ADDR_READ_1, |
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| 196 | CONFIG_CMD_IT_ADDR_READ_2, |
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| 197 | CONFIG_CMD_ERROR_WAIT, |
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| 198 | CONFIG_CMD_ERROR_RSP |
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| 199 | }; |
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| 200 | |
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| 201 | enum config_rsp_fsm_state { |
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| 202 | CONFIG_RSP_IDLE, |
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| 203 | CONFIG_RSP_TRT_LOCK, |
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| 204 | CONFIG_RSP_FIFO_PUT |
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| 205 | }; |
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| 206 | |
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| 207 | // Allocates the transaction_tab_dma |
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| 208 | enum alloc_trt_config_fsm_state { |
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| 209 | ALLOC_TRT_CONFIG_CMD, |
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| 210 | ALLOC_TRT_CONFIG_RSP |
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| 211 | }; |
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| 212 | |
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| 213 | //MISS TRANSACTIONS (to Direct Network) |
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| 214 | enum miss_init_fsm_state { |
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| 215 | MISS_INIT_IDLE_MISS, |
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| 216 | MISS_INIT_IDLE_IRQ, |
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| 217 | MISS_INIT_IRQ_CMD, |
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| 218 | MISS_INIT_IRQ_RSP, |
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| 219 | MISS_INIT_TLB_MISS_CMD, |
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| 220 | MISS_INIT_TLB_MISS_RSP |
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| 221 | }; |
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| 222 | |
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| 223 | ///////////////////////////////////////////////////////////////// |
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| 224 | |
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| 225 | // Configuration Error Type |
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| 226 | enum config_error_type { |
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| 227 | READ_OK = 0, |
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| 228 | READ_ERROR = 1, |
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| 229 | WRITE_OK = 2, |
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| 230 | WRITE_ERROR = 3 |
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| 231 | }; |
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| 232 | |
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| 233 | // Miss types for iotlb |
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| 234 | enum tlb_miss_type_e |
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| 235 | { |
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| 236 | PTE1_MISS, |
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| 237 | PTE2_MISS |
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| 238 | }; |
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| 239 | |
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| 240 | // IOB Configuration registers |
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| 241 | // Required segment size = (8 + 2*nb_periph) words |
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| 242 | enum { |
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| 243 | IOB_IOMMU_PTPR = 0, // R/W : Page Table Pointer Register |
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| 244 | IOB_IOMMU_ACTIVE = 1, // R/W : IOMMU activated if not 0 |
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| 245 | IOB_IOMMU_BVAR = 2, // R : Bad Virtual Address |
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| 246 | IOB_IOMMU_ETR = 3, // R : Error type |
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| 247 | IOB_IOMMU_BAD_ID = 4, // R : Faulty peripheral Index |
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| 248 | IOB_INVAL_PTE = 5, // W : Invalidate PTE. Virtual Address |
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| 249 | IOB_IT_ADDR_IOMMU_LO = 6, // R/W |
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| 250 | IOB_IT_ADDR_IOMMU_HI = 7, // R/W |
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| 251 | IOB_IT_ADDR_BEGIN = 8 // R/W : One register by IO |
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| 252 | // Addressed by two 32-bit words each |
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| 253 | }; |
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| 254 | |
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| 255 | |
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| 256 | // Error Type |
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| 257 | enum mmu_error_type_e |
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| 258 | { |
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| 259 | MMU_NONE = 0x0000, // None |
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| 260 | MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access of write access to a non writable page (bit W in flags) |
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| 261 | MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write access of Bus Error accessing Table 1 |
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| 262 | MMU_READ_PT1_UNMAPPED = 0x1001, // Read access of Page fault on Page Table 1 |
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| 263 | MMU_READ_PT2_UNMAPPED = 0x1002, // Read access of Page fault on Page Table 2 |
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| 264 | MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read access of Bus Error in Table1 access |
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| 265 | MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read access of Bus Error in Table2 access |
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| 266 | MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read access of Bus Error in cache access |
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| 267 | }; |
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| 268 | |
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| 269 | |
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| 270 | public: |
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| 271 | sc_in<bool> p_clk; |
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| 272 | sc_in<bool> p_resetn; |
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| 273 | sc_in<bool> *p_irq_in; |
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| 274 | |
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| 275 | soclib::caba::VciInitiator<vci_param_x> p_vci_ini_dma; // XRAM Noc |
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| 276 | soclib::caba::VciTarget<vci_param_io> p_vci_tgt_dma; |
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| 277 | |
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| 278 | soclib::caba::VciInitiator<vci_param_io> p_vci_ini_config; |
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| 279 | soclib::caba::VciTarget<vci_param_d> p_vci_tgt_config; |
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| 280 | |
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| 281 | soclib::caba::VciInitiator<vci_param_d> p_vci_ini_miss; |
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| 282 | |
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| 283 | private: |
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| 284 | const size_t m_words; |
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| 285 | const size_t m_nb_periph; |
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| 286 | |
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| 287 | // STRUCTURAL PARAMETERS |
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| 288 | // soclib::common::AddressDecodingTable<unsigned long, bool> m_locality_table_config; |
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| 289 | // soclib::common::AddressDecodingTable<unsigned long, int> m_routing_table_config; |
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| 290 | //const soclib::common::MappingTable& m_mtio; |
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| 291 | |
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| 292 | uint32_t m_transaction_tab_dma_lines; |
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| 293 | TransactionTabIO m_transaction_tab_dma; // dma transaction table |
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| 294 | |
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| 295 | uint32_t m_transaction_tab_config_lines; |
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| 296 | TransactionTabIO m_transaction_tab_config; // config transaction table |
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| 297 | |
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| 298 | // Direct Network |
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| 299 | const soclib::common::Segment m_segment_config; |
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| 300 | const vci_srcid_t m_srcid_miss; |
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| 301 | // XRAM Network |
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| 302 | const vci_srcid_t_x m_srcid_dma; |
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| 303 | // IO Network |
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| 304 | const soclib::common::Segment m_segment_io; |
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| 305 | const vci_srcid_t m_srcid_config; |
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| 306 | |
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| 307 | const size_t m_iotlb_ways; |
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| 308 | const size_t m_iotlb_sets; |
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| 309 | const size_t m_paddr_nbits; |
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| 310 | |
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| 311 | |
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| 312 | ///////////////////////////////////////////// |
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| 313 | // debug variables (for each FSM) |
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| 314 | ///////////////////////////////////////////// |
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| 315 | uint32_t m_debug_start_cycle; |
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| 316 | bool m_debug_ok; |
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| 317 | |
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| 318 | bool m_debug_dma_cmd_fsm; |
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| 319 | bool m_debug_dma_rsp_fsm; |
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| 320 | bool m_debug_dma_tlb_fsm; |
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| 321 | bool m_debug_config_cmd_fsm; |
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| 322 | bool m_debug_config_rsp_fsm; |
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| 323 | bool m_debug_miss_init_fsm; |
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| 324 | |
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| 325 | /////////////////////////////// |
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| 326 | // MEMORY MAPPED REGISTERS |
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| 327 | /////////////////////////////// |
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| 328 | sc_signal<uint32_t> r_iommu_ptpr; // page table pointer register |
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| 329 | sc_signal<bool> r_iommu_active; // iotlb mode |
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| 330 | sc_signal<uint32_t> r_iommu_bvar; // iommu bad address |
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| 331 | sc_signal<uint32_t> r_iommu_etr; // iommu error type |
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| 332 | sc_signal<uint32_t> r_iommu_bad_id; // ID of the peripheral that tried bad operation |
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| 333 | |
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| 334 | sc_signal<paddr_t> r_it_addr_iommu; // iommu error type |
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| 335 | paddr_t *r_it_addr; // iommu error type |
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| 336 | |
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| 337 | /////////////////////////////////// |
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| 338 | // DMA_CMD FSM REGISTERS |
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| 339 | /////////////////////////////////// |
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| 340 | sc_signal<int> r_dma_cmd_fsm; // state register |
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| 341 | sc_signal<int> r_dma_cmd_fsm_save; //saves current state when miss interruption happens |
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| 342 | sc_signal<bool> r_miss_interrupt; |
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| 343 | |
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| 344 | sc_signal<int> r_dma_cmd_count; |
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| 345 | sc_signal<vci_trdid_t> r_dma_cmd_trt_index; |
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| 346 | sc_signal<paddr_t> r_dma_paddr; |
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| 347 | |
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| 348 | GenericFifo<paddr_t> m_dma_cmd_addr_fifo; |
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| 349 | //GenericFifo<size_t> m_dma_cmd_length_fifo; |
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| 350 | GenericFifo<vci_srcid_t> m_dma_cmd_srcid_fifo; |
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| 351 | GenericFifo<vci_trdid_t> m_dma_cmd_trdid_fifo; |
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| 352 | GenericFifo<vci_pktid_t> m_dma_cmd_pktid_fifo; |
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| 353 | GenericFifo<vci_be_t> m_dma_cmd_be_fifo; |
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| 354 | GenericFifo<vci_cmd_t> m_dma_cmd_cmd_fifo; |
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| 355 | GenericFifo<vci_contig_t> m_dma_cmd_contig_fifo; |
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| 356 | GenericFifo<vci_data_t> m_dma_cmd_data_fifo; |
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| 357 | GenericFifo<vci_eop_t> m_dma_cmd_eop_fifo; |
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| 358 | GenericFifo<vci_cons_t> m_dma_cmd_cons_fifo; |
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| 359 | GenericFifo<vci_plen_t> m_dma_cmd_plen_fifo; |
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| 360 | GenericFifo<vci_wrap_t> m_dma_cmd_wrap_fifo; |
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| 361 | GenericFifo<vci_cfixed_t> m_dma_cmd_cfixed_fifo; |
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| 362 | GenericFifo<vci_clen_t> m_dma_cmd_clen_fifo; |
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| 363 | |
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| 364 | // Command storage registers (in case of miss tlb) |
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| 365 | sc_signal<paddr_t> r_miss_paddr; |
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| 366 | sc_signal<vci_cmd_t> r_miss_cmd ; |
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| 367 | sc_signal<vci_contig_t> r_miss_contig; |
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| 368 | sc_signal<vci_cons_t> r_miss_cons ; |
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| 369 | sc_signal<vci_plen_t> r_miss_plen ; |
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| 370 | sc_signal<vci_wrap_t> r_miss_wrap ; |
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| 371 | sc_signal<vci_cfixed_t> r_miss_cfixed; |
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| 372 | sc_signal<vci_clen_t> r_miss_clen ; |
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| 373 | sc_signal<vci_srcid_t> r_miss_srcid ; |
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| 374 | sc_signal<vci_trdid_t> r_miss_trdid ; |
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| 375 | sc_signal<vci_pktid_t> r_miss_pktid ; |
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| 376 | vci_data_t *r_miss_data ; |
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| 377 | vci_be_t *r_miss_be; |
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| 378 | |
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| 379 | // Error registers |
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| 380 | sc_signal<int> r_dma_error_type; |
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| 381 | sc_signal<vci_trdid_t> r_dma_error_trdid; |
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| 382 | sc_signal<vci_pktid_t> r_dma_error_pktid; |
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| 383 | |
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| 384 | /////////////////////////////////// |
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| 385 | // DMA_TLB FSM REGISTERS |
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| 386 | /////////////////////////////////// |
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| 387 | sc_signal<int> r_dma_tlb_fsm; // state register |
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| 388 | sc_signal<bool> r_waiting_transaction; // Flag for returning from |
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| 389 | // invalidation interruptions |
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| 390 | sc_signal<int> r_tlb_miss_type; |
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| 391 | |
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| 392 | sc_signal<vaddr_t> r_iotlb_vaddr; // virtual address for a tlb miss |
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| 393 | sc_signal<paddr_t> r_iotlb_paddr; // physical address of pte |
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| 394 | sc_signal<uint32_t> r_iotlb_pte_flags; // pte1 or first word of pte2 |
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| 395 | sc_signal<uint32_t> r_iotlb_pte_ppn; // second word of pte2 |
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| 396 | sc_signal<size_t> r_iotlb_way; // selected way in tlb |
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| 397 | sc_signal<size_t> r_iotlb_set; // selected set in tlb |
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| 398 | |
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| 399 | ////////////////////////////////////////////////////////////////// |
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| 400 | // IOTLB |
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| 401 | ////////////////////////////////////////////////////////////////// |
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| 402 | GenericTlb<paddr_t> r_iotlb; |
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| 403 | |
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| 404 | /////////////////////////////////// |
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| 405 | // DMA_RSP FSM REGISTERS |
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| 406 | /////////////////////////////////// |
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| 407 | sc_signal<int> r_dma_rsp_fsm; |
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| 408 | |
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| 409 | sc_signal<vci_trdid_t> r_dma_rtrdid; |
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| 410 | sc_signal<vci_srcid_t> r_dma_rsrcid; |
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| 411 | |
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| 412 | GenericFifo<vci_data_t> m_dma_rsp_data_fifo; |
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| 413 | GenericFifo<vci_srcid_t> m_dma_rsp_rsrcid_fifo; |
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| 414 | GenericFifo<vci_trdid_t> m_dma_rsp_rtrdid_fifo; |
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| 415 | GenericFifo<vci_pktid_t> m_dma_rsp_rpktid_fifo; |
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| 416 | GenericFifo<vci_eop_t> m_dma_rsp_reop_fifo; |
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| 417 | GenericFifo<vci_rerror_t> m_dma_rsp_rerror_fifo; |
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| 418 | |
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| 419 | //Communication between DMA_CMD and DMA_RSP |
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| 420 | sc_signal<bool> r_dma_cmd_rsp_erase_req; |
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| 421 | sc_signal<bool> r_dma_cmd_error_req; |
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| 422 | //Communication between DMA_CMD and TLB |
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| 423 | sc_signal<bool> r_dma_tlb_req; |
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| 424 | sc_signal<bool> r_tlb_dma_untreated; |
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| 425 | sc_signal<bool> r_dma_tlb_error_req; |
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| 426 | sc_signal<int> r_tlb_error_type; |
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| 427 | //Communication betweeen TLB and CONFIG_CMD |
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| 428 | sc_signal<bool> r_config_tlb_req; |
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| 429 | sc_signal<vaddr_t> r_config_tlb_inval_vaddr; |
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| 430 | |
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| 431 | /////////////////////////////////// |
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| 432 | // ALLOC_TRT_DMA FSM REGISTERS |
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| 433 | /////////////////////////////////// |
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| 434 | sc_signal<int> r_alloc_trt_dma_fsm; // state register |
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| 435 | |
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| 436 | |
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| 437 | /////////////////////////////////// |
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| 438 | // CONFIG_CMD FSM REGISTERS |
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| 439 | /////////////////////////////////// |
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| 440 | sc_signal<int> r_config_cmd_fsm; // state register |
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| 441 | |
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| 442 | sc_signal<vci_trdid_t> r_config_cmd_trt_index; |
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| 443 | |
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| 444 | GenericFifo<paddr_t> m_config_cmd_addr_fifo; |
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| 445 | //GenericFifo<size_t> m_config_cmd_length_fifo; |
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| 446 | GenericFifo<vci_srcid_t> m_config_cmd_srcid_fifo; |
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| 447 | GenericFifo<vci_trdid_t> m_config_cmd_trdid_fifo; |
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| 448 | GenericFifo<vci_pktid_t> m_config_cmd_pktid_fifo; |
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| 449 | GenericFifo<vci_be_t> m_config_cmd_be_fifo; |
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| 450 | GenericFifo<vci_cmd_t> m_config_cmd_cmd_fifo; |
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| 451 | GenericFifo<vci_contig_t> m_config_cmd_contig_fifo; |
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| 452 | GenericFifo<vci_data_t> m_config_cmd_data_fifo; |
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| 453 | GenericFifo<vci_eop_t> m_config_cmd_eop_fifo; |
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| 454 | GenericFifo<vci_cons_t> m_config_cmd_cons_fifo; |
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| 455 | GenericFifo<vci_plen_t> m_config_cmd_plen_fifo; |
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| 456 | GenericFifo<vci_wrap_t> m_config_cmd_wrap_fifo; |
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| 457 | GenericFifo<vci_cfixed_t> m_config_cmd_cfixed_fifo; |
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| 458 | GenericFifo<vci_clen_t> m_config_cmd_clen_fifo; |
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| 459 | |
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| 460 | |
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| 461 | // Private configuration registers |
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| 462 | sc_signal<int> r_config_error_type; // rerror field |
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| 463 | sc_signal<vci_data_t> r_config_first_word; |
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| 464 | sc_signal<int> r_it_index; |
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| 465 | |
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| 466 | GenericFifo<vci_data_t> m_config_local_data_fifo; |
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| 467 | GenericFifo<vci_srcid_t> m_config_local_rsrcid_fifo; |
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| 468 | GenericFifo<vci_trdid_t> m_config_local_rtrdid_fifo; |
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| 469 | GenericFifo<vci_pktid_t> m_config_local_rpktid_fifo; |
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| 470 | GenericFifo<vci_eop_t> m_config_local_reop_fifo; |
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| 471 | GenericFifo<vci_rerror_t> m_config_local_rerror_fifo; |
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| 472 | sc_signal<vaddr_t> r_config_vaddr; |
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| 473 | |
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| 474 | |
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| 475 | /////////////////////////////////// |
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| 476 | // CONFIG_RSP FSM REGISTERS |
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| 477 | /////////////////////////////////// |
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| 478 | sc_signal<int> r_config_rsp_fsm; |
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| 479 | |
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| 480 | sc_signal<vci_trdid_t> r_config_rtrdid; |
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| 481 | sc_signal<vci_srcid_t> r_config_rsrcid; |
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| 482 | |
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| 483 | GenericFifo<vci_data_t> m_config_rsp_data_fifo; |
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| 484 | GenericFifo<vci_srcid_t> m_config_rsp_rsrcid_fifo; |
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| 485 | GenericFifo<vci_trdid_t> m_config_rsp_rtrdid_fifo; |
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| 486 | GenericFifo<vci_pktid_t> m_config_rsp_rpktid_fifo; |
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| 487 | GenericFifo<vci_eop_t> m_config_rsp_reop_fifo; |
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| 488 | GenericFifo<vci_rerror_t> m_config_rsp_rerror_fifo; |
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| 489 | |
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| 490 | // Defines priority between the two response FIFOs (local and remote) |
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| 491 | sc_signal<bool> r_config_rsp_fifo_local_priority; |
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| 492 | |
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| 493 | //Communication between CONFIG_CMD and CONFIG_RSP |
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| 494 | sc_signal<bool> r_config_cmd_rsp_erase_req; // used to signal an erasing on TRT table |
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| 495 | |
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| 496 | /////////////////////////////////// |
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| 497 | // ALLOC_TRT_CONFIG FSM REGISTERS |
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| 498 | /////////////////////////////////// |
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| 499 | sc_signal<int> r_alloc_trt_config_fsm; // state register |
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| 500 | |
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| 501 | /////////////////////////////////// |
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| 502 | // MISS_INIT FSM REGISTERS |
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| 503 | /////////////////////////////////// |
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| 504 | sc_signal<int> r_miss_init_fsm; |
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| 505 | |
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| 506 | sc_signal<vci_data_t> r_miss_rdata; |
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| 507 | sc_signal<vci_pktid_t> r_miss_rpktid; |
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| 508 | sc_signal<vci_trdid_t> r_miss_rtrdid; |
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| 509 | sc_signal<vci_rerror_t> r_miss_rerror; |
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| 510 | sc_signal<vci_eop_t> r_miss_reop; |
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| 511 | //sc_signal<vci_data_t> r_miss_rsrcid; |
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| 512 | |
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| 513 | sc_signal<size_t> r_miss_rsp_cpt; |
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| 514 | |
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| 515 | //IRQ |
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| 516 | sc_signal<uint32_t> r_irq_pending; |
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| 517 | sc_signal<uint32_t> r_irq_mask; |
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| 518 | sc_signal<uint32_t> r_irq_chosen; |
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| 519 | |
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| 520 | |
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| 521 | //Communication between TLB and MISS_INIT |
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| 522 | sc_signal<bool> r_tlb_miss_init_req; |
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| 523 | sc_signal<bool> r_miss_init_error; |
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| 524 | |
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| 525 | //////////////////////////////////// |
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| 526 | // MISS PREFETCH BUFFER |
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| 527 | /////////////////////////////////// |
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| 528 | //DMA_TLB FSM is its owner. |
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| 529 | //CONFIG FSM must set a request in order to access the resource (invalidation) |
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| 530 | |
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| 531 | // Proposition : Buffer with some lines (4, for example). It could be |
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| 532 | // indexed from the bit 20. |
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| 533 | |
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| 534 | vci_data_t *r_miss_buf_data; // cache line data buffer |
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| 535 | bool r_miss_buf_valid; // For individual invalidation, |
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| 536 | // we could rather use the Valid bit at each PTE |
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| 537 | sc_signal<paddr_t> r_miss_buf_tag; // chache line number |
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| 538 | sc_signal<paddr_t> r_miss_buf_vaddr_begin; // Virtual address of the first PTE on the line |
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| 539 | |
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| 540 | bool r_miss_buf_first_level; // useful only if using both types of pages |
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| 541 | |
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| 542 | //////////////////////////////// |
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| 543 | // Activity counters |
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| 544 | //////////////////////////////// |
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| 545 | |
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| 546 | uint32_t m_cpt_total_cycles; // total number of cycles |
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| 547 | |
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| 548 | // TLB activity counters |
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| 549 | uint32_t m_cpt_iotlb_read; // number of iotlb read |
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| 550 | uint32_t m_cpt_iotlb_miss; // number of iotlb miss |
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| 551 | uint32_t m_cost_iotlb_miss; // number of blocking cycles (not the treatment cycles itself) |
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| 552 | uint32_t m_cpt_iotlbmiss_transaction; // number of iotlb miss transactions to Mem Cache |
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| 553 | uint32_t m_cost_iotlbmiss_transaction; // cumulated duration for iotlb miss transactions |
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| 554 | |
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| 555 | //Transaction Tabs (TRTs) activity counters |
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| 556 | uint32_t m_cpt_trt_dma_full; // DMA TRT full when a new command arrives |
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| 557 | uint32_t m_cpt_trt_dma_full_cost; // total number of cycles blocked |
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| 558 | uint32_t m_cpt_trt_config_full; // Config TRT full when a new command arrives |
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| 559 | uint32_t m_cpt_trt_config_full_cost; // total number of cycles blocked |
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| 560 | |
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| 561 | // FSM activity counters |
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| 562 | // unused on print_stats |
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| 563 | uint32_t m_cpt_fsm_dma_cmd [32]; |
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| 564 | uint32_t m_cpt_fsm_dma_rsp [32]; |
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| 565 | uint32_t m_cpt_fsm_dma_tlb [32]; |
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| 566 | uint32_t m_cpt_fsm_alloc_trt_dma [32]; |
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| 567 | uint32_t m_cpt_fsm_config_cmd [32]; |
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| 568 | uint32_t m_cpt_fsm_config_rsp [32]; |
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| 569 | uint32_t m_cpt_fsm_alloc_trt_config [32]; |
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| 570 | uint32_t m_cpt_fsm_miss_init [32]; |
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| 571 | |
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| 572 | protected: |
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| 573 | SC_HAS_PROCESS(VciIoBridge); |
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| 574 | |
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| 575 | public: |
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| 576 | VciIoBridge( |
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| 577 | sc_module_name insname, |
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| 578 | size_t nb_periph, // maximun is 32 |
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| 579 | const soclib::common::MappingTable &mtx, //external network |
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| 580 | const soclib::common::MappingTable &mtd, //direct network |
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| 581 | const soclib::common::MappingTable &mtio, //io network |
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| 582 | const soclib::common::Segment &seg_config_iob, |
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| 583 | const soclib::common::IntTab &tgt_index_iocluster, |
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| 584 | // const soclib::common::IntTab &tgt_index_config, // Direct Noc |
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| 585 | const soclib::common::IntTab &init_index_direct, // Direct Noc |
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| 586 | const soclib::common::IntTab &tgt_index_iospace, // IO Noc |
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| 587 | const soclib::common::IntTab &init_index_iospace, // IO Noc |
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| 588 | const soclib::common::IntTab &init_index_dma, // XRAM Noc |
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| 589 | size_t dcache_words, |
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| 590 | size_t iotlb_ways, |
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| 591 | size_t iotlb_sets, |
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| 592 | uint32_t debug_start_cycle, |
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| 593 | bool debug_ok); |
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| 594 | |
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| 595 | ~VciIoBridge(); |
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| 596 | |
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| 597 | void print_stats(); |
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| 598 | void clear_stats(); |
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| 599 | void print_trace(size_t mode = 0); |
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| 600 | |
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| 601 | |
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| 602 | private: |
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| 603 | void transition(); |
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| 604 | void genMoore(); |
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| 605 | }; |
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| 606 | |
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| 607 | }} |
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| 608 | |
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| 609 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */ |
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| 610 | |
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| 611 | // Local Variables: |
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| 612 | // tab-width: 4 |
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| 613 | // c-basic-offset: 4 |
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| 614 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 615 | // indent-tabs-mode: nil |
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| 616 | // End: |
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| 617 | |
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| 618 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 619 | |
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| 620 | |
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| 621 | |
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| 622 | |
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