1 | /* -*- c++ -*- |
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2 | * File : vci_io_bridge.h |
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3 | * Copyright (c) UPMC, Lip6, SoC |
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4 | * Date : 16/04/2012 |
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5 | * Authors: Cassio Fraga, Alain Greiner |
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6 | * |
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7 | * SOCLIB_LGPL_HEADER_BEGIN |
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8 | * |
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9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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10 | * |
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11 | * SoCLib is free software; you can redistribute it and/or modify it |
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12 | * under the terms of the GNU Lesser General Public License as published |
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13 | * by the Free Software Foundation; version 2.1 of the License. |
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14 | * |
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15 | * SoCLib is distributed in the hope that it will be useful, but |
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16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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18 | * Lesser General Public License for more details. |
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19 | * |
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20 | * You should have received a copy of the GNU Lesser General Public |
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21 | * License along with SoCLib; if not, write to the Free Software |
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22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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23 | * 02110-1301 USA |
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24 | * |
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25 | * SOCLIB_LGPL_HEADER_END |
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26 | */ |
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27 | ///////////////////////////////////////////////////////////////////////////////// |
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28 | // This TSAR component is a bridge to access external peripherals |
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29 | // connected to an external I/O bus (such as Hypertransport or PCIe). |
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30 | // AT the moment, the external I/O bus is modeled by a VCI VGMN component. |
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31 | // It connects three VCI networks: |
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32 | // - INT network : to receive both configuration requests from processors |
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33 | // or software driven data access to peripherals. |
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34 | // - RAM network : to send DMA transactions initiated by peripherals |
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35 | // directly to the RAM (or L3 caches). |
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36 | // - IOX network : to receive DMA transactions from peripherals, or to send |
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37 | // configuration or data transactions to peripherals. |
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38 | // |
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39 | // Regarding DMA transactions initiated by external peripherals, it provides |
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40 | // an - optional - IOMMU service : the 32 bits virtual address is translated |
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41 | // to a (up to) 40 bits physical address by a standard SoCLib generic TLB. |
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42 | // In case of TLB MISS, the DMA is stalled until the TLB is updated. |
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43 | // In case of page fault (illegal access), a VCI error is returned to the |
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44 | // faulty peripheral. |
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45 | ///////////////////////////////////////////////////////////////////////////////// |
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46 | // General Constraints: |
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47 | // |
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48 | // - All VCI fields have the same widths on the EXT and IOX networks. |
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49 | // - Only the VCI DATA field can differ between INT and EXT networks, |
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50 | // and the width must be 32 or 64 bits. |
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51 | // - The common VCI ADDRESS width cannot be larger than 64 bits. |
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52 | // - All VCI transactions must be included in a single cache line. |
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53 | // - Page Tables must have the format required by the SoCLib generic_tlb. |
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54 | // - IO's segments must be the same in INT and IOX networks |
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55 | // - Write operations on IOMMU configuration registers (PTPR, ACTIVE) can only |
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56 | // be done when DMA_TLB FSM is IDLE. It should, preferably, be done before |
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57 | // starting any transfers. Pseudo register INVAL may be modified any time. |
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58 | //////////////////////////////////////////////////////////////////////////////// |
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59 | |
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60 | |
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61 | ///////TODO List/////////////////////////////////////////////////////////////// |
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62 | // - Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit |
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63 | // (seulement 'data' et 'be') |
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64 | // - Traiter complêtement les codes d'erreur en réponse à une transaction |
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65 | // WTI write |
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66 | /////////////////////////////////////////////////////////////////////////////// |
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67 | |
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68 | #ifndef SOCLIB_CABA_VCI_IO_BRIDGE_H |
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69 | #define SOCLIB_CABA_VCI_IO_BRIDGE_H |
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70 | |
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71 | #include <inttypes.h> |
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72 | #include <systemc> |
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73 | #include "caba_base_module.h" |
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74 | #include "generic_fifo.h" |
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75 | #include "generic_tlb.h" |
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76 | #include "mapping_table.h" |
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77 | #include "address_decoding_table.h" |
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78 | #include "static_assert.h" |
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79 | #include "vci_initiator.h" |
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80 | #include "vci_target.h" |
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81 | #include "../../../include/soclib/io_bridge.h" |
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82 | |
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83 | namespace soclib { |
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84 | namespace caba { |
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85 | |
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86 | using namespace soclib::common; |
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87 | |
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88 | /////////////////////////////////////////////////////////////////////////////////// |
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89 | template<typename vci_param_int, |
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90 | typename vci_param_ext> |
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91 | class VciIoBridge |
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92 | /////////////////////////////////////////////////////////////////////////////////// |
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93 | : public soclib::caba::BaseModule |
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94 | { |
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95 | // Data field can have different widths on INT and EXT networks |
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96 | typedef typename vci_param_ext::fast_data_t ext_data_t; |
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97 | typedef typename vci_param_int::fast_data_t int_data_t; |
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98 | |
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99 | // Other fields must be equal |
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100 | typedef typename vci_param_int::fast_addr_t vci_addr_t; |
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101 | typedef typename vci_param_int::srcid_t vci_srcid_t; |
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102 | typedef typename vci_param_int::be_t vci_be_t; |
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103 | typedef typename vci_param_int::trdid_t vci_trdid_t; |
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104 | typedef typename vci_param_int::pktid_t vci_pktid_t; |
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105 | typedef typename vci_param_int::plen_t vci_plen_t; |
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106 | typedef typename vci_param_int::cmd_t vci_cmd_t; |
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107 | typedef typename vci_param_int::contig_t vci_contig_t; |
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108 | typedef typename vci_param_int::eop_t vci_eop_t; |
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109 | typedef typename vci_param_int::const_t vci_cons_t; |
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110 | typedef typename vci_param_int::wrap_t vci_wrap_t; |
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111 | typedef typename vci_param_int::clen_t vci_clen_t; |
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112 | typedef typename vci_param_int::cfixed_t vci_cfixed_t; |
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113 | typedef typename vci_param_int::rerror_t vci_rerror_t; |
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114 | |
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115 | enum |
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116 | { |
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117 | CACHE_LINE_MASK = 0xFFFFFFFFC0LL, |
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118 | PPN1_MASK = 0x0007FFFF, |
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119 | PPN2_MASK = 0x0FFFFFFF, |
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120 | K_PAGE_OFFSET_MASK = 0x00000FFF, |
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121 | M_PAGE_OFFSET_MASK = 0x001FFFFF, |
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122 | PTE2_LINE_OFFSET = 0x00007000, // bits 12,13,14. |
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123 | PTE1_LINE_OFFSET = 0x01E00000, // bits 21,22,23,24 |
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124 | }; |
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125 | |
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126 | // States for DMA_CMD FSM (from IOX to RAM) |
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127 | enum dma_cmd_fsm_state |
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128 | { |
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129 | DMA_CMD_IDLE, |
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130 | DMA_CMD_FIFO_PUT_CMD, |
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131 | DMA_CMD_FIFO_PUT_RSP, |
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132 | DMA_CMD_MISS_WAIT, |
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133 | DMA_CMD_WAIT_EOP, |
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134 | }; |
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135 | |
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136 | // States for DMA_RSP FSM (from RAM to IOX) |
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137 | enum dma_rsp_fsm_state |
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138 | { |
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139 | DMA_RSP_IDLE, |
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140 | DMA_RSP_FIFO_PUT, |
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141 | }; |
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142 | |
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143 | // States for TLB_MISS FSM |
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144 | enum dma_tlb_fsm_state |
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145 | { |
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146 | TLB_IDLE, |
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147 | TLB_MISS, |
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148 | TLB_PTE1_GET, |
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149 | TLB_PTE1_SELECT, |
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150 | TLB_PTE1_UPDT, |
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151 | TLB_PTE2_GET, |
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152 | TLB_PTE2_SELECT, |
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153 | TLB_PTE2_UPDT, |
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154 | TLB_WAIT, |
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155 | TLB_RETURN, |
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156 | TLB_INVAL_CHECK, |
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157 | }; |
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158 | |
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159 | // States for CONFIG_CMD FSM (from INT to IOX) |
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160 | enum config_cmd_fsm_state |
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161 | { |
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162 | CONFIG_CMD_IDLE, |
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163 | CONFIG_CMD_FIFO_PUT_CMD, |
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164 | CONFIG_CMD_FIFO_PUT_RSP, |
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165 | }; |
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166 | |
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167 | // states for CONFIG_RSP FSM (from IOX to INT) |
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168 | enum config_rsp_fsm_state |
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169 | { |
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170 | CONFIG_RSP_IDLE, |
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171 | CONFIG_RSP_FIFO_PUT, |
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172 | }; |
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173 | |
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174 | // States for MISS_WTI_CMD FSM (to INT network) |
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175 | enum miss_wti_cmd_state |
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176 | { |
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177 | MISS_WTI_CMD_IDLE, |
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178 | MISS_WTI_CMD_WTI, |
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179 | MISS_WTI_CMD_MISS, |
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180 | }; |
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181 | |
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182 | // States for MISS_WTI_RSP FSM (from INT network) |
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183 | enum miss_wti_rsp_state |
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184 | { |
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185 | MISS_WTI_RSP_IDLE, |
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186 | MISS_WTI_RSP_WTI, |
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187 | MISS_WTI_RSP_MISS, |
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188 | }; |
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189 | |
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190 | // PKTID values for TLB MISS and WTI transactions |
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191 | enum pktid_values_e |
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192 | { |
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193 | PKTID_READ = 0x0, // TSAR code for read data uncached |
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194 | PKTID_WRITE = 0x4, // TSAR code for write |
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195 | }; |
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196 | |
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197 | // Miss types for iotlb |
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198 | enum tlb_miss_type_e |
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199 | { |
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200 | PTE1_MISS, |
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201 | PTE2_MISS, |
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202 | }; |
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203 | |
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204 | public: |
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205 | sc_in<bool> p_clk; |
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206 | sc_in<bool> p_resetn; |
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207 | sc_in<bool>* p_irq[32]; // not always constructed |
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208 | |
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209 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_ram; |
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210 | |
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211 | soclib::caba::VciTarget<vci_param_ext> p_vci_tgt_iox; |
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212 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_iox; |
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213 | |
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214 | soclib::caba::VciTarget<vci_param_int> p_vci_tgt_int; |
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215 | soclib::caba::VciInitiator<vci_param_int> p_vci_ini_int; |
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216 | |
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217 | private: |
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218 | const size_t m_words; |
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219 | const bool m_has_irqs; |
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220 | |
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221 | // INT & IOX Networks |
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222 | std::list<soclib::common::Segment> m_int_seglist; |
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223 | const vci_srcid_t m_int_srcid; // local SRCID on INT network |
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224 | std::list<soclib::common::Segment> m_iox_seglist; |
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225 | |
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226 | // TLB parameters |
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227 | const size_t m_iotlb_ways; |
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228 | const size_t m_iotlb_sets; |
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229 | |
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230 | // debug variables |
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231 | uint32_t m_debug_start_cycle; |
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232 | bool m_debug_ok; |
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233 | bool m_debug_activated; |
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234 | |
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235 | /////////////////////////////// |
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236 | // MEMORY MAPPED REGISTERS |
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237 | /////////////////////////////// |
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238 | sc_signal<uint32_t> r_iommu_ptpr; // page table pointer register |
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239 | sc_signal<bool> r_iommu_active; // iotlb mode |
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240 | sc_signal<uint32_t> r_iommu_bvar; // iommu bad virtual address |
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241 | sc_signal<uint32_t> r_iommu_etr; // iommu error type |
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242 | sc_signal<uint32_t> r_iommu_bad_id; // SRCID of faulty peripheral |
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243 | sc_signal<uint32_t> r_iommu_wti_enable; // enable WTI transactions when true |
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244 | sc_signal<vci_addr_t> r_iommu_wti_paddr; // address of IOMMU WTI |
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245 | sc_signal<vci_addr_t>* r_iommu_peri_wti; // array[32] WTI for peripherals |
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246 | |
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247 | /////////////////////////////////// |
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248 | // DMA_CMD FSM REGISTERS |
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249 | /////////////////////////////////// |
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250 | sc_signal<int> r_dma_cmd_fsm; |
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251 | sc_signal<uint32_t> r_dma_cmd_vaddr; // input virtual address |
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252 | sc_signal<vci_addr_t> r_dma_cmd_paddr; // output physical address |
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253 | |
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254 | /////////////////////////////////// |
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255 | // DMA_RSP FSM REGISTERS |
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256 | /////////////////////////////////// |
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257 | sc_signal<int> r_dma_rsp_fsm; |
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258 | |
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259 | /////////////////////////////////// |
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260 | // CONFIG_CMD FSM REGISTERS |
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261 | /////////////////////////////////// |
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262 | sc_signal<int> r_config_cmd_fsm; |
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263 | sc_signal<uint32_t> r_config_cmd_rdata; |
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264 | sc_signal<bool> r_config_cmd_error; |
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265 | sc_signal<uint32_t> r_config_cmd_inval_vaddr; |
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266 | |
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267 | /////////////////////////////////// |
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268 | // CONFIG_RSP FSM REGISTERS |
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269 | /////////////////////////////////// |
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270 | sc_signal<int> r_config_rsp_fsm; |
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271 | |
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272 | /////////////////////////////////// |
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273 | // TLB FSM REGISTERS |
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274 | /////////////////////////////////// |
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275 | sc_signal<int> r_tlb_fsm; // state register |
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276 | sc_signal<bool> r_waiting_transaction; // Flag for returning from |
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277 | sc_signal<int> r_tlb_miss_type; |
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278 | sc_signal<bool> r_tlb_miss_error; |
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279 | |
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280 | sc_signal<vci_addr_t> r_tlb_paddr; // physical address of pte |
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281 | sc_signal<uint32_t> r_tlb_pte_flags; // pte1 or first word of pte2 |
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282 | sc_signal<uint32_t> r_tlb_pte_ppn; // second word of pte2 |
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283 | sc_signal<size_t> r_tlb_way; // selected way in tlb |
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284 | sc_signal<size_t> r_tlb_set; // selected set in tlb |
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285 | |
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286 | uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs |
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287 | sc_signal<bool> r_tlb_buf_valid; // one valit flag for all PTEs |
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288 | sc_signal<vci_addr_t> r_tlb_buf_tag; // cache line number |
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289 | sc_signal<vci_addr_t> r_tlb_buf_vaddr; // virtual address first PTE |
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290 | sc_signal<bool> r_tlb_buf_big_page; // ??? |
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291 | |
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292 | /////////////////////////////////// |
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293 | // MISS_WTI_CMD FSM REGISTERS |
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294 | /////////////////////////////////// |
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295 | sc_signal<int> r_miss_wti_cmd_fsm; |
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296 | sc_signal<size_t> r_miss_wti_cmd_index; |
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297 | |
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298 | /////////////////////////////////// |
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299 | // MISS_WTI_RSP FSM REGISTERS |
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300 | /////////////////////////////////// |
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301 | sc_signal<int> r_miss_wti_rsp_fsm; |
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302 | sc_signal<bool> r_miss_wti_rsp_error; |
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303 | sc_signal<size_t> r_miss_wti_rsp_count; |
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304 | |
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305 | ///////////////////////////////////////////////////// |
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306 | // ALLOCATORS for CONFIG_RSP fifo & DMA_RSP fifo |
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307 | ///////////////////////////////////////////////////// |
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308 | sc_signal<bool> r_alloc_fifo_config_rsp_local; |
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309 | sc_signal<bool> r_alloc_fifo_dma_rsp_local; |
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310 | |
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311 | ////////////////////////////////// |
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312 | // IRQ FSM registers |
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313 | ////////////////////////////////// |
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314 | sc_signal<bool>* r_irq_pending; // array[32] |
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315 | sc_signal<bool>* r_irq_request; // array[32] |
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316 | |
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317 | ////////////////////////////////////////////////////////////////// |
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318 | // IOTLB |
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319 | ////////////////////////////////////////////////////////////////// |
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320 | GenericTlb<vci_addr_t> r_iotlb; |
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321 | |
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322 | ////////////////////////////////////////////////////////////////// |
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323 | // Inter-FSM communications |
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324 | ////////////////////////////////////////////////////////////////// |
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325 | |
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326 | // between DMA_CMD and TLB FSM |
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327 | sc_signal<bool> r_dma_tlb_req; |
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328 | |
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329 | // between CONFIG_CMD FSM and TLB FSM |
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330 | sc_signal<bool> r_config_tlb_req; |
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331 | |
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332 | // between TLB FSM and MISS_WTI FSM |
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333 | sc_signal<bool> r_tlb_miss_req; |
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334 | |
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335 | ///////////////////////// |
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336 | // FIFOs |
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337 | ///////////////////////// |
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338 | |
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339 | // ouput FIFO to VCI INI port on RAM network (VCI command) |
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340 | GenericFifo<vci_addr_t> m_dma_cmd_addr_fifo; |
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341 | GenericFifo<vci_srcid_t> m_dma_cmd_srcid_fifo; |
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342 | GenericFifo<vci_trdid_t> m_dma_cmd_trdid_fifo; |
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343 | GenericFifo<vci_pktid_t> m_dma_cmd_pktid_fifo; |
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344 | GenericFifo<vci_be_t> m_dma_cmd_be_fifo; |
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345 | GenericFifo<vci_cmd_t> m_dma_cmd_cmd_fifo; |
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346 | GenericFifo<vci_contig_t> m_dma_cmd_contig_fifo; |
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347 | GenericFifo<ext_data_t> m_dma_cmd_data_fifo; |
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348 | GenericFifo<vci_eop_t> m_dma_cmd_eop_fifo; |
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349 | GenericFifo<vci_cons_t> m_dma_cmd_cons_fifo; |
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350 | GenericFifo<vci_plen_t> m_dma_cmd_plen_fifo; |
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351 | GenericFifo<vci_wrap_t> m_dma_cmd_wrap_fifo; |
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352 | GenericFifo<vci_cfixed_t> m_dma_cmd_cfixed_fifo; |
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353 | GenericFifo<vci_clen_t> m_dma_cmd_clen_fifo; |
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354 | |
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355 | // output FIFO to VCI TGT port on IOX network (VCI response) |
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356 | GenericFifo<ext_data_t> m_dma_rsp_data_fifo; |
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357 | GenericFifo<vci_srcid_t> m_dma_rsp_rsrcid_fifo; |
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358 | GenericFifo<vci_trdid_t> m_dma_rsp_rtrdid_fifo; |
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359 | GenericFifo<vci_pktid_t> m_dma_rsp_rpktid_fifo; |
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360 | GenericFifo<vci_eop_t> m_dma_rsp_reop_fifo; |
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361 | GenericFifo<vci_rerror_t> m_dma_rsp_rerror_fifo; |
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362 | |
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363 | // output FIFO to VCI INI port on IOX network (VCI command) |
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364 | GenericFifo<vci_addr_t> m_config_cmd_addr_fifo; |
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365 | GenericFifo<vci_srcid_t> m_config_cmd_srcid_fifo; |
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366 | GenericFifo<vci_trdid_t> m_config_cmd_trdid_fifo; |
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367 | GenericFifo<vci_pktid_t> m_config_cmd_pktid_fifo; |
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368 | GenericFifo<vci_be_t> m_config_cmd_be_fifo; |
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369 | GenericFifo<vci_cmd_t> m_config_cmd_cmd_fifo; |
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370 | GenericFifo<vci_contig_t> m_config_cmd_contig_fifo; |
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371 | GenericFifo<ext_data_t> m_config_cmd_data_fifo; |
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372 | GenericFifo<vci_eop_t> m_config_cmd_eop_fifo; |
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373 | GenericFifo<vci_cons_t> m_config_cmd_cons_fifo; |
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374 | GenericFifo<vci_plen_t> m_config_cmd_plen_fifo; |
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375 | GenericFifo<vci_wrap_t> m_config_cmd_wrap_fifo; |
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376 | GenericFifo<vci_cfixed_t> m_config_cmd_cfixed_fifo; |
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377 | GenericFifo<vci_clen_t> m_config_cmd_clen_fifo; |
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378 | |
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379 | // output FIFO to VCI TGT port on INT network (VCI response) |
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380 | GenericFifo<int_data_t> m_config_rsp_data_fifo; |
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381 | GenericFifo<vci_srcid_t> m_config_rsp_rsrcid_fifo; |
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382 | GenericFifo<vci_trdid_t> m_config_rsp_rtrdid_fifo; |
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383 | GenericFifo<vci_pktid_t> m_config_rsp_rpktid_fifo; |
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384 | GenericFifo<vci_eop_t> m_config_rsp_reop_fifo; |
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385 | GenericFifo<vci_rerror_t> m_config_rsp_rerror_fifo; |
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386 | |
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387 | |
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388 | //////////////////////////////// |
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389 | // Activity counters |
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390 | //////////////////////////////// |
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391 | |
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392 | uint32_t m_cpt_total_cycles; // total number of cycles |
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393 | |
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394 | // TLB activity counters |
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395 | uint32_t m_cpt_iotlb_read; // number of iotlb read |
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396 | uint32_t m_cpt_iotlb_miss; // number of iotlb miss |
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397 | uint32_t m_cost_iotlb_miss; // number of wait cycles (not treatment itself) |
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398 | uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions |
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399 | uint32_t m_cost_iotlbmiss_transaction; // cumulated duration tlb miss transactions |
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400 | |
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401 | //Transaction Tabs (TRTs) activity counters |
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402 | uint32_t m_cpt_trt_dma_full; // DMA TRT full when a new command arrives |
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403 | uint32_t m_cpt_trt_dma_full_cost; // total number of cycles blocked |
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404 | uint32_t m_cpt_trt_config_full; // Config TRT full when a new command arrives |
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405 | uint32_t m_cpt_trt_config_full_cost; // total number of cycles blocked |
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406 | |
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407 | // FSM activity counters |
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408 | // unused on print_stats |
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409 | uint32_t m_cpt_fsm_dma_cmd [32]; |
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410 | uint32_t m_cpt_fsm_dma_rsp [32]; |
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411 | uint32_t m_cpt_fsm_tlb [32]; |
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412 | uint32_t m_cpt_fsm_config_cmd [32]; |
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413 | uint32_t m_cpt_fsm_config_rsp [32]; |
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414 | uint32_t m_cpt_fsm_miss_wti_cmd [32]; |
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415 | uint32_t m_cpt_fsm_miss_wti_rsp [32]; |
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416 | |
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417 | protected: |
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418 | SC_HAS_PROCESS(VciIoBridge); |
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419 | |
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420 | public: |
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421 | VciIoBridge( |
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422 | sc_module_name insname, |
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423 | const soclib::common::MappingTable &mt_ext, // external network |
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424 | const soclib::common::MappingTable &mt_int, // internal network |
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425 | const soclib::common::MappingTable &mt_iox, // iox network |
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426 | const soclib::common::IntTab &int_tgtid, // INT network TGTID |
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427 | const soclib::common::IntTab &int_srcid, // INT network SRCID |
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428 | const soclib::common::IntTab &iox_tgtid, // IOX network TGTID |
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429 | const bool has_irqs, // component has irq ports |
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430 | const size_t dcache_words, |
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431 | const size_t iotlb_ways, |
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432 | const size_t iotlb_sets, |
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433 | const uint32_t debug_start_cycle, |
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434 | const bool debug_ok ); |
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435 | |
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436 | ~VciIoBridge(); |
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437 | |
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438 | void print_stats(); |
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439 | void clear_stats(); |
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440 | void print_trace(size_t mode = 0); |
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441 | |
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442 | |
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443 | private: |
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444 | void transition(); |
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445 | void genMoore(); |
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446 | }; |
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447 | |
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448 | }} |
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449 | |
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450 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */ |
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451 | |
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452 | // Local Variables: |
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453 | // tab-width: 4 |
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454 | // c-basic-offset: 4 |
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455 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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456 | // indent-tabs-mode: nil |
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457 | // End: |
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458 | |
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459 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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460 | |
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461 | |
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462 | |
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463 | |
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