[331] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_mem_cache.h |
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| 3 | * Date : 26/10/2008 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Alain Greiner / Eric Guthmuller |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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| 27 | * Maintainers: alain eric.guthmuller@polytechnique.edu |
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| 28 | * cesar.fuguet-tortolero@lip6.fr |
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| 29 | * alexandre.joannou@lip6.fr |
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| 30 | */ |
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| 31 | |
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| 32 | #ifndef SOCLIB_CABA_MEM_CACHE_H |
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| 33 | #define SOCLIB_CABA_MEM_CACHE_H |
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| 34 | |
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| 35 | #include <inttypes.h> |
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| 36 | #include <systemc> |
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| 37 | #include <list> |
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| 38 | #include <cassert> |
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| 39 | #include "arithmetics.h" |
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| 40 | #include "alloc_elems.h" |
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| 41 | #include "caba_base_module.h" |
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| 42 | #include "vci_target.h" |
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| 43 | #include "vci_initiator.h" |
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| 44 | #include "generic_fifo.h" |
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| 45 | #include "mapping_table.h" |
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| 46 | #include "int_tab.h" |
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| 47 | #include "generic_llsc_global_table.h" |
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| 48 | #include "mem_cache_directory.h" |
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| 49 | #include "xram_transaction.h" |
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| 50 | #include "update_tab.h" |
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| 51 | #include "dspin_interface.h" |
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| 52 | #include "dspin_dhccp_param.h" |
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| 53 | |
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[395] | 54 | #define TRT_ENTRIES 4 // Number of entries in TRT |
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| 55 | #define UPT_ENTRIES 4 // Number of entries in UPT |
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| 56 | #define HEAP_ENTRIES 1024 // Number of entries in HEAP |
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[331] | 57 | |
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| 58 | namespace soclib { namespace caba { |
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[395] | 59 | |
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[331] | 60 | using namespace sc_core; |
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| 61 | |
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[385] | 62 | template<typename vci_param_int, |
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| 63 | typename vci_param_ext, |
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| 64 | size_t dspin_in_width, |
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| 65 | size_t dspin_out_width> |
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[331] | 66 | class VciMemCache |
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| 67 | : public soclib::caba::BaseModule |
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| 68 | { |
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[385] | 69 | typedef typename vci_param_int::fast_addr_t addr_t; |
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| 70 | |
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| 71 | typedef typename sc_dt::sc_uint<64> wide_data_t; |
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| 72 | |
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[331] | 73 | typedef uint32_t data_t; |
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| 74 | typedef uint32_t tag_t; |
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| 75 | typedef uint32_t be_t; |
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| 76 | typedef uint32_t copy_t; |
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| 77 | |
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| 78 | /* States of the TGT_CMD fsm */ |
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| 79 | enum tgt_cmd_fsm_state_e{ |
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| 80 | TGT_CMD_IDLE, |
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| 81 | TGT_CMD_READ, |
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| 82 | TGT_CMD_WRITE, |
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| 83 | TGT_CMD_CAS |
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| 84 | }; |
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| 85 | |
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| 86 | /* States of the TGT_RSP fsm */ |
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[395] | 87 | enum tgt_rsp_fsm_state_e |
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| 88 | { |
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[331] | 89 | TGT_RSP_READ_IDLE, |
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| 90 | TGT_RSP_WRITE_IDLE, |
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| 91 | TGT_RSP_CAS_IDLE, |
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| 92 | TGT_RSP_XRAM_IDLE, |
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| 93 | TGT_RSP_INIT_IDLE, |
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| 94 | TGT_RSP_CLEANUP_IDLE, |
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| 95 | TGT_RSP_READ, |
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| 96 | TGT_RSP_WRITE, |
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| 97 | TGT_RSP_CAS, |
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| 98 | TGT_RSP_XRAM, |
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| 99 | TGT_RSP_INIT, |
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| 100 | TGT_RSP_CLEANUP |
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| 101 | }; |
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| 102 | |
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| 103 | /* States of the DSPIN_TGT fsm */ |
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[395] | 104 | enum cc_receive_fsm_state_e |
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| 105 | { |
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[331] | 106 | CC_RECEIVE_IDLE, |
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| 107 | CC_RECEIVE_CLEANUP, |
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| 108 | CC_RECEIVE_MULTI_ACK |
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| 109 | }; |
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| 110 | |
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| 111 | /* States of the CC_SEND fsm */ |
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[395] | 112 | enum cc_send_fsm_state_e |
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| 113 | { |
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[331] | 114 | CC_SEND_XRAM_RSP_IDLE, |
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| 115 | CC_SEND_WRITE_IDLE, |
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| 116 | CC_SEND_CAS_IDLE, |
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| 117 | CC_SEND_CLEANUP_IDLE, |
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| 118 | CC_SEND_CLEANUP_ACK, |
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| 119 | CC_SEND_XRAM_RSP_BRDCAST_HEADER, |
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| 120 | CC_SEND_XRAM_RSP_BRDCAST_NLINE, |
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| 121 | CC_SEND_XRAM_RSP_INVAL_HEADER, |
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| 122 | CC_SEND_XRAM_RSP_INVAL_NLINE, |
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| 123 | CC_SEND_WRITE_BRDCAST_HEADER, |
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| 124 | CC_SEND_WRITE_BRDCAST_NLINE, |
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| 125 | CC_SEND_WRITE_UPDT_HEADER, |
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| 126 | CC_SEND_WRITE_UPDT_NLINE, |
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| 127 | CC_SEND_WRITE_UPDT_DATA, |
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| 128 | CC_SEND_CAS_BRDCAST_HEADER, |
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| 129 | CC_SEND_CAS_BRDCAST_NLINE, |
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| 130 | CC_SEND_CAS_UPDT_HEADER, |
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| 131 | CC_SEND_CAS_UPDT_NLINE, |
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| 132 | CC_SEND_CAS_UPDT_DATA, |
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| 133 | CC_SEND_CAS_UPDT_DATA_HIGH |
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| 134 | }; |
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| 135 | |
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| 136 | /* States of the MULTI_ACK fsm */ |
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[395] | 137 | enum multi_ack_fsm_state_e |
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| 138 | { |
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[331] | 139 | MULTI_ACK_IDLE, |
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| 140 | MULTI_ACK_UPT_LOCK, |
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| 141 | MULTI_ACK_UPT_CLEAR, |
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| 142 | MULTI_ACK_WRITE_RSP |
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| 143 | }; |
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| 144 | |
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| 145 | /* States of the READ fsm */ |
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[395] | 146 | enum read_fsm_state_e |
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| 147 | { |
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[331] | 148 | READ_IDLE, |
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| 149 | READ_DIR_REQ, |
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| 150 | READ_DIR_LOCK, |
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| 151 | READ_DIR_HIT, |
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| 152 | READ_HEAP_REQ, |
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| 153 | READ_HEAP_LOCK, |
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| 154 | READ_HEAP_WRITE, |
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| 155 | READ_HEAP_ERASE, |
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| 156 | READ_HEAP_LAST, |
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| 157 | READ_RSP, |
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| 158 | READ_TRT_LOCK, |
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| 159 | READ_TRT_SET, |
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| 160 | READ_TRT_REQ |
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| 161 | }; |
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| 162 | |
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| 163 | /* States of the WRITE fsm */ |
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[395] | 164 | enum write_fsm_state_e |
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| 165 | { |
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[331] | 166 | WRITE_IDLE, |
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| 167 | WRITE_NEXT, |
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| 168 | WRITE_DIR_REQ, |
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| 169 | WRITE_DIR_LOCK, |
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| 170 | WRITE_DIR_READ, |
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| 171 | WRITE_DIR_HIT, |
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| 172 | WRITE_UPT_LOCK, |
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| 173 | WRITE_UPT_HEAP_LOCK, |
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| 174 | WRITE_UPT_REQ, |
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| 175 | WRITE_UPT_NEXT, |
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| 176 | WRITE_UPT_DEC, |
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| 177 | WRITE_RSP, |
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| 178 | WRITE_MISS_TRT_LOCK, |
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| 179 | WRITE_MISS_TRT_DATA, |
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| 180 | WRITE_MISS_TRT_SET, |
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| 181 | WRITE_MISS_XRAM_REQ, |
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| 182 | WRITE_BC_TRT_LOCK, |
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| 183 | WRITE_BC_UPT_LOCK, |
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| 184 | WRITE_BC_DIR_INVAL, |
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| 185 | WRITE_BC_CC_SEND, |
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| 186 | WRITE_BC_XRAM_REQ, |
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| 187 | WRITE_WAIT |
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| 188 | }; |
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| 189 | |
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| 190 | /* States of the IXR_RSP fsm */ |
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[395] | 191 | enum ixr_rsp_fsm_state_e |
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| 192 | { |
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[331] | 193 | IXR_RSP_IDLE, |
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| 194 | IXR_RSP_ACK, |
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| 195 | IXR_RSP_TRT_ERASE, |
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| 196 | IXR_RSP_TRT_READ |
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| 197 | }; |
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| 198 | |
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| 199 | /* States of the XRAM_RSP fsm */ |
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[395] | 200 | enum xram_rsp_fsm_state_e |
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| 201 | { |
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[331] | 202 | XRAM_RSP_IDLE, |
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| 203 | XRAM_RSP_TRT_COPY, |
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| 204 | XRAM_RSP_TRT_DIRTY, |
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| 205 | XRAM_RSP_DIR_LOCK, |
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| 206 | XRAM_RSP_DIR_UPDT, |
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| 207 | XRAM_RSP_DIR_RSP, |
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| 208 | XRAM_RSP_INVAL_LOCK, |
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| 209 | XRAM_RSP_INVAL_WAIT, |
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| 210 | XRAM_RSP_INVAL, |
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| 211 | XRAM_RSP_WRITE_DIRTY, |
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| 212 | XRAM_RSP_HEAP_REQ, |
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| 213 | XRAM_RSP_HEAP_ERASE, |
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| 214 | XRAM_RSP_HEAP_LAST, |
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| 215 | XRAM_RSP_ERROR_ERASE, |
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| 216 | XRAM_RSP_ERROR_RSP |
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| 217 | }; |
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| 218 | |
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| 219 | /* States of the IXR_CMD fsm */ |
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[395] | 220 | enum ixr_cmd_fsm_state_e |
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| 221 | { |
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[331] | 222 | IXR_CMD_READ_IDLE, |
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| 223 | IXR_CMD_WRITE_IDLE, |
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| 224 | IXR_CMD_CAS_IDLE, |
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| 225 | IXR_CMD_XRAM_IDLE, |
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[395] | 226 | IXR_CMD_READ, |
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| 227 | IXR_CMD_WRITE, |
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| 228 | IXR_CMD_CAS, |
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| 229 | IXR_CMD_XRAM |
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[331] | 230 | }; |
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| 231 | |
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| 232 | /* States of the CAS fsm */ |
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[395] | 233 | enum cas_fsm_state_e |
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| 234 | { |
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[331] | 235 | CAS_IDLE, |
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| 236 | CAS_DIR_REQ, |
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| 237 | CAS_DIR_LOCK, |
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| 238 | CAS_DIR_HIT_READ, |
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| 239 | CAS_DIR_HIT_COMPARE, |
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| 240 | CAS_DIR_HIT_WRITE, |
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| 241 | CAS_UPT_LOCK, |
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| 242 | CAS_UPT_HEAP_LOCK, |
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| 243 | CAS_UPT_REQ, |
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| 244 | CAS_UPT_NEXT, |
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| 245 | CAS_BC_TRT_LOCK, |
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| 246 | CAS_BC_UPT_LOCK, |
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| 247 | CAS_BC_DIR_INVAL, |
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| 248 | CAS_BC_CC_SEND, |
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| 249 | CAS_BC_XRAM_REQ, |
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| 250 | CAS_RSP_FAIL, |
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| 251 | CAS_RSP_SUCCESS, |
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| 252 | CAS_MISS_TRT_LOCK, |
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| 253 | CAS_MISS_TRT_SET, |
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| 254 | CAS_MISS_XRAM_REQ, |
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| 255 | CAS_WAIT |
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| 256 | }; |
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| 257 | |
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| 258 | /* States of the CLEANUP fsm */ |
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[395] | 259 | enum cleanup_fsm_state_e |
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| 260 | { |
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[331] | 261 | CLEANUP_IDLE, |
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| 262 | CLEANUP_GET_NLINE, |
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| 263 | CLEANUP_DIR_REQ, |
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| 264 | CLEANUP_DIR_LOCK, |
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| 265 | CLEANUP_DIR_WRITE, |
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| 266 | CLEANUP_HEAP_REQ, |
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| 267 | CLEANUP_HEAP_LOCK, |
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| 268 | CLEANUP_HEAP_SEARCH, |
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| 269 | CLEANUP_HEAP_CLEAN, |
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| 270 | CLEANUP_HEAP_FREE, |
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| 271 | CLEANUP_UPT_LOCK, |
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| 272 | CLEANUP_UPT_DECREMENT, |
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| 273 | CLEANUP_UPT_CLEAR, |
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| 274 | CLEANUP_WRITE_RSP, |
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| 275 | CLEANUP_SEND_ACK |
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| 276 | }; |
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| 277 | |
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| 278 | /* States of the ALLOC_DIR fsm */ |
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[395] | 279 | enum alloc_dir_fsm_state_e |
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| 280 | { |
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[331] | 281 | ALLOC_DIR_RESET, |
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| 282 | ALLOC_DIR_READ, |
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| 283 | ALLOC_DIR_WRITE, |
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| 284 | ALLOC_DIR_CAS, |
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| 285 | ALLOC_DIR_CLEANUP, |
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| 286 | ALLOC_DIR_XRAM_RSP |
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| 287 | }; |
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| 288 | |
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| 289 | /* States of the ALLOC_TRT fsm */ |
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[395] | 290 | enum alloc_trt_fsm_state_e |
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| 291 | { |
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[331] | 292 | ALLOC_TRT_READ, |
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| 293 | ALLOC_TRT_WRITE, |
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| 294 | ALLOC_TRT_CAS, |
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| 295 | ALLOC_TRT_XRAM_RSP, |
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| 296 | ALLOC_TRT_IXR_RSP |
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| 297 | }; |
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| 298 | |
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| 299 | /* States of the ALLOC_UPT fsm */ |
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[395] | 300 | enum alloc_upt_fsm_state_e |
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| 301 | { |
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[331] | 302 | ALLOC_UPT_WRITE, |
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| 303 | ALLOC_UPT_XRAM_RSP, |
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| 304 | ALLOC_UPT_MULTI_ACK, |
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| 305 | ALLOC_UPT_CLEANUP, |
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| 306 | ALLOC_UPT_CAS |
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| 307 | }; |
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| 308 | |
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| 309 | /* States of the ALLOC_HEAP fsm */ |
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[395] | 310 | enum alloc_heap_fsm_state_e |
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| 311 | { |
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[331] | 312 | ALLOC_HEAP_RESET, |
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| 313 | ALLOC_HEAP_READ, |
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| 314 | ALLOC_HEAP_WRITE, |
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| 315 | ALLOC_HEAP_CAS, |
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| 316 | ALLOC_HEAP_CLEANUP, |
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| 317 | ALLOC_HEAP_XRAM_RSP |
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| 318 | }; |
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| 319 | |
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| 320 | /* transaction type, pktid field */ |
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| 321 | enum transaction_type_e |
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| 322 | { |
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| 323 | // b3 unused |
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| 324 | // b2 READ / NOT READ |
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| 325 | // Si READ |
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| 326 | // b1 DATA / INS |
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| 327 | // b0 UNC / MISS |
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| 328 | // Si NOT READ |
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| 329 | // b1 accÚs table llsc type SW / other |
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| 330 | // b2 WRITE/CAS/LL/SC |
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| 331 | TYPE_READ_DATA_UNC = 0x0, |
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| 332 | TYPE_READ_DATA_MISS = 0x1, |
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| 333 | TYPE_READ_INS_UNC = 0x2, |
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| 334 | TYPE_READ_INS_MISS = 0x3, |
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| 335 | TYPE_WRITE = 0x4, |
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| 336 | TYPE_CAS = 0x5, |
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| 337 | TYPE_LL = 0x6, |
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| 338 | TYPE_SC = 0x7 |
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| 339 | }; |
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| 340 | |
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| 341 | /* SC return values */ |
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| 342 | enum sc_status_type_e |
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| 343 | { |
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| 344 | SC_SUCCESS = 0x00000000, |
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| 345 | SC_FAIL = 0x00000001 |
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| 346 | }; |
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| 347 | |
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| 348 | // debug variables (for each FSM) |
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| 349 | bool m_debug_global; |
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| 350 | bool m_debug_tgt_cmd_fsm; |
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| 351 | bool m_debug_tgt_rsp_fsm; |
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| 352 | bool m_debug_cc_send_fsm; |
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| 353 | bool m_debug_cc_receive_fsm; |
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| 354 | bool m_debug_multi_ack_fsm; |
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| 355 | bool m_debug_read_fsm; |
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| 356 | bool m_debug_write_fsm; |
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| 357 | bool m_debug_cas_fsm; |
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| 358 | bool m_debug_cleanup_fsm; |
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| 359 | bool m_debug_ixr_cmd_fsm; |
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| 360 | bool m_debug_ixr_rsp_fsm; |
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| 361 | bool m_debug_xram_rsp_fsm; |
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| 362 | bool m_debug_previous_hit; |
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| 363 | size_t m_debug_previous_count; |
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| 364 | |
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| 365 | bool m_monitor_ok; |
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[385] | 366 | addr_t m_monitor_base; |
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| 367 | addr_t m_monitor_length; |
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[331] | 368 | |
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| 369 | // instrumentation counters |
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| 370 | uint32_t m_cpt_cycles; // Counter of cycles |
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| 371 | uint32_t m_cpt_read; // Number of READ transactions |
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| 372 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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| 373 | uint32_t m_cpt_write; // Number of WRITE transactions |
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| 374 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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| 375 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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| 376 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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| 377 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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| 378 | uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt |
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| 379 | uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt |
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| 380 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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| 381 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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| 382 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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| 383 | uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL |
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| 384 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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| 385 | uint32_t m_cpt_ll; // Number of LL transactions |
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| 386 | uint32_t m_cpt_sc; // Number of SC transactions |
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| 387 | uint32_t m_cpt_cas; // Number of CAS transactions |
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| 388 | |
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| 389 | size_t m_prev_count; |
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| 390 | |
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| 391 | protected: |
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| 392 | |
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| 393 | SC_HAS_PROCESS(VciMemCache); |
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| 394 | |
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| 395 | public: |
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[385] | 396 | sc_in<bool> p_clk; |
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| 397 | sc_in<bool> p_resetn; |
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| 398 | soclib::caba::VciTarget<vci_param_int> p_vci_tgt; |
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| 399 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; |
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| 400 | soclib::caba::DspinInput<dspin_in_width> p_dspin_in; |
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| 401 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; |
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[331] | 402 | |
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| 403 | VciMemCache( |
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| 404 | sc_module_name name, // Instance Name |
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[395] | 405 | const soclib::common::MappingTable &mtp, // Mapping table direct network |
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| 406 | const soclib::common::MappingTable &mtx, // Mapping table external network |
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[346] | 407 | const soclib::common::IntTab &srcid_x, // global index on external network |
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| 408 | const soclib::common::IntTab &tgtid_d, // global index on direct network |
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| 409 | const size_t cc_global_id, // global index on cc network |
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| 410 | const size_t nways, // Number of ways per set |
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| 411 | const size_t nsets, // Number of sets |
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| 412 | const size_t nwords, // Number of words per line |
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| 413 | const size_t max_copies, // max number of copies in heap |
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[395] | 414 | const size_t heap_size=HEAP_ENTRIES, |
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| 415 | const size_t trt_lines=TRT_ENTRIES, |
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| 416 | const size_t upt_lines=UPT_ENTRIES, |
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[346] | 417 | const size_t debug_start_cycle=0, |
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| 418 | const bool debug_ok=false ); |
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[331] | 419 | |
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| 420 | ~VciMemCache(); |
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| 421 | |
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| 422 | void print_stats(); |
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| 423 | void print_trace(); |
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[385] | 424 | void copies_monitor(addr_t addr); |
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| 425 | void start_monitor(addr_t addr, addr_t length); |
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[331] | 426 | void stop_monitor(); |
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| 427 | |
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| 428 | private: |
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| 429 | |
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| 430 | void transition(); |
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| 431 | void genMoore(); |
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[385] | 432 | void check_monitor( const char *buf, addr_t addr, data_t data, bool read); |
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[331] | 433 | |
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| 434 | // Component attributes |
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[346] | 435 | std::list<soclib::common::Segment> m_seglist; // segments allocated to memcache |
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| 436 | size_t m_nseg; // number of segments |
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| 437 | soclib::common::Segment **m_seg; // array of segments pointers |
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| 438 | const size_t m_srcid_x; // global index on external network |
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| 439 | const size_t m_initiators; // Number of initiators |
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| 440 | const size_t m_heap_size; // Size of the heap |
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| 441 | const size_t m_ways; // Number of ways in a set |
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| 442 | const size_t m_sets; // Number of cache sets |
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| 443 | const size_t m_words; // Number of words in a line |
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| 444 | const size_t m_cc_global_id; // global_index on cc network |
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| 445 | size_t m_debug_start_cycle; |
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| 446 | bool m_debug_ok; |
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| 447 | uint32_t m_trt_lines; |
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| 448 | TransactionTab m_trt; // xram transaction table |
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| 449 | uint32_t m_upt_lines; |
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| 450 | UpdateTab m_upt; // pending update & invalidate |
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| 451 | CacheDirectory m_cache_directory; // data cache directory |
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| 452 | CacheData m_cache_data; // data array[set][way][word] |
---|
| 453 | HeapDirectory m_heap; // heap for copies |
---|
| 454 | size_t m_max_copies; // max number of copies in heap |
---|
[331] | 455 | GenericLLSCGlobalTable |
---|
[346] | 456 | < 32 , // number of slots |
---|
| 457 | 4096, // number of processors in the system |
---|
[385] | 458 | 8000, // registration life (# of LL operations) |
---|
| 459 | addr_t > m_llsc_table; // ll/sc global registration table |
---|
[331] | 460 | |
---|
| 461 | // adress masks |
---|
[385] | 462 | const soclib::common::AddressMaskingTable<addr_t> m_x; |
---|
| 463 | const soclib::common::AddressMaskingTable<addr_t> m_y; |
---|
| 464 | const soclib::common::AddressMaskingTable<addr_t> m_z; |
---|
| 465 | const soclib::common::AddressMaskingTable<addr_t> m_nline; |
---|
[331] | 466 | |
---|
| 467 | // broadcast address |
---|
[395] | 468 | uint32_t m_broadcast_boundaries; |
---|
[331] | 469 | |
---|
| 470 | ////////////////////////////////////////////////// |
---|
| 471 | // Registers controlled by the TGT_CMD fsm |
---|
| 472 | ////////////////////////////////////////////////// |
---|
| 473 | |
---|
| 474 | // Fifo between TGT_CMD fsm and READ fsm |
---|
[385] | 475 | GenericFifo<addr_t> m_cmd_read_addr_fifo; |
---|
[331] | 476 | GenericFifo<size_t> m_cmd_read_length_fifo; |
---|
| 477 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
---|
| 478 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
---|
| 479 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
---|
| 480 | |
---|
| 481 | // Fifo between TGT_CMD fsm and WRITE fsm |
---|
[385] | 482 | GenericFifo<addr_t> m_cmd_write_addr_fifo; |
---|
[331] | 483 | GenericFifo<bool> m_cmd_write_eop_fifo; |
---|
| 484 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
---|
| 485 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
---|
| 486 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
---|
| 487 | GenericFifo<data_t> m_cmd_write_data_fifo; |
---|
| 488 | GenericFifo<be_t> m_cmd_write_be_fifo; |
---|
| 489 | |
---|
| 490 | // Fifo between TGT_CMD fsm and CAS fsm |
---|
[385] | 491 | GenericFifo<addr_t> m_cmd_cas_addr_fifo; |
---|
[331] | 492 | GenericFifo<bool> m_cmd_cas_eop_fifo; |
---|
| 493 | GenericFifo<size_t> m_cmd_cas_srcid_fifo; |
---|
| 494 | GenericFifo<size_t> m_cmd_cas_trdid_fifo; |
---|
| 495 | GenericFifo<size_t> m_cmd_cas_pktid_fifo; |
---|
| 496 | GenericFifo<data_t> m_cmd_cas_wdata_fifo; |
---|
| 497 | |
---|
| 498 | // Fifo between INIT_RSP fsm and CLEANUP fsm |
---|
| 499 | GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; |
---|
| 500 | |
---|
| 501 | // Fifo between INIT_RSP fsm and MULTI_ACK fsm |
---|
| 502 | GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; |
---|
| 503 | |
---|
| 504 | sc_signal<int> r_tgt_cmd_fsm; |
---|
| 505 | |
---|
| 506 | /////////////////////////////////////////////////////// |
---|
| 507 | // Registers controlled by the READ fsm |
---|
| 508 | /////////////////////////////////////////////////////// |
---|
| 509 | |
---|
| 510 | sc_signal<int> r_read_fsm; // FSM state |
---|
| 511 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
---|
| 512 | sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy |
---|
| 513 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
---|
| 514 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
---|
| 515 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
---|
| 516 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
---|
| 517 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
---|
| 518 | sc_signal<size_t> r_read_count; // number of copies |
---|
| 519 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
---|
| 520 | sc_signal<data_t> * r_read_data; // data (one cache line) |
---|
| 521 | sc_signal<size_t> r_read_way; // associative way (in cache) |
---|
| 522 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
---|
| 523 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
---|
| 524 | sc_signal<bool> r_read_last_free; // Last free entry |
---|
[385] | 525 | sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table |
---|
[331] | 526 | |
---|
| 527 | // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 528 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
---|
| 529 | sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index |
---|
| 530 | sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 531 | |
---|
| 532 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
---|
| 533 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
---|
| 534 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 535 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 536 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 537 | sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) |
---|
| 538 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
---|
| 539 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
---|
[385] | 540 | sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table |
---|
[331] | 541 | |
---|
| 542 | /////////////////////////////////////////////////////////////// |
---|
| 543 | // Registers controlled by the WRITE fsm |
---|
| 544 | /////////////////////////////////////////////////////////////// |
---|
| 545 | |
---|
| 546 | sc_signal<int> r_write_fsm; // FSM state |
---|
| 547 | sc_signal<addr_t> r_write_address; // first word address |
---|
| 548 | sc_signal<size_t> r_write_word_index; // first word index in line |
---|
| 549 | sc_signal<size_t> r_write_word_count; // number of words in line |
---|
| 550 | sc_signal<size_t> r_write_srcid; // transaction srcid |
---|
| 551 | sc_signal<size_t> r_write_trdid; // transaction trdid |
---|
| 552 | sc_signal<size_t> r_write_pktid; // transaction pktid |
---|
| 553 | sc_signal<data_t> * r_write_data; // data (one cache line) |
---|
| 554 | sc_signal<be_t> * r_write_be; // one byte enable per word |
---|
| 555 | sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) |
---|
| 556 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
| 557 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
| 558 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
| 559 | sc_signal<size_t> r_write_copy; // first owner of the line |
---|
| 560 | sc_signal<size_t> r_write_copy_cache; // first owner of the line |
---|
| 561 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
---|
| 562 | sc_signal<size_t> r_write_count; // number of copies |
---|
| 563 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
---|
| 564 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
---|
| 565 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
---|
| 566 | sc_signal<size_t> r_write_way; // way of the line |
---|
| 567 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
| 568 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
| 569 | sc_signal<bool> r_write_sc_fail; // sc command failed |
---|
[336] | 570 | sc_signal<bool> r_write_pending_sc; // sc command pending |
---|
[331] | 571 | |
---|
| 572 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 573 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
| 574 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
| 575 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
| 576 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
| 577 | sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed |
---|
| 578 | |
---|
| 579 | // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 580 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
| 581 | sc_signal<bool> r_write_to_ixr_cmd_write; // write request |
---|
| 582 | sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index |
---|
| 583 | sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data |
---|
| 584 | sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 585 | |
---|
| 586 | // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
| 587 | sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request |
---|
| 588 | sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request |
---|
| 589 | sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index |
---|
| 590 | sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table |
---|
| 591 | sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line) |
---|
| 592 | sc_signal<be_t> * r_write_to_cc_send_be; // word enable |
---|
| 593 | sc_signal<size_t> r_write_to_cc_send_count; // number of words in line |
---|
| 594 | sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line |
---|
| 595 | GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 596 | GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 597 | |
---|
[331] | 598 | #if L1_MULTI_CACHE |
---|
| 599 | GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids |
---|
| 600 | #endif |
---|
| 601 | |
---|
| 602 | // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) |
---|
| 603 | sc_signal<bool> r_write_to_multi_ack_req; // valid request |
---|
| 604 | sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table |
---|
| 605 | |
---|
| 606 | ///////////////////////////////////////////////////////// |
---|
| 607 | // Registers controlled by MULTI_ACK fsm |
---|
| 608 | ////////////////////////////////////////////////////////// |
---|
| 609 | |
---|
| 610 | sc_signal<int> r_multi_ack_fsm; // FSM state |
---|
| 611 | sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table |
---|
| 612 | sc_signal<size_t> r_multi_ack_srcid; // pending write srcid |
---|
| 613 | sc_signal<size_t> r_multi_ack_trdid; // pending write trdid |
---|
| 614 | sc_signal<size_t> r_multi_ack_pktid; // pending write pktid |
---|
| 615 | sc_signal<addr_t> r_multi_ack_nline; // pending write nline |
---|
| 616 | |
---|
| 617 | // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) |
---|
| 618 | sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request |
---|
| 619 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 620 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 621 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 622 | |
---|
| 623 | /////////////////////////////////////////////////////// |
---|
| 624 | // Registers controlled by CLEANUP fsm |
---|
| 625 | /////////////////////////////////////////////////////// |
---|
| 626 | |
---|
| 627 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
| 628 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
| 629 | sc_signal<bool> r_cleanup_inst; // Instruction or Data ? |
---|
| 630 | sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index |
---|
| 631 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
| 632 | |
---|
| 633 | #if L1_MULTI_CACHE |
---|
| 634 | sc_signal<size_t> r_cleanup_pktid; // transaction pktid |
---|
| 635 | #endif |
---|
| 636 | |
---|
| 637 | sc_signal<copy_t> r_cleanup_copy; // first copy |
---|
| 638 | sc_signal<copy_t> r_cleanup_copy_cache; // first copy |
---|
| 639 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
---|
| 640 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
| 641 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
---|
| 642 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
---|
| 643 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
---|
| 644 | sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry |
---|
| 645 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
---|
| 646 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
---|
| 647 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
| 648 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
| 649 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
| 650 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
| 651 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
| 652 | |
---|
| 653 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response |
---|
| 654 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
| 655 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
| 656 | sc_signal<bool> r_cleanup_write_need_rsp;// needs a write rsp |
---|
| 657 | |
---|
| 658 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
| 659 | |
---|
| 660 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 661 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
| 662 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
| 663 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
| 664 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
| 665 | |
---|
| 666 | // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1) |
---|
| 667 | sc_signal<bool> r_cleanup_to_cc_send_req; // valid request |
---|
| 668 | sc_signal<size_t> r_cleanup_to_cc_send_srcid; // L1 srcid |
---|
| 669 | sc_signal<size_t> r_cleanup_to_cc_send_set_index; // L1 set index |
---|
| 670 | sc_signal<size_t> r_cleanup_to_cc_send_way_index; // L1 way index |
---|
| 671 | sc_signal<bool> r_cleanup_to_cc_send_inst; // Instruction Cleanup Ack |
---|
| 672 | |
---|
| 673 | /////////////////////////////////////////////////////// |
---|
| 674 | // Registers controlled by CAS fsm |
---|
| 675 | /////////////////////////////////////////////////////// |
---|
| 676 | |
---|
| 677 | sc_signal<int> r_cas_fsm; // FSM state |
---|
| 678 | sc_signal<data_t> r_cas_wdata; // write data word |
---|
| 679 | sc_signal<data_t> * r_cas_rdata; // read data word |
---|
| 680 | sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing |
---|
| 681 | sc_signal<size_t> r_cas_cpt; // size of command |
---|
| 682 | sc_signal<copy_t> r_cas_copy; // Srcid of the first copy |
---|
| 683 | sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy |
---|
| 684 | sc_signal<bool> r_cas_copy_inst; // Type of the first copy |
---|
| 685 | sc_signal<size_t> r_cas_count; // number of copies |
---|
| 686 | sc_signal<size_t> r_cas_ptr; // pointer to the heap |
---|
| 687 | sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap |
---|
| 688 | sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) |
---|
| 689 | sc_signal<bool> r_cas_dirty; // dirty bit (in directory) |
---|
| 690 | sc_signal<size_t> r_cas_way; // way in directory |
---|
| 691 | sc_signal<size_t> r_cas_set; // set in directory |
---|
| 692 | sc_signal<data_t> r_cas_tag; // cache line tag (in directory) |
---|
| 693 | sc_signal<size_t> r_cas_trt_index; // Transaction Table index |
---|
| 694 | sc_signal<size_t> r_cas_upt_index; // Update Table index |
---|
| 695 | sc_signal<data_t> * r_cas_data; // cache line data |
---|
| 696 | |
---|
| 697 | // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) |
---|
| 698 | sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request |
---|
| 699 | sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index |
---|
| 700 | sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 701 | sc_signal<bool> r_cas_to_ixr_cmd_write; // write request |
---|
| 702 | sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data |
---|
| 703 | |
---|
| 704 | |
---|
| 705 | // Buffer between CAS fsm and TGT_RSP fsm |
---|
| 706 | sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request |
---|
| 707 | sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word |
---|
| 708 | sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 709 | sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 710 | sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 711 | |
---|
| 712 | // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
| 713 | sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request |
---|
| 714 | sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request |
---|
| 715 | sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index |
---|
| 716 | sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table |
---|
| 717 | sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word) |
---|
| 718 | sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS |
---|
| 719 | sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word) |
---|
| 720 | sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line |
---|
| 721 | GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 722 | GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 723 | |
---|
[331] | 724 | #if L1_MULTI_CACHE |
---|
| 725 | GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids |
---|
| 726 | #endif |
---|
| 727 | |
---|
| 728 | //////////////////////////////////////////////////// |
---|
| 729 | // Registers controlled by the IXR_RSP fsm |
---|
| 730 | //////////////////////////////////////////////////// |
---|
| 731 | |
---|
| 732 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
| 733 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
| 734 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
| 735 | |
---|
| 736 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
| 737 | sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready |
---|
| 738 | |
---|
| 739 | //////////////////////////////////////////////////// |
---|
| 740 | // Registers controlled by the XRAM_RSP fsm |
---|
| 741 | //////////////////////////////////////////////////// |
---|
| 742 | |
---|
| 743 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
| 744 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
| 745 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
| 746 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
| 747 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
| 748 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
| 749 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
| 750 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
| 751 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
| 752 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
| 753 | sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy |
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| 754 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
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| 755 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
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| 756 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
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| 757 | sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data |
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| 758 | sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index |
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| 759 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
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| 760 | |
---|
| 761 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
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| 762 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
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| 763 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
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| 764 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
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| 765 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
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| 766 | sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
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| 767 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
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| 768 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response |
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| 769 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester |
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[385] | 770 | sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table |
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[331] | 771 | |
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| 772 | // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) |
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| 773 | sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request |
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| 774 | sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request |
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| 775 | sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index; |
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| 776 | sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry |
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| 777 | GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type |
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| 778 | GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids |
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[385] | 779 | |
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[331] | 780 | #if L1_MULTI_CACHE |
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| 781 | GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids |
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| 782 | #endif |
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| 783 | |
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| 784 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) |
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| 785 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
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| 786 | sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index |
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| 787 | sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data |
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| 788 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table |
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| 789 | |
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| 790 | //////////////////////////////////////////////////// |
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| 791 | // Registers controlled by the IXR_CMD fsm |
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| 792 | //////////////////////////////////////////////////// |
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| 793 | |
---|
| 794 | sc_signal<int> r_ixr_cmd_fsm; |
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| 795 | sc_signal<size_t> r_ixr_cmd_cpt; |
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| 796 | |
---|
| 797 | //////////////////////////////////////////////////// |
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| 798 | // Registers controlled by TGT_RSP fsm |
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| 799 | //////////////////////////////////////////////////// |
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| 800 | |
---|
| 801 | sc_signal<int> r_tgt_rsp_fsm; |
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| 802 | sc_signal<size_t> r_tgt_rsp_cpt; |
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[362] | 803 | sc_signal<bool> r_tgt_rsp_key_sent; |
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[331] | 804 | |
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| 805 | //////////////////////////////////////////////////// |
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| 806 | // Registers controlled by CC_SEND fsm |
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| 807 | //////////////////////////////////////////////////// |
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| 808 | |
---|
| 809 | sc_signal<int> r_cc_send_fsm; |
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| 810 | sc_signal<size_t> r_cc_send_cpt; |
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| 811 | sc_signal<bool> r_cc_send_inst; |
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| 812 | |
---|
| 813 | //////////////////////////////////////////////////// |
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| 814 | // Registers controlled by CC_RECEIVE fsm |
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| 815 | //////////////////////////////////////////////////// |
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| 816 | |
---|
| 817 | sc_signal<int> r_cc_receive_fsm; |
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| 818 | |
---|
| 819 | //////////////////////////////////////////////////// |
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| 820 | // Registers controlled by ALLOC_DIR fsm |
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| 821 | //////////////////////////////////////////////////// |
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| 822 | |
---|
| 823 | sc_signal<int> r_alloc_dir_fsm; |
---|
| 824 | sc_signal<unsigned> r_alloc_dir_reset_cpt; |
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| 825 | |
---|
| 826 | //////////////////////////////////////////////////// |
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| 827 | // Registers controlled by ALLOC_TRT fsm |
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| 828 | //////////////////////////////////////////////////// |
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| 829 | |
---|
| 830 | sc_signal<int> r_alloc_trt_fsm; |
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| 831 | |
---|
| 832 | //////////////////////////////////////////////////// |
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| 833 | // Registers controlled by ALLOC_UPT fsm |
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| 834 | //////////////////////////////////////////////////// |
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| 835 | |
---|
| 836 | sc_signal<int> r_alloc_upt_fsm; |
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| 837 | |
---|
| 838 | //////////////////////////////////////////////////// |
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| 839 | // Registers controlled by ALLOC_HEAP fsm |
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| 840 | //////////////////////////////////////////////////// |
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| 841 | |
---|
| 842 | sc_signal<int> r_alloc_heap_fsm; |
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| 843 | sc_signal<unsigned> r_alloc_heap_reset_cpt; |
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| 844 | }; // end class VciMemCache |
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| 845 | |
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| 846 | }} |
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| 847 | |
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| 848 | #endif |
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| 849 | |
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| 850 | // Local Variables: |
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| 851 | // tab-width: 2 |
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| 852 | // c-basic-offset: 2 |
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| 853 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 854 | // indent-tabs-mode: nil |
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| 855 | // End: |
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| 856 | |
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| 857 | // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 |
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| 858 | |
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