[434] | 1 | /* |
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| 2 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 3 | * |
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| 4 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 5 | * |
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| 6 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 7 | * under the terms of the GNU Lesser General Public License as published |
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| 8 | * by the Free Software Foundation; version 2.1 of the License. |
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| 9 | * |
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| 10 | * SoCLib is distributed in the hope that it will be useful, but |
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| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 13 | * Lesser General Public License for more details. |
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| 14 | * |
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| 15 | * You should have received a copy of the GNU Lesser General Public |
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| 16 | * License along with SoCLib; if not, write to the Free Software |
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| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 18 | * 02110-1301 USA |
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| 19 | * |
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| 20 | * SOCLIB_LGPL_HEADER_END |
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| 21 | * |
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| 22 | * Copyright (c) UPMC, Lip6, Asim |
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| 23 | * alain greiner |
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| 24 | * |
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| 25 | * Maintainers: alain |
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| 26 | */ |
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| 27 | #ifndef MEM_CACHE_REGS_H |
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| 28 | #define MEM_CACHE_REGS_H |
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| 29 | |
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[596] | 30 | enum SoclibMemCacheFunc |
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| 31 | { |
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| 32 | MEMC_CONFIG = 0, |
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| 33 | MEMC_INSTRM = 1, |
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[601] | 34 | MEMC_RERROR = 2, |
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[596] | 35 | |
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| 36 | MEMC_FUNC_SPAN = 0x200 |
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| 37 | }; |
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| 38 | |
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[434] | 39 | enum SoclibMemCacheConfigRegs |
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| 40 | { |
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| 41 | MEMC_LOCK, |
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| 42 | MEMC_ADDR_LO, |
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| 43 | MEMC_ADDR_HI, |
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[489] | 44 | MEMC_BUF_LENGTH, |
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| 45 | MEMC_CMD_TYPE |
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[434] | 46 | }; |
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| 47 | |
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| 48 | enum SoclibMemCacheConfigCmd |
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| 49 | { |
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| 50 | MEMC_CMD_NOP, |
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| 51 | MEMC_CMD_INVAL, |
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| 52 | MEMC_CMD_SYNC |
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| 53 | }; |
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| 54 | |
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[596] | 55 | /////////////////////////////////////////////////////////// |
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| 56 | // Decoding CONFIG interface commands // |
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| 57 | // // |
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| 58 | // VCI ADDRESS // |
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| 59 | // ================================================ // |
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| 60 | // GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 // |
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| 61 | // IDX | IDX | | (3 bits) | (7 bits) | // |
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| 62 | // ================================================ // |
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| 63 | // // |
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| 64 | // For instrumentation: FUNC_IDX = 0b001 // |
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| 65 | // // |
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| 66 | // REGS_IDX // |
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| 67 | // ============================================ // |
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| 68 | // Z | Y | X | W // |
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| 69 | // (1 bit) | (2 bits) | (3 bits) | (1 bit) // |
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| 70 | // ============================================ // |
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| 71 | // // |
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| 72 | // For configuration: FUNC_IDX = 0b000 // |
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| 73 | // // |
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| 74 | // REGS_IDX // |
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| 75 | // ============================================ // |
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| 76 | // RESERVED | X | // |
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| 77 | // (4 bits) | (3 bits) | // |
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| 78 | // ============================================ // |
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| 79 | // // |
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| 80 | // X : REGISTER INDEX // |
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| 81 | // // |
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[601] | 82 | // For WRITE MISS error signaling: FUNC = 0x010 // |
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| 83 | // // |
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| 84 | // REGS_IDX // |
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| 85 | // ============================================ // |
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| 86 | // RESERVED | X | // |
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| 87 | // (4 bits) | (3 bits) | // |
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| 88 | // ============================================ // |
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| 89 | // // |
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| 90 | // X : REGISTER INDEX // |
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| 91 | // // |
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[596] | 92 | /////////////////////////////////////////////////////////// |
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| 93 | |
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| 94 | enum SoclibMemCacheInstrRegs { |
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| 95 | /////////////////////////////////////////////////////// |
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| 96 | // DIRECT instrumentation registers // |
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| 97 | /////////////////////////////////////////////////////// |
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| 98 | |
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| 99 | // LOCAL |
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| 100 | |
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| 101 | MEMC_LOCAL_READ_LO = 0x00, |
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| 102 | MEMC_LOCAL_READ_HI = 0x01, |
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| 103 | MEMC_LOCAL_WRITE_LO = 0x02, |
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| 104 | MEMC_LOCAL_WRITE_HI = 0x03, |
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| 105 | MEMC_LOCAL_LL_LO = 0x04, |
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| 106 | MEMC_LOCAL_LL_HI = 0x05, |
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| 107 | MEMC_LOCAL_SC_LO = 0x06, |
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| 108 | MEMC_LOCAL_SC_HI = 0x07, |
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| 109 | MEMC_LOCAL_CAS_LO = 0x08, |
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| 110 | MEMC_LOCAL_CAS_HI = 0x09, |
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| 111 | |
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| 112 | // REMOTE |
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| 113 | |
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| 114 | MEMC_REMOTE_READ_LO = 0x10, |
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| 115 | MEMC_REMOTE_READ_HI = 0x11, |
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| 116 | MEMC_REMOTE_WRITE_LO = 0x12, |
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| 117 | MEMC_REMOTE_WRITE_HI = 0x13, |
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| 118 | MEMC_REMOTE_LL_LO = 0x14, |
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| 119 | MEMC_REMOTE_LL_HI = 0x15, |
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| 120 | MEMC_REMOTE_SC_LO = 0x16, |
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| 121 | MEMC_REMOTE_SC_HI = 0x17, |
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| 122 | MEMC_REMOTE_CAS_LO = 0x18, |
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| 123 | MEMC_REMOTE_CAS_HI = 0x19, |
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| 124 | |
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| 125 | // COST |
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| 126 | |
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| 127 | MEMC_COST_READ_LO = 0x20, |
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| 128 | MEMC_COST_READ_HI = 0x21, |
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| 129 | MEMC_COST_WRITE_LO = 0x22, |
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| 130 | MEMC_COST_WRITE_HI = 0x23, |
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| 131 | MEMC_COST_LL_LO = 0x24, |
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| 132 | MEMC_COST_LL_HI = 0x25, |
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| 133 | MEMC_COST_SC_LO = 0x26, |
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| 134 | MEMC_COST_SC_HI = 0x27, |
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| 135 | MEMC_COST_CAS_LO = 0x28, |
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| 136 | MEMC_COST_CAS_HI = 0x29, |
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| 137 | |
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| 138 | /////////////////////////////////////////////////////// |
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| 139 | // COHERENCE instrumentation registers // |
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| 140 | /////////////////////////////////////////////////////// |
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| 141 | |
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| 142 | // LOCAL |
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| 143 | |
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| 144 | MEMC_LOCAL_MUPDATE_LO = 0x40, |
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| 145 | MEMC_LOCAL_MUPDATE_HI = 0x41, |
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| 146 | MEMC_LOCAL_MINVAL_LO = 0x42, |
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| 147 | MEMC_LOCAL_MINVAL_HI = 0x43, |
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| 148 | MEMC_LOCAL_CLEANUP_LO = 0x44, |
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| 149 | MEMC_LOCAL_CLEANUP_HI = 0x45, |
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| 150 | |
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| 151 | // REMOTE |
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| 152 | |
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| 153 | MEMC_REMOTE_MUPDATE_LO = 0x50, |
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| 154 | MEMC_REMOTE_MUPDATE_HI = 0x51, |
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| 155 | MEMC_REMOTE_MINVAL_LO = 0x52, |
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| 156 | MEMC_REMOTE_MINVAL_HI = 0x53, |
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| 157 | MEMC_REMOTE_CLEANUP_LO = 0x54, |
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| 158 | MEMC_REMOTE_CLEANUP_HI = 0x55, |
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| 159 | |
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| 160 | // COST |
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| 161 | |
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| 162 | MEMC_COST_MUPDATE_LO = 0x60, |
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| 163 | MEMC_COST_MUPDATE_HI = 0x61, |
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| 164 | MEMC_COST_MINVAL_LO = 0x62, |
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| 165 | MEMC_COST_MINVAL_HI = 0x63, |
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| 166 | MEMC_COST_CLEANUP_LO = 0x64, |
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| 167 | MEMC_COST_CLEANUP_HI = 0x65, |
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| 168 | |
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| 169 | // TOTAL |
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| 170 | |
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| 171 | MEMC_TOTAL_MUPDATE_LO = 0x68, |
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| 172 | MEMC_TOTAL_MUPDATE_HI = 0x69, |
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| 173 | MEMC_TOTAL_MINVAL_LO = 0x6A, |
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| 174 | MEMC_TOTAL_MINVAL_HI = 0x6B, |
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| 175 | MEMC_TOTAL_BINVAL_LO = 0x6C, |
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| 176 | MEMC_TOTAL_BINVAL_HI = 0x6D, |
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| 177 | }; |
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| 178 | |
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[601] | 179 | enum SoclibMemCacheRerrorRegs |
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| 180 | { |
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| 181 | MEMC_RERROR_ADDR_LO = 0, |
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| 182 | MEMC_RERROR_ADDR_HI, |
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| 183 | MEMC_RERROR_SRCID, |
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| 184 | MEMC_RERROR_IRQ_RESET, |
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| 185 | MEMC_RERROR_IRQ_ENABLE |
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| 186 | }; |
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| 187 | |
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[596] | 188 | #define MEMC_REG(func,idx) ((func<<7)|idx) |
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| 189 | |
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[434] | 190 | #endif /* MEM_CACHE_REGS_H */ |
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| 191 | |
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| 192 | // Local Variables: |
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| 193 | // tab-width: 4 |
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| 194 | // c-basic-offset: 4 |
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| 195 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 196 | // indent-tabs-mode: nil |
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| 197 | // End: |
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| 198 | |
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| 199 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 200 | |
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