source: trunk/modules/vci_mem_cache/include/soclib/mem_cache.h@ 890

Last change on this file since 890 was 601, checked in by cfuguet, 13 years ago

Modifications in vci_mem_cache:

  • The out of segment read or write does not activate any more an assert on the memory cache. Instead, the request is sent to the XRAM and the error from the XRAM will be propagated to the processor doing the access.

The propagation of the error is done in two different ways:

  • When is a READ MISS: The error is propagated through the VCI rerror to the processor doing the read.
  • When is a WRITE MISS: The error is propagated through an IRQ which normally is connected to the local XICU.
File size: 6.2 KB
Line 
1/*
2 * SOCLIB_LGPL_HEADER_BEGIN
3 *
4 * This file is part of SoCLib, GNU LGPLv2.1.
5 *
6 * SoCLib is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU Lesser General Public License as published
8 * by the Free Software Foundation; version 2.1 of the License.
9 *
10 * SoCLib is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
14 *
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with SoCLib; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 * SOCLIB_LGPL_HEADER_END
21 *
22 * Copyright (c) UPMC, Lip6, Asim
23 * alain greiner
24 *
25 * Maintainers: alain
26 */
27#ifndef MEM_CACHE_REGS_H
28#define MEM_CACHE_REGS_H
29
30enum SoclibMemCacheFunc
31{
32 MEMC_CONFIG = 0,
33 MEMC_INSTRM = 1,
34 MEMC_RERROR = 2,
35
36 MEMC_FUNC_SPAN = 0x200
37};
38
39enum SoclibMemCacheConfigRegs
40{
41 MEMC_LOCK,
42 MEMC_ADDR_LO,
43 MEMC_ADDR_HI,
44 MEMC_BUF_LENGTH,
45 MEMC_CMD_TYPE
46};
47
48enum SoclibMemCacheConfigCmd
49{
50 MEMC_CMD_NOP,
51 MEMC_CMD_INVAL,
52 MEMC_CMD_SYNC
53};
54
55///////////////////////////////////////////////////////////
56// Decoding CONFIG interface commands //
57// //
58// VCI ADDRESS //
59// ================================================ //
60// GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 //
61// IDX | IDX | | (3 bits) | (7 bits) | //
62// ================================================ //
63// //
64// For instrumentation: FUNC_IDX = 0b001 //
65// //
66// REGS_IDX //
67// ============================================ //
68// Z | Y | X | W //
69// (1 bit) | (2 bits) | (3 bits) | (1 bit) //
70// ============================================ //
71// //
72// For configuration: FUNC_IDX = 0b000 //
73// //
74// REGS_IDX //
75// ============================================ //
76// RESERVED | X | //
77// (4 bits) | (3 bits) | //
78// ============================================ //
79// //
80// X : REGISTER INDEX //
81// //
82// For WRITE MISS error signaling: FUNC = 0x010 //
83// //
84// REGS_IDX //
85// ============================================ //
86// RESERVED | X | //
87// (4 bits) | (3 bits) | //
88// ============================================ //
89// //
90// X : REGISTER INDEX //
91// //
92///////////////////////////////////////////////////////////
93
94enum SoclibMemCacheInstrRegs {
95 ///////////////////////////////////////////////////////
96 // DIRECT instrumentation registers //
97 ///////////////////////////////////////////////////////
98
99 // LOCAL
100
101 MEMC_LOCAL_READ_LO = 0x00,
102 MEMC_LOCAL_READ_HI = 0x01,
103 MEMC_LOCAL_WRITE_LO = 0x02,
104 MEMC_LOCAL_WRITE_HI = 0x03,
105 MEMC_LOCAL_LL_LO = 0x04,
106 MEMC_LOCAL_LL_HI = 0x05,
107 MEMC_LOCAL_SC_LO = 0x06,
108 MEMC_LOCAL_SC_HI = 0x07,
109 MEMC_LOCAL_CAS_LO = 0x08,
110 MEMC_LOCAL_CAS_HI = 0x09,
111
112 // REMOTE
113
114 MEMC_REMOTE_READ_LO = 0x10,
115 MEMC_REMOTE_READ_HI = 0x11,
116 MEMC_REMOTE_WRITE_LO = 0x12,
117 MEMC_REMOTE_WRITE_HI = 0x13,
118 MEMC_REMOTE_LL_LO = 0x14,
119 MEMC_REMOTE_LL_HI = 0x15,
120 MEMC_REMOTE_SC_LO = 0x16,
121 MEMC_REMOTE_SC_HI = 0x17,
122 MEMC_REMOTE_CAS_LO = 0x18,
123 MEMC_REMOTE_CAS_HI = 0x19,
124
125 // COST
126
127 MEMC_COST_READ_LO = 0x20,
128 MEMC_COST_READ_HI = 0x21,
129 MEMC_COST_WRITE_LO = 0x22,
130 MEMC_COST_WRITE_HI = 0x23,
131 MEMC_COST_LL_LO = 0x24,
132 MEMC_COST_LL_HI = 0x25,
133 MEMC_COST_SC_LO = 0x26,
134 MEMC_COST_SC_HI = 0x27,
135 MEMC_COST_CAS_LO = 0x28,
136 MEMC_COST_CAS_HI = 0x29,
137
138 ///////////////////////////////////////////////////////
139 // COHERENCE instrumentation registers //
140 ///////////////////////////////////////////////////////
141
142 // LOCAL
143
144 MEMC_LOCAL_MUPDATE_LO = 0x40,
145 MEMC_LOCAL_MUPDATE_HI = 0x41,
146 MEMC_LOCAL_MINVAL_LO = 0x42,
147 MEMC_LOCAL_MINVAL_HI = 0x43,
148 MEMC_LOCAL_CLEANUP_LO = 0x44,
149 MEMC_LOCAL_CLEANUP_HI = 0x45,
150
151 // REMOTE
152
153 MEMC_REMOTE_MUPDATE_LO = 0x50,
154 MEMC_REMOTE_MUPDATE_HI = 0x51,
155 MEMC_REMOTE_MINVAL_LO = 0x52,
156 MEMC_REMOTE_MINVAL_HI = 0x53,
157 MEMC_REMOTE_CLEANUP_LO = 0x54,
158 MEMC_REMOTE_CLEANUP_HI = 0x55,
159
160 // COST
161
162 MEMC_COST_MUPDATE_LO = 0x60,
163 MEMC_COST_MUPDATE_HI = 0x61,
164 MEMC_COST_MINVAL_LO = 0x62,
165 MEMC_COST_MINVAL_HI = 0x63,
166 MEMC_COST_CLEANUP_LO = 0x64,
167 MEMC_COST_CLEANUP_HI = 0x65,
168
169 // TOTAL
170
171 MEMC_TOTAL_MUPDATE_LO = 0x68,
172 MEMC_TOTAL_MUPDATE_HI = 0x69,
173 MEMC_TOTAL_MINVAL_LO = 0x6A,
174 MEMC_TOTAL_MINVAL_HI = 0x6B,
175 MEMC_TOTAL_BINVAL_LO = 0x6C,
176 MEMC_TOTAL_BINVAL_HI = 0x6D,
177};
178
179enum SoclibMemCacheRerrorRegs
180{
181 MEMC_RERROR_ADDR_LO = 0,
182 MEMC_RERROR_ADDR_HI,
183 MEMC_RERROR_SRCID,
184 MEMC_RERROR_IRQ_RESET,
185 MEMC_RERROR_IRQ_ENABLE
186};
187
188#define MEMC_REG(func,idx) ((func<<7)|idx)
189
190#endif /* MEM_CACHE_REGS_H */
191
192// Local Variables:
193// tab-width: 4
194// c-basic-offset: 4
195// c-file-offsets:((innamespace . 0)(inline-open . 0))
196// indent-tabs-mode: nil
197// End:
198
199// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
200
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