[2] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_mem_cache_v4.h |
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| 3 | * Date : 26/10/2008 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Alain Greiner / Eric Guthmuller |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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| 27 | * Maintainers: alain eric.guthmuller@polytechnique.edu |
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[273] | 28 | * cesar.fuguet-tortolero@lip6.fr |
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[2] | 29 | * |
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| 30 | * Modifications done by Christophe Choichillon on the 7/04/2009: |
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| 31 | * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE |
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| 32 | * - Adding a new VCI target port for the CLEANUP network |
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| 33 | * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP |
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[273] | 34 | * |
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[2] | 35 | * Modifications to do : |
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| 36 | * - Adding new variables used by the CLEANUP FSM |
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| 37 | * |
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| 38 | */ |
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| 39 | |
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| 40 | #ifndef SOCLIB_CABA_MEM_CACHE_V4_H |
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| 41 | #define SOCLIB_CABA_MEM_CACHE_V4_H |
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| 42 | |
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| 43 | #include <inttypes.h> |
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| 44 | #include <systemc> |
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| 45 | #include <list> |
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| 46 | #include <cassert> |
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| 47 | #include "arithmetics.h" |
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| 48 | #include "alloc_elems.h" |
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| 49 | #include "caba_base_module.h" |
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| 50 | #include "vci_target.h" |
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| 51 | #include "vci_initiator.h" |
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| 52 | #include "generic_fifo.h" |
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| 53 | #include "mapping_table.h" |
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| 54 | #include "int_tab.h" |
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| 55 | #include "mem_cache_directory_v4.h" |
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| 56 | #include "xram_transaction_v4.h" |
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| 57 | #include "update_tab_v4.h" |
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| 58 | |
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[273] | 59 | #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab |
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| 60 | #define UPDATE_TAB_LINES 4 // Number of lines in the update tab |
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[2] | 61 | |
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| 62 | namespace soclib { namespace caba { |
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| 63 | using namespace sc_core; |
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| 64 | |
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| 65 | template<typename vci_param> |
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| 66 | class VciMemCacheV4 |
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| 67 | : public soclib::caba::BaseModule |
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| 68 | { |
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| 69 | typedef sc_dt::sc_uint<40> addr_t; |
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| 70 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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| 71 | typedef uint32_t data_t; |
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| 72 | typedef uint32_t tag_t; |
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| 73 | typedef uint32_t size_t; |
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| 74 | typedef uint32_t be_t; |
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| 75 | typedef uint32_t copy_t; |
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| 76 | |
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| 77 | /* States of the TGT_CMD fsm */ |
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| 78 | enum tgt_cmd_fsm_state_e{ |
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| 79 | TGT_CMD_IDLE, |
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| 80 | TGT_CMD_READ, |
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| 81 | TGT_CMD_WRITE, |
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[273] | 82 | TGT_CMD_ATOMIC |
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[2] | 83 | }; |
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| 84 | |
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| 85 | /* States of the TGT_RSP fsm */ |
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| 86 | enum tgt_rsp_fsm_state_e{ |
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| 87 | TGT_RSP_READ_IDLE, |
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| 88 | TGT_RSP_WRITE_IDLE, |
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[184] | 89 | TGT_RSP_SC_IDLE, |
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[2] | 90 | TGT_RSP_XRAM_IDLE, |
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| 91 | TGT_RSP_INIT_IDLE, |
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| 92 | TGT_RSP_CLEANUP_IDLE, |
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| 93 | TGT_RSP_READ, |
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| 94 | TGT_RSP_WRITE, |
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[184] | 95 | TGT_RSP_SC, |
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[2] | 96 | TGT_RSP_XRAM, |
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| 97 | TGT_RSP_INIT, |
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[273] | 98 | TGT_RSP_CLEANUP |
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[2] | 99 | }; |
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| 100 | |
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| 101 | /* States of the INIT_CMD fsm */ |
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| 102 | enum init_cmd_fsm_state_e{ |
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| 103 | INIT_CMD_INVAL_IDLE, |
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| 104 | INIT_CMD_INVAL_NLINE, |
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| 105 | INIT_CMD_XRAM_BRDCAST, |
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| 106 | INIT_CMD_UPDT_IDLE, |
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| 107 | INIT_CMD_WRITE_BRDCAST, |
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| 108 | INIT_CMD_UPDT_NLINE, |
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| 109 | INIT_CMD_UPDT_INDEX, |
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| 110 | INIT_CMD_UPDT_DATA, |
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| 111 | INIT_CMD_SC_UPDT_IDLE, |
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| 112 | INIT_CMD_SC_BRDCAST, |
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| 113 | INIT_CMD_SC_UPDT_NLINE, |
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| 114 | INIT_CMD_SC_UPDT_INDEX, |
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| 115 | INIT_CMD_SC_UPDT_DATA, |
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[273] | 116 | INIT_CMD_SC_UPDT_DATA_HIGH |
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[2] | 117 | }; |
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| 118 | |
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| 119 | /* States of the INIT_RSP fsm */ |
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| 120 | enum init_rsp_fsm_state_e{ |
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| 121 | INIT_RSP_IDLE, |
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| 122 | INIT_RSP_UPT_LOCK, |
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| 123 | INIT_RSP_UPT_CLEAR, |
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[273] | 124 | INIT_RSP_END |
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[2] | 125 | }; |
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| 126 | |
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| 127 | /* States of the READ fsm */ |
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| 128 | enum read_fsm_state_e{ |
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| 129 | READ_IDLE, |
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[273] | 130 | READ_DIR_REQ, |
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[2] | 131 | READ_DIR_LOCK, |
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| 132 | READ_DIR_HIT, |
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[273] | 133 | READ_HEAP_REQ, |
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[2] | 134 | READ_HEAP_LOCK, |
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| 135 | READ_HEAP_WRITE, |
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| 136 | READ_HEAP_ERASE, |
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| 137 | READ_HEAP_LAST, |
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| 138 | READ_RSP, |
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| 139 | READ_TRT_LOCK, |
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| 140 | READ_TRT_SET, |
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[273] | 141 | READ_TRT_REQ |
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[2] | 142 | }; |
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| 143 | |
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| 144 | /* States of the WRITE fsm */ |
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| 145 | enum write_fsm_state_e{ |
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| 146 | WRITE_IDLE, |
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| 147 | WRITE_NEXT, |
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[273] | 148 | WRITE_DIR_REQ, |
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[2] | 149 | WRITE_DIR_LOCK, |
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[200] | 150 | WRITE_DIR_READ, |
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[2] | 151 | WRITE_DIR_HIT, |
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| 152 | WRITE_UPT_LOCK, |
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[200] | 153 | WRITE_UPT_HEAP_LOCK, |
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[2] | 154 | WRITE_UPT_REQ, |
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[200] | 155 | WRITE_UPT_NEXT, |
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[2] | 156 | WRITE_UPT_DEC, |
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| 157 | WRITE_RSP, |
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[200] | 158 | WRITE_MISS_TRT_LOCK, |
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| 159 | WRITE_MISS_TRT_DATA, |
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| 160 | WRITE_MISS_TRT_SET, |
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| 161 | WRITE_MISS_XRAM_REQ, |
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| 162 | WRITE_BC_TRT_LOCK, |
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| 163 | WRITE_BC_UPT_LOCK, |
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| 164 | WRITE_BC_DIR_INVAL, |
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| 165 | WRITE_BC_CC_SEND, |
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| 166 | WRITE_BC_XRAM_REQ, |
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[273] | 167 | WRITE_WAIT |
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[2] | 168 | }; |
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| 169 | |
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| 170 | /* States of the IXR_RSP fsm */ |
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| 171 | enum ixr_rsp_fsm_state_e{ |
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| 172 | IXR_RSP_IDLE, |
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| 173 | IXR_RSP_ACK, |
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| 174 | IXR_RSP_TRT_ERASE, |
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[273] | 175 | IXR_RSP_TRT_READ |
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[2] | 176 | }; |
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| 177 | |
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| 178 | /* States of the XRAM_RSP fsm */ |
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| 179 | enum xram_rsp_fsm_state_e{ |
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| 180 | XRAM_RSP_IDLE, |
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| 181 | XRAM_RSP_TRT_COPY, |
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| 182 | XRAM_RSP_TRT_DIRTY, |
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| 183 | XRAM_RSP_DIR_LOCK, |
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| 184 | XRAM_RSP_DIR_UPDT, |
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| 185 | XRAM_RSP_DIR_RSP, |
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| 186 | XRAM_RSP_INVAL_LOCK, |
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| 187 | XRAM_RSP_INVAL_WAIT, |
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| 188 | XRAM_RSP_INVAL, |
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| 189 | XRAM_RSP_WRITE_DIRTY, |
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[273] | 190 | XRAM_RSP_HEAP_REQ, |
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[2] | 191 | XRAM_RSP_HEAP_ERASE, |
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| 192 | XRAM_RSP_HEAP_LAST, |
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[138] | 193 | XRAM_RSP_ERROR_ERASE, |
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[273] | 194 | XRAM_RSP_ERROR_RSP |
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[2] | 195 | }; |
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| 196 | |
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| 197 | /* States of the IXR_CMD fsm */ |
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| 198 | enum ixr_cmd_fsm_state_e{ |
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| 199 | IXR_CMD_READ_IDLE, |
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| 200 | IXR_CMD_WRITE_IDLE, |
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[184] | 201 | IXR_CMD_SC_IDLE, |
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[2] | 202 | IXR_CMD_XRAM_IDLE, |
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| 203 | IXR_CMD_READ_NLINE, |
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| 204 | IXR_CMD_WRITE_NLINE, |
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[184] | 205 | IXR_CMD_SC_NLINE, |
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[273] | 206 | IXR_CMD_XRAM_DATA |
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[2] | 207 | }; |
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| 208 | |
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[184] | 209 | /* States of the SC fsm */ |
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| 210 | enum sc_fsm_state_e{ |
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| 211 | SC_IDLE, |
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[273] | 212 | SC_DIR_REQ, |
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[2] | 213 | SC_DIR_LOCK, |
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| 214 | SC_DIR_HIT_READ, |
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| 215 | SC_DIR_HIT_WRITE, |
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| 216 | SC_UPT_LOCK, |
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[200] | 217 | SC_UPT_HEAP_LOCK, |
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[2] | 218 | SC_UPT_REQ, |
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[184] | 219 | SC_UPT_NEXT, |
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[200] | 220 | SC_BC_TRT_LOCK, |
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| 221 | SC_BC_UPT_LOCK, |
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| 222 | SC_BC_DIR_INVAL, |
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| 223 | SC_BC_CC_SEND, |
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| 224 | SC_BC_XRAM_REQ, |
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[184] | 225 | SC_RSP_FAIL, |
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| 226 | SC_RSP_SUCCESS, |
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[200] | 227 | SC_MISS_TRT_LOCK, |
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| 228 | SC_MISS_TRT_SET, |
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| 229 | SC_MISS_XRAM_REQ, |
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[273] | 230 | SC_WAIT |
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[2] | 231 | }; |
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| 232 | |
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| 233 | /* States of the CLEANUP fsm */ |
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| 234 | enum cleanup_fsm_state_e{ |
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| 235 | CLEANUP_IDLE, |
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[273] | 236 | CLEANUP_DIR_REQ, |
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[2] | 237 | CLEANUP_DIR_LOCK, |
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| 238 | CLEANUP_DIR_WRITE, |
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[273] | 239 | CLEANUP_HEAP_REQ, |
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[2] | 240 | CLEANUP_HEAP_LOCK, |
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| 241 | CLEANUP_HEAP_SEARCH, |
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| 242 | CLEANUP_HEAP_CLEAN, |
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| 243 | CLEANUP_HEAP_FREE, |
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| 244 | CLEANUP_UPT_LOCK, |
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| 245 | CLEANUP_UPT_WRITE, |
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| 246 | CLEANUP_WRITE_RSP, |
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[273] | 247 | CLEANUP_RSP |
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[2] | 248 | }; |
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| 249 | |
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| 250 | /* States of the ALLOC_DIR fsm */ |
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| 251 | enum alloc_dir_fsm_state_e{ |
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[273] | 252 | ALLOC_DIR_RESET, |
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[2] | 253 | ALLOC_DIR_READ, |
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| 254 | ALLOC_DIR_WRITE, |
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[184] | 255 | ALLOC_DIR_SC, |
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[2] | 256 | ALLOC_DIR_CLEANUP, |
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[273] | 257 | ALLOC_DIR_XRAM_RSP |
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[2] | 258 | }; |
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| 259 | |
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| 260 | /* States of the ALLOC_TRT fsm */ |
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| 261 | enum alloc_trt_fsm_state_e{ |
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| 262 | ALLOC_TRT_READ, |
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| 263 | ALLOC_TRT_WRITE, |
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[184] | 264 | ALLOC_TRT_SC, |
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[2] | 265 | ALLOC_TRT_XRAM_RSP, |
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[273] | 266 | ALLOC_TRT_IXR_RSP |
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[2] | 267 | }; |
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| 268 | |
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| 269 | /* States of the ALLOC_UPT fsm */ |
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| 270 | enum alloc_upt_fsm_state_e{ |
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| 271 | ALLOC_UPT_WRITE, |
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| 272 | ALLOC_UPT_XRAM_RSP, |
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| 273 | ALLOC_UPT_INIT_RSP, |
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| 274 | ALLOC_UPT_CLEANUP, |
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[273] | 275 | ALLOC_UPT_SC |
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[2] | 276 | }; |
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| 277 | |
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| 278 | /* States of the ALLOC_HEAP fsm */ |
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| 279 | enum alloc_heap_fsm_state_e{ |
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[273] | 280 | ALLOC_HEAP_RESET, |
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[2] | 281 | ALLOC_HEAP_READ, |
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| 282 | ALLOC_HEAP_WRITE, |
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[184] | 283 | ALLOC_HEAP_SC, |
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[2] | 284 | ALLOC_HEAP_CLEANUP, |
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[273] | 285 | ALLOC_HEAP_XRAM_RSP |
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[2] | 286 | }; |
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| 287 | |
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[184] | 288 | // debug variables (for each FSM) |
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| 289 | size_t m_debug_start_cycle; |
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| 290 | bool m_debug_ok; |
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| 291 | bool m_debug_global; |
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| 292 | bool m_debug_tgt_cmd_fsm; |
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| 293 | bool m_debug_tgt_rsp_fsm; |
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| 294 | bool m_debug_init_cmd_fsm; |
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| 295 | bool m_debug_init_rsp_fsm; |
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| 296 | bool m_debug_read_fsm; |
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| 297 | bool m_debug_write_fsm; |
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| 298 | bool m_debug_sc_fsm; |
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| 299 | bool m_debug_cleanup_fsm; |
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| 300 | bool m_debug_ixr_cmd_fsm; |
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| 301 | bool m_debug_ixr_rsp_fsm; |
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| 302 | bool m_debug_xram_rsp_fsm; |
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| 303 | bool m_debug_previous_hit; |
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| 304 | size_t m_debug_previous_count; |
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| 305 | |
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[215] | 306 | bool m_monitor_ok; |
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| 307 | vci_addr_t m_monitor_base; |
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| 308 | vci_addr_t m_monitor_length; |
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| 309 | |
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[184] | 310 | // instrumentation counters |
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[273] | 311 | uint32_t m_cpt_cycles; // Counter of cycles |
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| 312 | uint32_t m_cpt_read; // Number of READ transactions |
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| 313 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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| 314 | uint32_t m_cpt_write; // Number of WRITE transactions |
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| 315 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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| 316 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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| 317 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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| 318 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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| 319 | uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt |
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| 320 | uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt |
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| 321 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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| 322 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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| 323 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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| 324 | uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL |
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| 325 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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| 326 | uint32_t m_cpt_ll; // Number of LL transactions |
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| 327 | uint32_t m_cpt_sc; // Number of SC transactions |
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[2] | 328 | |
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[184] | 329 | size_t m_prev_count; |
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| 330 | |
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[2] | 331 | protected: |
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| 332 | |
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| 333 | SC_HAS_PROCESS(VciMemCacheV4); |
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| 334 | |
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| 335 | public: |
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[273] | 336 | sc_in<bool> p_clk; |
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| 337 | sc_in<bool> p_resetn; |
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| 338 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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| 339 | soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup; |
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| 340 | soclib::caba::VciInitiator<vci_param> p_vci_ini; |
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| 341 | soclib::caba::VciInitiator<vci_param> p_vci_ixr; |
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[2] | 342 | |
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| 343 | VciMemCacheV4( |
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[273] | 344 | sc_module_name name, // Instance Name |
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[184] | 345 | const soclib::common::MappingTable &mtp, // Mapping table for primary requets |
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| 346 | const soclib::common::MappingTable &mtc, // Mapping table for coherence requets |
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| 347 | const soclib::common::MappingTable &mtx, // Mapping table for XRAM |
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| 348 | const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) |
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| 349 | const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) |
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| 350 | const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) |
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| 351 | const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup |
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[273] | 352 | size_t nways, // Number of ways per set |
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[184] | 353 | size_t nsets, // Number of sets |
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| 354 | size_t nwords, // Number of words per line |
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| 355 | size_t heap_size=1024, // Size of the heap |
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| 356 | size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT |
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| 357 | size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT |
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[273] | 358 | size_t debug_start_cycle=0, |
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[184] | 359 | bool debug_ok=false); |
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[2] | 360 | |
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| 361 | ~VciMemCacheV4(); |
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| 362 | |
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| 363 | void print_stats(); |
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[116] | 364 | void print_trace(); |
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[215] | 365 | void copies_monitor(vci_addr_t addr); |
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| 366 | void start_monitor(vci_addr_t addr, vci_addr_t length); |
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| 367 | void stop_monitor(); |
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[116] | 368 | |
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[2] | 369 | private: |
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| 370 | |
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[215] | 371 | void transition(); |
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| 372 | void genMoore(); |
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[222] | 373 | void check_monitor( const char *buf, vci_addr_t addr, data_t data); |
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[215] | 374 | |
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[2] | 375 | // Component attributes |
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[273] | 376 | std::list<soclib::common::Segment> m_seglist; // memory cached into the cache |
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| 377 | std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache |
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[2] | 378 | |
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[273] | 379 | const size_t m_initiators; // Number of initiators |
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| 380 | const size_t m_heap_size; // Size of the heap |
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| 381 | const size_t m_ways; // Number of ways in a set |
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| 382 | const size_t m_sets; // Number of cache sets |
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| 383 | const size_t m_words; // Number of words in a line |
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| 384 | const size_t m_srcid_ixr; // Srcid for requests to XRAM |
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| 385 | const size_t m_srcid_ini; // Srcid for requests to processors |
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[2] | 386 | |
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[273] | 387 | uint32_t m_transaction_tab_lines; |
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| 388 | TransactionTab m_transaction_tab; // xram transaction table |
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| 389 | uint32_t m_update_tab_lines; |
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| 390 | UpdateTab m_update_tab; // pending update & invalidate |
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| 391 | CacheDirectory m_cache_directory; // data cache directory |
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| 392 | HeapDirectory m_heap; // heap for copies |
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| 393 | |
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| 394 | data_t *** m_cache_data; // data array[set][way][word] |
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| 395 | |
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[2] | 396 | // adress masks |
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[273] | 397 | const soclib::common::AddressMaskingTable<vci_addr_t> m_x; |
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| 398 | const soclib::common::AddressMaskingTable<vci_addr_t> m_y; |
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| 399 | const soclib::common::AddressMaskingTable<vci_addr_t> m_z; |
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| 400 | const soclib::common::AddressMaskingTable<vci_addr_t> m_nline; |
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[2] | 401 | |
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[82] | 402 | // broadcast address |
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[273] | 403 | vci_addr_t m_broadcast_address; |
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[82] | 404 | |
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[2] | 405 | ////////////////////////////////////////////////// |
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| 406 | // Others registers |
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| 407 | ////////////////////////////////////////////////// |
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[273] | 408 | sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line |
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| 409 | sc_signal<size_t> xxx_count; |
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[2] | 410 | |
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| 411 | ////////////////////////////////////////////////// |
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| 412 | // Registers controlled by the TGT_CMD fsm |
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| 413 | ////////////////////////////////////////////////// |
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| 414 | |
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| 415 | // Fifo between TGT_CMD fsm and READ fsm |
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| 416 | GenericFifo<uint64_t> m_cmd_read_addr_fifo; |
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| 417 | GenericFifo<size_t> m_cmd_read_length_fifo; |
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| 418 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
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| 419 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
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| 420 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
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| 421 | |
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[273] | 422 | // Fifo between TGT_CMD fsm and WRITE fsm |
---|
[2] | 423 | GenericFifo<uint64_t> m_cmd_write_addr_fifo; |
---|
| 424 | GenericFifo<bool> m_cmd_write_eop_fifo; |
---|
| 425 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
---|
| 426 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
---|
| 427 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
---|
| 428 | GenericFifo<data_t> m_cmd_write_data_fifo; |
---|
[273] | 429 | GenericFifo<be_t> m_cmd_write_be_fifo; |
---|
[2] | 430 | |
---|
[184] | 431 | // Fifo between TGT_CMD fsm and SC fsm |
---|
| 432 | GenericFifo<uint64_t> m_cmd_sc_addr_fifo; |
---|
| 433 | GenericFifo<bool> m_cmd_sc_eop_fifo; |
---|
| 434 | GenericFifo<size_t> m_cmd_sc_srcid_fifo; |
---|
| 435 | GenericFifo<size_t> m_cmd_sc_trdid_fifo; |
---|
| 436 | GenericFifo<size_t> m_cmd_sc_pktid_fifo; |
---|
| 437 | GenericFifo<data_t> m_cmd_sc_wdata_fifo; |
---|
[2] | 438 | |
---|
| 439 | sc_signal<int> r_tgt_cmd_fsm; |
---|
| 440 | |
---|
[245] | 441 | size_t m_nseg; |
---|
| 442 | size_t m_ncseg; |
---|
[2] | 443 | soclib::common::Segment **m_seg; |
---|
| 444 | soclib::common::Segment **m_cseg; |
---|
| 445 | /////////////////////////////////////////////////////// |
---|
| 446 | // Registers controlled by the READ fsm |
---|
| 447 | /////////////////////////////////////////////////////// |
---|
| 448 | |
---|
[273] | 449 | sc_signal<int> r_read_fsm; // FSM state |
---|
| 450 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
---|
| 451 | sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy |
---|
| 452 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
---|
| 453 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
---|
| 454 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
---|
| 455 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
---|
| 456 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
---|
| 457 | sc_signal<size_t> r_read_count; // number of copies |
---|
| 458 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
---|
| 459 | sc_signal<data_t> * r_read_data; // data (one cache line) |
---|
| 460 | sc_signal<size_t> r_read_way; // associative way (in cache) |
---|
| 461 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
---|
| 462 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
---|
| 463 | sc_signal<bool> r_read_last_free; // Last free entry |
---|
[2] | 464 | |
---|
[273] | 465 | // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 466 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
---|
| 467 | sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index |
---|
| 468 | sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table |
---|
[2] | 469 | |
---|
| 470 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
---|
[273] | 471 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
---|
| 472 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 473 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 474 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 475 | sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) |
---|
| 476 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
---|
| 477 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
---|
[2] | 478 | |
---|
| 479 | /////////////////////////////////////////////////////////////// |
---|
| 480 | // Registers controlled by the WRITE fsm |
---|
| 481 | /////////////////////////////////////////////////////////////// |
---|
| 482 | |
---|
[273] | 483 | sc_signal<int> r_write_fsm; // FSM state |
---|
| 484 | sc_signal<addr_t> r_write_address; // first word address |
---|
| 485 | sc_signal<size_t> r_write_word_index; // first word index in line |
---|
| 486 | sc_signal<size_t> r_write_word_count; // number of words in line |
---|
| 487 | sc_signal<size_t> r_write_srcid; // transaction srcid |
---|
| 488 | sc_signal<size_t> r_write_trdid; // transaction trdid |
---|
| 489 | sc_signal<size_t> r_write_pktid; // transaction pktid |
---|
| 490 | sc_signal<data_t> * r_write_data; // data (one cache line) |
---|
| 491 | sc_signal<be_t> * r_write_be; // one byte enable per word |
---|
| 492 | sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) |
---|
| 493 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
| 494 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
| 495 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
| 496 | sc_signal<size_t> r_write_copy; // first owner of the line |
---|
| 497 | sc_signal<size_t> r_write_copy_cache; // first owner of the line |
---|
| 498 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
---|
| 499 | sc_signal<size_t> r_write_count; // number of copies |
---|
| 500 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
---|
| 501 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
---|
| 502 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
---|
| 503 | sc_signal<size_t> r_write_way; // way of the line |
---|
| 504 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
| 505 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
[2] | 506 | |
---|
| 507 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
[273] | 508 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
| 509 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
| 510 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
| 511 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
[2] | 512 | |
---|
[273] | 513 | // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 514 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
| 515 | sc_signal<bool> r_write_to_ixr_cmd_write; // write request |
---|
| 516 | sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index |
---|
| 517 | sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data |
---|
| 518 | sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table |
---|
[2] | 519 | |
---|
| 520 | // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches) |
---|
[273] | 521 | sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request |
---|
| 522 | sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request |
---|
| 523 | sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index |
---|
| 524 | sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table |
---|
| 525 | sc_signal<data_t> * r_write_to_init_cmd_data; // data (one cache line) |
---|
| 526 | sc_signal<be_t> * r_write_to_init_cmd_be; // word enable |
---|
| 527 | sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line |
---|
| 528 | sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line |
---|
| 529 | GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type |
---|
| 530 | GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids |
---|
| 531 | GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids |
---|
[2] | 532 | |
---|
| 533 | // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry) |
---|
[273] | 534 | sc_signal<bool> r_write_to_init_rsp_req; // valid request |
---|
| 535 | sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table |
---|
[2] | 536 | |
---|
| 537 | ///////////////////////////////////////////////////////// |
---|
| 538 | // Registers controlled by INIT_RSP fsm |
---|
| 539 | ////////////////////////////////////////////////////////// |
---|
| 540 | |
---|
[273] | 541 | sc_signal<int> r_init_rsp_fsm; // FSM state |
---|
| 542 | sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table |
---|
| 543 | sc_signal<size_t> r_init_rsp_srcid; // pending write srcid |
---|
| 544 | sc_signal<size_t> r_init_rsp_trdid; // pending write trdid |
---|
| 545 | sc_signal<size_t> r_init_rsp_pktid; // pending write pktid |
---|
| 546 | sc_signal<addr_t> r_init_rsp_nline; // pending write nline |
---|
[2] | 547 | |
---|
| 548 | // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction) |
---|
[273] | 549 | sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request |
---|
| 550 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 551 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 552 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
[2] | 553 | |
---|
| 554 | /////////////////////////////////////////////////////// |
---|
| 555 | // Registers controlled by CLEANUP fsm |
---|
| 556 | /////////////////////////////////////////////////////// |
---|
| 557 | |
---|
[273] | 558 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
| 559 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
| 560 | sc_signal<size_t> r_cleanup_trdid; // transaction trdid |
---|
| 561 | sc_signal<size_t> r_cleanup_pktid; // transaction pktid |
---|
| 562 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
[2] | 563 | |
---|
[273] | 564 | sc_signal<copy_t> r_cleanup_copy; // first copy |
---|
| 565 | sc_signal<copy_t> r_cleanup_copy_cache; // first copy |
---|
| 566 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
---|
| 567 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
| 568 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
---|
| 569 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
---|
| 570 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
---|
| 571 | sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry |
---|
| 572 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
---|
| 573 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
---|
| 574 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
| 575 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
| 576 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
| 577 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
| 578 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
[2] | 579 | |
---|
[273] | 580 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response |
---|
| 581 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
| 582 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
| 583 | sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp |
---|
[2] | 584 | |
---|
[273] | 585 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
[2] | 586 | |
---|
| 587 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
[273] | 588 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
| 589 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
| 590 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
| 591 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
[2] | 592 | |
---|
| 593 | /////////////////////////////////////////////////////// |
---|
[184] | 594 | // Registers controlled by SC fsm |
---|
[2] | 595 | /////////////////////////////////////////////////////// |
---|
| 596 | |
---|
[273] | 597 | sc_signal<int> r_sc_fsm; // FSM state |
---|
| 598 | sc_signal<data_t> r_sc_wdata; // write data word |
---|
| 599 | sc_signal<data_t> * r_sc_rdata; // read data word |
---|
| 600 | sc_signal<uint32_t> r_sc_lfsr; // lfsr for random introducing |
---|
| 601 | sc_signal<size_t> r_sc_cpt; // size of command |
---|
| 602 | sc_signal<copy_t> r_sc_copy; // Srcid of the first copy |
---|
| 603 | sc_signal<copy_t> r_sc_copy_cache; // Srcid of the first copy |
---|
| 604 | sc_signal<bool> r_sc_copy_inst; // Type of the first copy |
---|
| 605 | sc_signal<size_t> r_sc_count; // number of copies |
---|
| 606 | sc_signal<size_t> r_sc_ptr; // pointer to the heap |
---|
| 607 | sc_signal<size_t> r_sc_next_ptr; // next pointer to the heap |
---|
| 608 | sc_signal<bool> r_sc_is_cnt; // is_cnt bit (in directory) |
---|
| 609 | sc_signal<bool> r_sc_dirty; // dirty bit (in directory) |
---|
| 610 | sc_signal<size_t> r_sc_way; // way in directory |
---|
| 611 | sc_signal<size_t> r_sc_set; // set in directory |
---|
| 612 | sc_signal<data_t> r_sc_tag; // cache line tag (in directory) |
---|
| 613 | sc_signal<size_t> r_sc_trt_index; // Transaction Table index |
---|
| 614 | sc_signal<size_t> r_sc_upt_index; // Update Table index |
---|
[2] | 615 | |
---|
[273] | 616 | // Buffer between SC fsm and INIT_CMD fsm (XRAM read) |
---|
| 617 | sc_signal<bool> r_sc_to_ixr_cmd_req; // valid request |
---|
| 618 | sc_signal<addr_t> r_sc_to_ixr_cmd_nline; // cache line index |
---|
| 619 | sc_signal<size_t> r_sc_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 620 | sc_signal<bool> r_sc_to_ixr_cmd_write; // write request |
---|
| 621 | sc_signal<data_t> * r_sc_to_ixr_cmd_data; // cache line data |
---|
[2] | 622 | |
---|
| 623 | |
---|
[184] | 624 | // Buffer between SC fsm and TGT_RSP fsm |
---|
[273] | 625 | sc_signal<bool> r_sc_to_tgt_rsp_req; // valid request |
---|
| 626 | sc_signal<data_t> r_sc_to_tgt_rsp_data; // read data word |
---|
| 627 | sc_signal<size_t> r_sc_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 628 | sc_signal<size_t> r_sc_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 629 | sc_signal<size_t> r_sc_to_tgt_rsp_pktid; // Transaction pktid |
---|
[2] | 630 | |
---|
[184] | 631 | // Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches) |
---|
[273] | 632 | sc_signal<bool> r_sc_to_init_cmd_multi_req; // valid request |
---|
| 633 | sc_signal<bool> r_sc_to_init_cmd_brdcast_req; // brdcast request |
---|
| 634 | sc_signal<addr_t> r_sc_to_init_cmd_nline; // cache line index |
---|
| 635 | sc_signal<size_t> r_sc_to_init_cmd_trdid; // index in Update Table |
---|
| 636 | sc_signal<data_t> r_sc_to_init_cmd_wdata; // data (one word) |
---|
| 637 | sc_signal<bool> r_sc_to_init_cmd_is_long; // it is a 64 bits SC |
---|
| 638 | sc_signal<data_t> r_sc_to_init_cmd_wdata_high; // data high (one word) |
---|
| 639 | sc_signal<size_t> r_sc_to_init_cmd_index; // index of the word in line |
---|
| 640 | GenericFifo<bool> m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type |
---|
| 641 | GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo; // fifo for srcids |
---|
| 642 | GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids |
---|
[2] | 643 | |
---|
[184] | 644 | // Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry) |
---|
[273] | 645 | sc_signal<bool> r_sc_to_init_rsp_req; // valid request |
---|
| 646 | sc_signal<size_t> r_sc_to_init_rsp_upt_index; // index in update table |
---|
[2] | 647 | |
---|
| 648 | //////////////////////////////////////////////////// |
---|
| 649 | // Registers controlled by the IXR_RSP fsm |
---|
| 650 | //////////////////////////////////////////////////// |
---|
| 651 | |
---|
[273] | 652 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
| 653 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
| 654 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
[2] | 655 | |
---|
| 656 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
[273] | 657 | sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready |
---|
[2] | 658 | |
---|
| 659 | //////////////////////////////////////////////////// |
---|
| 660 | // Registers controlled by the XRAM_RSP fsm |
---|
| 661 | //////////////////////////////////////////////////// |
---|
| 662 | |
---|
[273] | 663 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
| 664 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
| 665 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
| 666 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
| 667 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
| 668 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
| 669 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
| 670 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
| 671 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
| 672 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
| 673 | sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy |
---|
| 674 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
---|
| 675 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
| 676 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
---|
| 677 | sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data |
---|
| 678 | sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index |
---|
| 679 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
---|
[2] | 680 | |
---|
| 681 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
[273] | 682 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
| 683 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 684 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 685 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 686 | sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
| 687 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
| 688 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response |
---|
| 689 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester |
---|
[2] | 690 | |
---|
[273] | 691 | // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) |
---|
| 692 | sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request |
---|
| 693 | sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request |
---|
| 694 | sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index; |
---|
| 695 | sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry |
---|
| 696 | GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type |
---|
| 697 | GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids |
---|
| 698 | GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids |
---|
[2] | 699 | |
---|
| 700 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) |
---|
[273] | 701 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
---|
| 702 | sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index |
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| 703 | sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data |
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| 704 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table |
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[2] | 705 | |
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| 706 | //////////////////////////////////////////////////// |
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| 707 | // Registers controlled by the IXR_CMD fsm |
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| 708 | //////////////////////////////////////////////////// |
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| 709 | |
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[273] | 710 | sc_signal<int> r_ixr_cmd_fsm; |
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| 711 | sc_signal<size_t> r_ixr_cmd_cpt; |
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[2] | 712 | |
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| 713 | //////////////////////////////////////////////////// |
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| 714 | // Registers controlled by TGT_RSP fsm |
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| 715 | //////////////////////////////////////////////////// |
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| 716 | |
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[273] | 717 | sc_signal<int> r_tgt_rsp_fsm; |
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| 718 | sc_signal<size_t> r_tgt_rsp_cpt; |
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[2] | 719 | |
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| 720 | //////////////////////////////////////////////////// |
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| 721 | // Registers controlled by INIT_CMD fsm |
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| 722 | //////////////////////////////////////////////////// |
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| 723 | |
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[273] | 724 | sc_signal<int> r_init_cmd_fsm; |
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[2] | 725 | sc_signal<size_t> r_init_cmd_cpt; |
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| 726 | sc_signal<bool> r_init_cmd_inst; |
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| 727 | |
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| 728 | //////////////////////////////////////////////////// |
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| 729 | // Registers controlled by ALLOC_DIR fsm |
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| 730 | //////////////////////////////////////////////////// |
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| 731 | |
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[273] | 732 | sc_signal<int> r_alloc_dir_fsm; |
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| 733 | sc_signal<unsigned> r_alloc_dir_reset_cpt; |
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[2] | 734 | |
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| 735 | //////////////////////////////////////////////////// |
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| 736 | // Registers controlled by ALLOC_TRT fsm |
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| 737 | //////////////////////////////////////////////////// |
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| 738 | |
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[273] | 739 | sc_signal<int> r_alloc_trt_fsm; |
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[2] | 740 | |
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| 741 | //////////////////////////////////////////////////// |
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| 742 | // Registers controlled by ALLOC_UPT fsm |
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| 743 | //////////////////////////////////////////////////// |
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| 744 | |
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[273] | 745 | sc_signal<int> r_alloc_upt_fsm; |
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[2] | 746 | |
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| 747 | //////////////////////////////////////////////////// |
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| 748 | // Registers controlled by ALLOC_HEAP fsm |
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| 749 | //////////////////////////////////////////////////// |
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| 750 | |
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[273] | 751 | sc_signal<int> r_alloc_heap_fsm; |
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| 752 | sc_signal<unsigned> r_alloc_heap_reset_cpt; |
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[2] | 753 | }; // end class VciMemCacheV4 |
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| 754 | |
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| 755 | }} |
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| 756 | |
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| 757 | #endif |
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| 758 | |
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| 759 | // Local Variables: |
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[141] | 760 | // tab-width: 2 |
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| 761 | // c-basic-offset: 2 |
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[2] | 762 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 763 | // indent-tabs-mode: nil |
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| 764 | // End: |
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| 765 | |
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[273] | 766 | // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 |
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[2] | 767 | |
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