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source: trunk/platforms/tsar_generic_iob/arch.py @ 964

Last change on this file since 964 was 959, checked in by alain, 10 years ago
Fix a bug in platform tsar_generic_iob to support more than 4 processors per cluster. The hard_config.h file format has also been enriched.
Property svn:executable set to ``*
File size: 18.2 KB

Rev	Line
[938]	1	#!/usr/bin/env python
[707]	2
[802]	3	from math import log, ceil
[707]	4	from mapping import *
	5
[938]	6	##################################################################################
[714]	7	# file : arch.py (for the tsar_generic_iob architecture)
[707]	8	# date : may 2014
	9	# author : Alain Greiner
[938]	10	##################################################################################
[802]	11	# This file contains a mapping generator for the "tsar_generic_iob" platform.
[707]	12	# This includes both the hardware architecture (clusters, processors, peripherals,
[938]	13	# physical space segmentation) and the mapping of all boot and kernel objects
	14	# (global vsegs).
[714]	15	#
[938]	16	# This platform includes 6 external peripherals, accessible through an IOB
	17	# components located in cluster [0,0] or in cluster [x_size-1, y_size-1].
	18	# Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA, PIC.
	19	#
	20	# All clusters contain (nb_procs) processors, one L2 cache, one XCU, and
	21	# one DMA controller.
	22	#
[714]	23	# The "constructor" parameters are:
	24	# - x_size : number of clusters in a row
	25	# - y_size : number of clusters in a column
	26	# - nb_procs : number of processors per cluster
[874]	27	# - nb_ttys : number of TTY channels
[817]	28	# - fbf_width : frame_buffer width = frame_buffer heigth
[714]	29	#
[938]	30	# The other hardware parameters are:
[714]	31	# - nb_nics : number of NIC channels
[938]	32	# - nb_cmas : number of CMA channels
[714]	33	# - x_io : cluster_io x coordinate
	34	# - y_io : cluster_io y coordinate
	35	# - x_width : number of bits for x coordinate
	36	# - y_width : number of bits for y coordinate
	37	# - paddr_width : number of bits for physical address
	38	# - irq_per_proc : number of input IRQs per processor
	39	# - use_ramdisk : use a ramdisk when True
[817]	40	# - vseg_increment : address increment for replicated peripherals
	41	#
[938]	42	# Regarding the boot and kernel vsegs mapping :
	43	# - We use one big physical page (2 Mbytes) for the preloader and the four
	44	# boot vsegs, all allocated in cluster[0,0].
	45	# - We use one big page per cluster for the replicated kernel code vsegs.
	46	# - We use one big page in cluster[0][0] for the kernel data vseg.
	47	# - We use one big page per cluster for the distributed kernel heap vsegs.
	48	# - We use one big page per cluster for the distributed ptab vsegs.
	49	# - We use small physical pages (4 Kbytes) per cluster for the schedulers.
	50	# - We use one big page for each external peripheral in IO cluster,
	51	# - We use one small page per cluster for each internal peripheral.
	52	##################################################################################
[707]	53
[714]	54	########################
	55	def arch( x_size = 2,
	56	y_size = 2,
[817]	57	nb_procs = 2,
[874]	58	nb_ttys = 1,
[817]	59	fbf_width = 128 ):
[714]	60
	61	### define architecture constants
	62
[913]	63	nb_nics = 1
	64	nb_cmas = 2
[817]	65	x_io = 0
	66	y_io = 0
	67	x_width = 4
	68	y_width = 4
	69	p_width = 4
	70	paddr_width = 40
	71	irq_per_proc = 4
	72	use_ramdisk = False
	73	peri_increment = 0x10000 # distributed peripherals vbase address increment
[802]	74
[707]	75	### parameters checking
[714]	76
[802]	77	assert( nb_procs <= (1 << p_width) )
[707]	78
[802]	79	assert( (x_size == 1) or (x_size == 2) or (x_size == 4)
[764]	80	or (x_size == 8) or (x_size == 16) )
[707]	81
[802]	82	assert( (y_size == 1) or (y_size == 2) or (y_size == 4)
[707]	83	or (y_size == 8) or (y_size == 16) )
	84
[943]	85	assert( (nb_ttys >= 1) and (nb_ttys <= 8) )
[707]	86
	87	assert( ((x_io == 0) and (y_io == 0)) or
	88	((x_io == x_size-1) and (y_io == y_size-1)) )
	89
[938]	90	### define type and name
[802]	91
[938]	92	platform_type = 'tsar_iob'
	93	platform_name = '%s_%d_%d_%d' % ( platform_type, x_size, y_size , nb_procs )
[707]	94
[938]	95	### define physical segments replicated in all clusters
	96
[707]	97	ram_base = 0x0000000000
[913]	98	ram_size = 0x1000000 # 16 Mbytes
[707]	99
[802]	100	xcu_base = 0x00B0000000
	101	xcu_size = 0x1000 # 4 Kbytes
[707]	102
	103	dma_base = 0x00B1000000
[817]	104	dma_size = 0x1000 # 4 Kbytes
[707]	105
[802]	106	mmc_base = 0x00B2000000
[714]	107	mmc_size = 0x1000 # 4 Kbytes
[707]	108
[817]	109	### define physical segments for external peripherals
	110	## These segments are only defined in cluster_io
	111
[945]	112	bdv_base = 0x00B3000000
[714]	113	bdv_size = 0x1000 # 4kbytes
[707]	114
[945]	115	tty_base = 0x00B4000000
[714]	116	tty_size = 0x4000 # 16 Kbytes
[707]	117
[945]	118	nic_base = 0x00B5000000
[714]	119	nic_size = 0x80000 # 512 kbytes
[707]	120
[945]	121	cma_base = 0x00B6000000
[714]	122	cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics
[707]	123
[945]	124	fbf_base = 0x00B7000000
[874]	125	fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes
[707]	126
[945]	127	pic_base = 0x00B8000000
[714]	128	pic_size = 0x1000 # 4 Kbytes
[707]	129
[945]	130	iob_base = 0x00BE000000
[817]	131	iob_size = 0x1000 # 4 bytes
[707]	132
[945]	133	rom_base = 0x00BFC00000
[714]	134	rom_size = 0x4000 # 16 Kbytes
[707]	135
[754]	136	### define bootloader vsegs base addresses and sizes
[817]	137	### We want to pack these 4 vsegs in the same big page
[913]	138	### => boot cost is one BIG page in cluster[0][0]
[707]	139
[913]	140	boot_mapping_vbase = 0x00000000 # ident
	141	boot_mapping_size = 0x00080000 # 512 Kbytes
[707]	142
[913]	143	boot_code_vbase = 0x00080000 # ident
	144	boot_code_size = 0x00040000 # 256 Kbytes
[802]	145
[913]	146	boot_data_vbase = 0x000C0000 # ident
	147	boot_data_size = 0x000C0000 # 768 Kbytes
[707]	148
[913]	149	boot_stack_vbase = 0x00180000 # ident
	150	boot_stack_size = 0x00080000 # 512 Kbytes
[707]	151
[754]	152	### define kernel vsegs base addresses and sizes
[913]	153	### code, init, ptab, heap & sched vsegs are replicated in all clusters.
[817]	154	### data & uncdata vsegs are only mapped in cluster[0][0].
[707]	155
[802]	156	kernel_code_vbase = 0x80000000
[913]	157	kernel_code_size = 0x00100000 # 1 Mbytes per cluster
[707]	158
[913]	159	kernel_init_vbase = 0x80100000
	160	kernel_init_size = 0x00100000 # 1 Mbytes per cluster
[707]	161
[913]	162	kernel_data_vbase = 0x90000000
	163	kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0]
[707]	164
[817]	165	kernel_ptab_vbase = 0xE0000000
[913]	166	kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster
[707]	167
[913]	168	kernel_heap_vbase = 0xD0000000
	169	kernel_heap_size = 0x00200000 # 2 Mbytes per cluster
[707]	170
[817]	171	kernel_sched_vbase = 0xA0000000
	172	kernel_sched_size = 0x00002000*nb_procs # 8 Kbytes per proc per cluster
	173
[938]	174	#########################
[707]	175	### create mapping
[938]	176	#########################
[707]	177
[817]	178	mapping = Mapping( name = platform_name,
	179	x_size = x_size,
	180	y_size = y_size,
	181	nprocs = nb_procs,
	182	x_width = x_width,
	183	y_width = y_width,
[802]	184	p_width = p_width,
[817]	185	paddr_width = paddr_width,
	186	coherence = True,
	187	irq_per_proc = irq_per_proc,
	188	use_ramdisk = use_ramdisk,
	189	x_io = x_io,
[714]	190	y_io = y_io,
[802]	191	peri_increment = peri_increment,
	192	ram_base = ram_base,
	193	ram_size = ram_size )
[707]	194
	195
[938]	196	#############################
	197	### Hardware Components
	198	#############################
[707]	199
[938]	200	for x in xrange( x_size ):
	201	for y in xrange( y_size ):
	202	cluster_xy = (x << y_width) + y;
	203	offset = cluster_xy << (paddr_width - x_width - y_width)
[707]	204
[938]	205	### components replicated in all clusters
	206	ram = mapping.addRam( 'RAM', base = ram_base + offset,
	207	size = ram_size )
[707]	208
[938]	209	mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset,
	210	size = mmc_size, ptype = 'MMC' )
[707]	211
[938]	212	dma = mapping.addPeriph( 'DMA', base = dma_base + offset,
	213	size = dma_size, ptype = 'DMA',
	214	channels = nb_procs )
[707]	215
[938]	216	xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset,
	217	size = xcu_size, ptype = 'XCU',
[955]	218	channels = nb_procs * irq_per_proc,
[959]	219	arg0 = 32, arg1 = 32, arg2 = 32 )
[707]	220
[938]	221	mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' )
[707]	222
[938]	223	for i in xrange ( dma.channels ):
	224	mapping.addIrq( xcu, index = 1+i, isrtype = 'ISR_DMA',
	225	channel = i )
[707]	226
[938]	227	for p in xrange ( nb_procs ):
	228	mapping.addProc( x, y, p )
[707]	229
[938]	230	### external peripherals in cluster_io
	231	if ( (x==x_io) and (y==y_io) ):
[707]	232
[945]	233	iob = mapping.addPeriph( 'IOB', base = iob_base + offset, size = iob_size,
[938]	234	ptype = 'IOB' )
[707]	235
[945]	236	bdv = mapping.addPeriph( 'BDV', base = bdv_base + offset, size = bdv_size,
[938]	237	ptype = 'IOC', subtype = 'BDV' )
[707]	238
[945]	239	tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size,
[938]	240	ptype = 'TTY', channels = nb_ttys )
[710]	241
[945]	242	nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size,
[938]	243	ptype = 'NIC', channels = nb_nics )
[707]	244
[945]	245	cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size,
[938]	246	ptype = 'CMA', channels = nb_cmas )
[707]	247
[945]	248	fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size,
[955]	249	ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width )
[707]	250
[945]	251	rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size,
[938]	252	ptype = 'ROM' )
[707]	253
[945]	254	pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size,
[938]	255	ptype = 'PIC', channels = 32 )
[707]	256
[938]	257	mapping.addIrq( pic, index = 0, isrtype = 'ISR_NIC_RX', channel = 0 )
	258	mapping.addIrq( pic, index = 1, isrtype = 'ISR_NIC_RX', channel = 1 )
[707]	259
[938]	260	mapping.addIrq( pic, index = 2, isrtype = 'ISR_NIC_TX', channel = 0 )
	261	mapping.addIrq( pic, index = 3, isrtype = 'ISR_NIC_TX', channel = 1 )
[710]	262
[938]	263	mapping.addIrq( pic, index = 4, isrtype = 'ISR_CMA' , channel = 0 )
	264	mapping.addIrq( pic, index = 5, isrtype = 'ISR_CMA' , channel = 1 )
	265	mapping.addIrq( pic, index = 6, isrtype = 'ISR_CMA' , channel = 2 )
	266	mapping.addIrq( pic, index = 7, isrtype = 'ISR_CMA' , channel = 3 )
[770]	267
[938]	268	mapping.addIrq( pic, index = 8, isrtype = 'ISR_BDV' , channel = 0 )
[707]	269
[938]	270	mapping.addIrq( pic, index = 16, isrtype = 'ISR_TTY_RX', channel = 0 )
	271	mapping.addIrq( pic, index = 17, isrtype = 'ISR_TTY_RX', channel = 1 )
	272	mapping.addIrq( pic, index = 18, isrtype = 'ISR_TTY_RX', channel = 2 )
	273	mapping.addIrq( pic, index = 19, isrtype = 'ISR_TTY_RX', channel = 3 )
	274	mapping.addIrq( pic, index = 20, isrtype = 'ISR_TTY_RX', channel = 4 )
	275	mapping.addIrq( pic, index = 21, isrtype = 'ISR_TTY_RX', channel = 5 )
	276	mapping.addIrq( pic, index = 22, isrtype = 'ISR_TTY_RX', channel = 6 )
	277	mapping.addIrq( pic, index = 23, isrtype = 'ISR_TTY_RX', channel = 7 )
	278
	279
	280	####################################
	281	### Boot & Kernel vsegs mapping
	282	####################################
	283
[817]	284	### global vsegs for boot_loader
	285	### we want to pack those 4 vsegs in the same big page
	286	### => same flags CXW_ / identity mapping / non local / big page
[707]	287
[730]	288	mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size,
[817]	289	'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM',
	290	identity = True , local = False, big = True )
[707]	291
[730]	292	mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size,
	293	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
[817]	294	identity = True , local = False, big = True )
[707]	295
[730]	296	mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size,
[817]	297	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	298	identity = True , local = False, big = True )
[707]	299
[730]	300	mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size,
[817]	301	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	302	identity = True , local = False, big = True )
[707]	303
[943]	304	### global vseg kernel_data : big / non local
	305	### Only mapped in cluster[0][0]
	306	mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size,
	307	'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM',
	308	binpath = 'build/kernel/kernel.elf',
	309	local = False, big = True )
	310
[913]	311	### global vsegs kernel_code, kernel_init : big / local
[874]	312	### replicated in all clusters with the same name & same vbase
	313	for x in xrange( x_size ):
	314	for y in xrange( y_size ):
[817]	315	mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size,
	316	'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
	317	binpath = 'build/kernel/kernel.elf',
	318	local = True, big = True )
[707]	319
[817]	320	mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size,
	321	'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
	322	binpath = 'build/kernel/kernel.elf',
	323	local = True, big = True )
[707]	324
[938]	325	### Global vsegs kernel_ptab_x_y : big / non local
	326	### one vseg per cluster: name indexed by (x,y)
	327	for x in xrange( x_size ):
	328	for y in xrange( y_size ):
	329	offset = ((x << y_width) + y) * kernel_ptab_size
	330	base = kernel_ptab_vbase + offset
	331	mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), base, kernel_ptab_size,
	332	'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM',
	333	local = False , big = True )
	334
[913]	335	### global vsegs kernel_sched_x_y : small / non local
[874]	336	### one vseg per cluster with name indexed by (x,y)
[817]	337	for x in xrange( x_size ):
	338	for y in xrange( y_size ):
[913]	339	offset = ((x << y_width) + y) * kernel_sched_size
[938]	340	mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y),
	341	kernel_sched_vbase + offset , kernel_sched_size,
[817]	342	'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM',
	343	local = False, big = False )
[707]	344
[913]	345	### global vsegs kernel_heap_x_y : big / non local
	346	### one vseg per cluster with name indexed by (x,y)
	347	for x in xrange( x_size ):
	348	for y in xrange( y_size ):
	349	offset = ((x << y_width) + y) * kernel_heap_size
[938]	350	mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y),
	351	kernel_heap_vbase + offset , kernel_heap_size,
[913]	352	'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM',
	353	local = False, big = True )
	354
[817]	355	### global vsegs for external peripherals : non local / big page
[802]	356	mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_',
	357	vtype = 'PERI', x = 0, y = 0, pseg = 'IOB',
[817]	358	local = False, big = True )
[707]	359
[802]	360	mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_',
[730]	361	vtype = 'PERI', x = 0, y = 0, pseg = 'BDV',
[817]	362	local = False, big = True )
[707]	363
[802]	364	mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_',
[730]	365	vtype = 'PERI', x = 0, y = 0, pseg = 'TTY',
[817]	366	local = False, big = True )
[707]	367
[802]	368	mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_',
[730]	369	vtype = 'PERI', x = 0, y = 0, pseg = 'NIC',
[817]	370	local = False, big = True )
[707]	371
[802]	372	mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_',
[730]	373	vtype = 'PERI', x = 0, y = 0, pseg = 'CMA',
[817]	374	local = False, big = True )
[707]	375
[802]	376	mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_',
[730]	377	vtype = 'PERI', x = 0, y = 0, pseg = 'FBF',
[817]	378	local = False, big = True )
[707]	379
[802]	380	mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_',
[730]	381	vtype = 'PERI', x = 0, y = 0, pseg = 'PIC',
[817]	382	local = False, big = True )
[707]	383
[802]	384	mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_',
[730]	385	vtype = 'PERI', x = 0, y = 0, pseg = 'ROM',
[817]	386	local = False, big = True )
[707]	387
[817]	388	### global vsegs for internal peripherals : non local / small pages
	389	### allocated in all clusters with name indexed by (x,y)
	390	### as vbase address is incremented by (cluster_xy * vseg_increment)
[714]	391	for x in xrange( x_size ):
	392	for y in xrange( y_size ):
[817]	393	offset = ((x << y_width) + y) * peri_increment
[707]	394
[714]	395	mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size,
[817]	396	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU',
	397	local = False, big = False )
[707]	398
[714]	399	mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size,
[817]	400	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA',
	401	local = False, big = False )
[707]	402
[714]	403	mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size,
[817]	404	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC',
	405	local = False, big = False )
[707]	406
	407	return mapping
	408
[938]	409	################################# platform test ####################################
[707]	410
	411	if __name__ == '__main__':
	412
[730]	413	mapping = arch( x_size = 2,
	414	y_size = 2,
	415	nb_procs = 2 )
[707]	416
	417	# print mapping.netbsd_dts()
	418
	419	print mapping.xml()
	420
	421	# print mapping.giet_vsegs()
	422
[802]	423
[707]	424	# Local Variables:
	425	# tab-width: 4;
	426	# c-basic-offset: 4;
	427	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	428	# indent-tabs-mode: nil;
	429	# End:
	430	#
	431	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	432

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