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source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 972

Last change on this file since 972 was 972, checked in by alain, 9 years ago
Modify the tsar_generic_iob platform: The vci_multi_dma component replicated in all cluster is replaced by a vci_mwmr_dma component. This new component supports all hardware coprocessors respection the "coproc" interface. Amongst the available coprocessors (defined in the SocLib? "coprocessor_components" directory) the MWR_CPY coprocessor provide an improved memory copy service throughput x 2).
File size: 37.5 KB

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[450]	1	//////////////////////////////////////////////////////////////////////////////
	2	// File: tsar_iob_cluster.cpp
[802]	3	// Author: Alain Greiner
[450]	4	// Copyright: UPMC/LIP6
	5	// Date : april 2013
	6	// This program is released under the GNU public license
	7	//////////////////////////////////////////////////////////////////////////////
	8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
	9	// These two clusters contain 6 extra components:
	10	// - 1 vci_io_bridge (connected to the 3 networks.
	11	// - 3 vci_dspin_wrapper for the IOB.
[802]	12	// - 2 dspin_local_crossbar for commands and responses.
[450]	13	//////////////////////////////////////////////////////////////////////////////
	14
	15	#include "../include/tsar_iob_cluster.h"
	16
[972]	17	#define MWR_COPROC_CPY 0
	18	#define MWR_COPROC_DCT 1
	19	#define MWR_COPROC_GCD 2
	20
[718]	21	#define tmpl(x) \
	22	template<typename vci_param_int , typename vci_param_ext,\
	23	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
	24	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
	25	x TsarIobCluster<\
	26	vci_param_int , vci_param_ext,\
	27	dspin_int_cmd_width, dspin_int_rsp_width,\
	28	dspin_ram_cmd_width, dspin_ram_rsp_width>
	29
[450]	30	namespace soclib { namespace caba {
	31
[972]	32	/////////////////////////////////////////////////////////////////////////////
[718]	33	tmpl(/**/)::TsarIobCluster(
[972]	34	/////////////////////////////////////////////////////////////////////////////
[450]	35	sc_module_name insname,
	36	size_t nb_procs,
	37	size_t x_id,
	38	size_t y_id,
	39	size_t xmax,
	40	size_t ymax,
	41
	42	const soclib::common::MappingTable &mt_int,
[802]	43	const soclib::common::MappingTable &mt_ram,
	44	const soclib::common::MappingTable &mt_iox,
[450]	45
	46	size_t x_width,
	47	size_t y_width,
	48	size_t l_width,
[802]	49	size_t p_width,
[450]	50
[718]	51	size_t int_memc_tgt_id, // local index
	52	size_t int_xicu_tgt_id, // local index
[972]	53	size_t int_mwmr_tgt_id, // local index
[718]	54	size_t int_iobx_tgt_id, // local index
[450]	55
[718]	56	size_t int_proc_ini_id, // local index
[972]	57	size_t int_mwmr_ini_id, // local index
[718]	58	size_t int_iobx_ini_id, // local index
[450]	59
[718]	60	size_t ram_xram_tgt_id, // local index
	61	size_t ram_memc_ini_id, // local index
	62	size_t ram_iobx_ini_id, // local index
[450]	63
[718]	64	bool is_io, // is IO cluster (IOB)?
	65	size_t iox_iobx_tgt_id, // local_index
	66	size_t iox_iobx_ini_id, // local index
[450]	67
	68	size_t memc_ways,
	69	size_t memc_sets,
	70	size_t l1_i_ways,
	71	size_t l1_i_sets,
	72	size_t l1_d_ways,
	73	size_t l1_d_sets,
	74	size_t xram_latency,
[959]	75	size_t xcu_nb_hwi,
	76	size_t xcu_nb_pti,
	77	size_t xcu_nb_wti,
	78	size_t xcu_nb_out,
[450]	79
[972]	80	size_t coproc_type,
	81
[450]	82	const Loader &loader,
	83
	84	uint32_t frozen_cycles,
	85	uint32_t debug_start_cycle,
	86	bool memc_debug_ok,
	87	bool proc_debug_ok,
	88	bool iob_debug_ok )
	89	: soclib::caba::BaseModule(insname),
	90	p_clk("clk"),
	91	p_resetn("resetn")
	92	{
[972]	93	assert( (x_id < xmax) and (y_id < ymax) and
	94	"Error in tsar_iob_cluster : Illegal cluster coordinates");
[450]	95
[607]	96	size_t cluster_id = (x_id<<4) + y_id;
[450]	97
	98	// Vectors of DSPIN ports for inter-cluster communications
[468]	99	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
	100	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
	101	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
	102	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
[450]	103
	104	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
	105	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
	106	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
	107	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
	108
[718]	109	// VCI ports from IOB to IOX network (only in IO clusters)
	110	if ( is_io )
[450]	111	{
[550]	112	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
[802]	113	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
[450]	114	}
	115
	116	/////////////////////////////////////////////////////////////////////////////
	117	// Hardware components
	118	/////////////////////////////////////////////////////////////////////////////
	119
	120	//////////// PROCS
	121	for (size_t p = 0; p < nb_procs; p++)
[802]	122	{
[450]	123	std::ostringstream s_proc;
	124	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
	125	proc[p] = new VciCcVCacheWrapper<vci_param_int,
	126	dspin_int_cmd_width,
	127	dspin_int_rsp_width,
	128	GdbServer<Mips32ElIss> >(
	129	s_proc.str().c_str(),
[802]	130	(cluster_id << p_width) + p, // GLOBAL PROC_ID
[450]	131	mt_int, // Mapping Table INT network
	132	IntTab(cluster_id,p), // SRCID
	133	(cluster_id << l_width) + p, // CC_GLOBAL_ID
	134	8, // ITLB ways
	135	8, // ITLB sets
	136	8, // DTLB ways
	137	8, // DTLB sets
[718]	138	l1_i_ways, l1_i_sets, 16, // ICACHE size
	139	l1_d_ways, l1_d_sets, 16, // DCACHE size
[450]	140	4, // WBUF nlines
	141	4, // WBUF nwords
	142	x_width,
	143	y_width,
	144	frozen_cycles, // max frozen cycles
	145	debug_start_cycle,
	146	proc_debug_ok);
	147	}
	148
[802]	149	/////////// MEMC
[450]	150	std::ostringstream s_memc;
	151	s_memc << "memc_" << x_id << "_" << y_id;
	152	memc = new VciMemCache<vci_param_int,
	153	vci_param_ext,
	154	dspin_int_rsp_width,
	155	dspin_int_cmd_width>(
	156	s_memc.str().c_str(),
[718]	157	mt_int, // Mapping Table INT network
	158	mt_ram, // Mapping Table RAM network
	159	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
	160	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
	161	x_width, // number of bits for x coordinate
	162	y_width, // number of bits for y coordinate
	163	memc_ways, memc_sets, 16, // CACHE SIZE
	164	3, // MAX NUMBER OF COPIES
	165	4096, // HEAP SIZE
	166	8, // TRANSACTION TABLE DEPTH
	167	8, // UPDATE TABLE DEPTH
	168	8, // INVALIDATE TABLE DEPTH
[450]	169	debug_start_cycle,
	170	memc_debug_ok );
	171
	172	std::ostringstream s_wi_memc;
	173	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
	174	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
	175	dspin_ram_cmd_width,
	176	dspin_ram_rsp_width>(
	177	s_wi_memc.str().c_str(),
	178	x_width + y_width + l_width);
	179
	180	/////////// XICU
	181	std::ostringstream s_xicu;
	182	s_xicu << "xicu_" << x_id << "_" << y_id;
	183	xicu = new VciXicu<vci_param_int>(
	184	s_xicu.str().c_str(),
[718]	185	mt_int, // mapping table INT network
	186	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
[959]	187	xcu_nb_pti, // number of timer IRQs
	188	xcu_nb_hwi, // number of hard IRQs
	189	xcu_nb_wti, // number of soft IRQs
	190	xcu_nb_out); // number of output IRQs
[450]	191
[972]	192	//////////// MWMR controller and coprocessor
	193	std::ostringstream s_mwmr;
	194	std::ostringstream s_copro;
	195	s_mwmr << "mwmr_" << x_id << "_" << y_id;
	196
	197	if ( coproc_type == MWR_COPROC_CPY)
	198	{
	199	s_copro << "cpy_" << x_id << "_" << y_id;
	200	cpy = new CoprocCpy( s_copro.str().c_str(), 64 ); // burst size
	201
	202	mwmr = new VciMwmrDma<vci_param_int>(
	203	s_mwmr.str().c_str(),
[450]	204	mt_int,
[972]	205	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
	206	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
	207	1, // nb to_coproc ports
	208	1, // nb from_coproc ports
	209	1, // nb config registers
	210	0, // nb status registers
	211	64 ); // burst size (bytes)
	212	}
	213	if ( coproc_type == MWR_COPROC_DCT )
	214	{
	215	s_copro << "dct_" << x_id << "_" << y_id;
	216	dct = new CoprocDct( s_copro.str().c_str(), 64 , 16 ); // burst size / latency
[450]	217
[972]	218	mwmr = new VciMwmrDma<vci_param_int>(
	219	s_mwmr.str().c_str(),
	220	mt_int,
	221	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
	222	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
	223	1, // nb to_coproc ports
	224	1, // nb from_coproc ports
	225	1, // nb config registers
	226	0, // nb status registers
	227	64 ); // burst size (bytes)
	228	}
	229	if ( coproc_type == MWR_COPROC_GCD )
	230	{
	231	s_copro << "gcd_" << x_id << "_" << y_id;
	232	gcd = new CoprocGcd( s_copro.str().c_str(), 64 ); // burst size
	233
	234	mwmr = new VciMwmrDma<vci_param_int>(
	235	s_mwmr.str().c_str(),
	236	mt_int,
	237	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
	238	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
	239	2, // nb to_coproc ports
	240	1, // nb from_coproc ports
	241	1, // nb config registers
	242	0, // nb status registers
	243	64 ); // burst size (bytes)
	244	}
	245
[450]	246	/////////// Direct LOCAL_XBAR(S)
[718]	247	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
	248	size_t nb_direct_targets = is_io ? 4 : 3;
[450]	249
[693]	250	std::ostringstream s_int_xbar_d;
	251	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
	252	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
	253	s_int_xbar_d.str().c_str(),
[450]	254	mt_int, // mapping table
[693]	255	cluster_id, // cluster id
	256	nb_direct_initiators, // number of local initiators
[802]	257	nb_direct_targets, // number of local targets
[693]	258	0 ); // default target
[450]	259
[693]	260	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
	261	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
	262	<< x_id << "_" << y_id;
	263	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
	264	dspin_int_cmd_width,
	265	dspin_int_rsp_width>(
	266	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
	267	x_width + y_width + l_width);
[450]	268
[693]	269	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
	270	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
	271	<< x_id << "_" << y_id;
	272	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
	273	dspin_int_cmd_width,
	274	dspin_int_rsp_width>(
	275	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
	276	x_width + y_width + l_width);
	277
[450]	278	//////////// Coherence LOCAL_XBAR(S)
	279	std::ostringstream s_int_xbar_m2p_c;
	280	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
	281	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
	282	s_int_xbar_m2p_c.str().c_str(),
	283	mt_int, // mapping table
	284	x_id, y_id, // cluster coordinates
	285	x_width, y_width, l_width, // several dests
	286	1, // number of local sources
[802]	287	nb_procs, // number of local dests
	288	2, 2, // fifo depths
[450]	289	true, // pseudo CMD
	290	false, // no routing table
	291	true ); // broacast
	292
	293	std::ostringstream s_int_xbar_p2m_c;
	294	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
	295	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
	296	s_int_xbar_p2m_c.str().c_str(),
	297	mt_int, // mapping table
	298	x_id, y_id, // cluster coordinates
	299	x_width, y_width, 0, // only one dest
	300	nb_procs, // number of local sources
	301	1, // number of local dests
[802]	302	2, 2, // fifo depths
[450]	303	false, // pseudo RSP
	304	false, // no routing table
[802]	305	false ); // no broacast
[450]	306
[468]	307	std::ostringstream s_int_xbar_clack_c;
	308	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
	309	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
	310	s_int_xbar_clack_c.str().c_str(),
	311	mt_int, // mapping table
	312	x_id, y_id, // cluster coordinates
	313	x_width, y_width, l_width,
	314	1, // number of local sources
[802]	315	nb_procs, // number of local targets
[468]	316	1, 1, // fifo depths
	317	true, // CMD
[707]	318	false, // no routing table
[468]	319	false); // broadcast
	320
[450]	321	////////////// INT ROUTER(S)
	322	std::ostringstream s_int_router_cmd;
	323	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
	324	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
	325	s_int_router_cmd.str().c_str(),
	326	x_id,y_id, // coordinate in the mesh
	327	x_width, y_width, // x & y fields width
[468]	328	3, // nb virtual channels
[450]	329	4,4); // input & output fifo depths
	330
	331	std::ostringstream s_int_router_rsp;
	332	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
	333	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
	334	s_int_router_rsp.str().c_str(),
[550]	335	x_id,y_id, // router coordinates in mesh
[450]	336	x_width, y_width, // x & y fields width
[468]	337	2, // nb virtual channels
[450]	338	4,4); // input & output fifo depths
	339
	340	////////////// XRAM
	341	std::ostringstream s_xram;
	342	s_xram << "xram_" << x_id << "_" << y_id;
	343	xram = new VciSimpleRam<vci_param_ext>(
	344	s_xram.str().c_str(),
[718]	345	IntTab(cluster_id, ram_xram_tgt_id),
[450]	346	mt_ram,
	347	loader,
	348	xram_latency);
	349
	350	std::ostringstream s_wt_xram;
	351	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
	352	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
	353	dspin_ram_cmd_width,
	354	dspin_ram_rsp_width>(
	355	s_wt_xram.str().c_str(),
	356	x_width + y_width + l_width);
	357
	358	///////////// RAM ROUTER(S)
	359	std::ostringstream s_ram_router_cmd;
	360	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
[718]	361	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
[450]	362	s_ram_router_cmd.str().c_str(),
[584]	363	x_id, y_id, // router coordinates in mesh
	364	x_width, // x field width in first flit
	365	y_width, // y field width in first flit
[718]	366	4, 4); // input & output fifo depths
[450]	367
	368	std::ostringstream s_ram_router_rsp;
	369	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
[718]	370	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
[450]	371	s_ram_router_rsp.str().c_str(),
[584]	372	x_id, y_id, // coordinates in mesh
	373	x_width, // x field width in first flit
	374	y_width, // y field width in first flit
[718]	375	4, 4); // input & output fifo depths
[450]	376
[550]	377
[450]	378	////////////////////// I/O CLUSTER ONLY ///////////////////////
[718]	379	if ( is_io )
[450]	380	{
	381	/////////// IO_BRIDGE
	382	std::ostringstream s_iob;
[802]	383	s_iob << "iob_" << x_id << "_" << y_id;
[450]	384	iob = new VciIoBridge<vci_param_int,
[802]	385	vci_param_ext>(
[450]	386	s_iob.str().c_str(),
[718]	387	mt_ram, // EXT network maptab
	388	mt_int, // INT network maptab
	389	mt_iox, // IOX network maptab
	390	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
	391	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
	392	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
	393	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
	394	16, // cache line words
	395	8, // IOTLB ways
	396	8, // IOTLB sets
[450]	397	debug_start_cycle,
	398	iob_debug_ok );
[802]	399
[450]	400	std::ostringstream s_iob_ram_wi;
[802]	401	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
[450]	402	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
	403	dspin_ram_cmd_width,
	404	dspin_ram_rsp_width>(
	405	s_iob_ram_wi.str().c_str(),
[718]	406	vci_param_int::S);
	407
	408	std::ostringstream s_ram_xbar_cmd;
	409	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
	410	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
	411	s_ram_xbar_cmd.str().c_str(), // name
	412	mt_ram, // mapping table
	413	x_id, y_id, // x, y
	414	x_width, y_width, l_width, // x_width, y_width, l_width
	415	2, 0, // local inputs, local outputs
	416	2, 2, // in fifo, out fifo depths
	417	true, // is cmd ?
	418	false, // use routing table ?
	419	false); // support broadcast ?
	420
	421	std::ostringstream s_ram_xbar_rsp;
	422	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
	423	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
	424	s_ram_xbar_rsp.str().c_str(), // name
	425	mt_ram, // mapping table
	426	x_id, y_id, // x, y
	427	x_width, y_width, l_width, // x_width, y_width, l_width
	428	0, 2, // local inputs, local outputs
	429	2, 2, // in fifo, out fifo depths
	430	false, // is cmd ?
	431	true, // use routing table ?
	432	false); // support broadcast ?
[550]	433	} // end if IO
[450]	434
	435	////////////////////////////////////
	436	// Connections are defined here
	437	////////////////////////////////////
	438
	439	// on coherence network : local srcid[proc] in [0...nb_procs-1]
	440	// : local srcid[memc] = nb_procs
[802]	441
[450]	442	//////////////////////// internal CMD & RSP routers
	443	int_router_cmd->p_clk (this->p_clk);
	444	int_router_cmd->p_resetn (this->p_resetn);
	445	int_router_rsp->p_clk (this->p_clk);
	446	int_router_rsp->p_resetn (this->p_resetn);
[468]	447
	448	for (int i = 0; i < 4; i++)
[450]	449	{
[468]	450	for(int k = 0; k < 3; k++)
[450]	451	{
[468]	452	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
	453	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
[450]	454	}
[468]	455
	456	for(int k = 0; k < 2; k++)
	457	{
	458	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
	459	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
	460	}
[450]	461	}
	462
	463	// local ports
[468]	464	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
	465	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
	466	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
	467	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
	468	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
	469	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
[802]	470
[468]	471	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
	472	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
	473	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
	474	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
[450]	475
	476	///////////////////// CMD DSPIN local crossbar direct
[693]	477	int_xbar_d->p_clk (this->p_clk);
	478	int_xbar_d->p_resetn (this->p_resetn);
	479	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
	480	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
[450]	481
[718]	482	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
	483	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
[972]	484	int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr);
	485	int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr);
[450]	486	for (size_t p = 0; p < nb_procs; p++)
[718]	487	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
[450]	488
[718]	489	if ( is_io )
[450]	490	{
[718]	491	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
	492	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
[450]	493	}
	494
[714]	495	int_wi_gate_d->p_clk (this->p_clk);
	496	int_wi_gate_d->p_resetn (this->p_resetn);
	497	int_wi_gate_d->p_vci (signal_int_vci_l2g);
	498	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
	499	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
[450]	500
[714]	501	int_wt_gate_d->p_clk (this->p_clk);
	502	int_wt_gate_d->p_resetn (this->p_resetn);
	503	int_wt_gate_d->p_vci (signal_int_vci_g2l);
	504	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
	505	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
[802]	506
[450]	507	////////////////////// M2P DSPIN local crossbar coherence
	508	int_xbar_m2p_c->p_clk (this->p_clk);
	509	int_xbar_m2p_c->p_resetn (this->p_resetn);
	510	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
	511	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
	512	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
[802]	513	for (size_t p = 0; p < nb_procs; p++)
[450]	514	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
	515
	516	////////////////////////// P2M DSPIN local crossbar coherence
	517	int_xbar_p2m_c->p_clk (this->p_clk);
	518	int_xbar_p2m_c->p_resetn (this->p_resetn);
	519	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
	520	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
	521	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
[802]	522	for (size_t p = 0; p < nb_procs; p++)
[450]	523	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
	524
[468]	525	////////////////////// CLACK DSPIN local crossbar coherence
	526	int_xbar_clack_c->p_clk (this->p_clk);
	527	int_xbar_clack_c->p_resetn (this->p_resetn);
	528	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
	529	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
	530	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
	531	for (size_t p = 0; p < nb_procs; p++)
	532	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
	533
[450]	534	//////////////////////////////////// Processors
	535	for (size_t p = 0; p < nb_procs; p++)
	536	{
	537	proc[p]->p_clk (this->p_clk);
	538	proc[p]->p_resetn (this->p_resetn);
	539	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
[468]	540	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
	541	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
	542	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
[707]	543
	544	for ( size_t j = 0 ; j < 6 ; j++)
[450]	545	{
[707]	546	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
	547	else proc[p]->p_irq[j] (signal_false);
[450]	548	}
	549	}
	550
	551	///////////////////////////////////// XICU
[468]	552	xicu->p_clk (this->p_clk);
	553	xicu->p_resetn (this->p_resetn);
	554	xicu->p_vci (signal_int_vci_tgt_xicu);
[959]	555	for ( size_t i=0 ; i < xcu_nb_out ; i++)
[450]	556	{
[714]	557	xicu->p_irq[i] (signal_proc_it[i]);
[450]	558	}
[959]	559	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
[450]	560	{
[707]	561	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
[972]	562	else if ( i == 1 ) xicu->p_hwi[i] (signal_irq_mwmr);
[707]	563	else xicu->p_hwi[i] (signal_false);
[802]	564	}
[450]	565
	566	///////////////////////////////////// MEMC
[468]	567	memc->p_clk (this->p_clk);
	568	memc->p_resetn (this->p_resetn);
	569	memc->p_vci_ixr (signal_ram_vci_ini_memc);
	570	memc->p_vci_tgt (signal_int_vci_tgt_memc);
	571	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
	572	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
	573	memc->p_dspin_clack (signal_int_dspin_clack_memc);
[607]	574	memc->p_irq (signal_irq_memc);
[450]	575
	576	// wrapper to RAM network
	577	memc_ram_wi->p_clk (this->p_clk);
	578	memc_ram_wi->p_resetn (this->p_resetn);
	579	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
	580	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
	581	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
	582
	583	//////////////////////////////////// XRAM
[468]	584	xram->p_clk (this->p_clk);
	585	xram->p_resetn (this->p_resetn);
	586	xram->p_vci (signal_ram_vci_tgt_xram);
[450]	587
	588	// wrapper to RAM network
	589	xram_ram_wt->p_clk (this->p_clk);
	590	xram_ram_wt->p_resetn (this->p_resetn);
	591	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
	592	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
	593	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
	594
[972]	595	/////////////////////////////////// GCD coprocessor
	596	if ( coproc_type == MWR_COPROC_GCD )
	597	{
	598	gcd->p_clk (this->p_clk);
	599	gcd->p_resetn (this->p_resetn);
	600	gcd->p_opa (signal_to_coproc[0]);
	601	gcd->p_opb (signal_to_coproc[1]);
	602	gcd->p_res (signal_from_coproc[0]);
	603	gcd->p_config (signal_config_coproc[0]);
[450]	604
[972]	605	mwmr->p_clk (this->p_clk);
	606	mwmr->p_resetn (this->p_resetn);
	607	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
	608	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
	609	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
	610	mwmr->p_to_coproc[1] (signal_to_coproc[1]);
	611	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
	612	mwmr->p_config[0] (signal_config_coproc[0]);
	613	mwmr->p_irq (signal_irq_mwmr);
	614	}
	615
	616	/////////////////////////////////// DCT coprocessor
	617	if ( coproc_type == MWR_COPROC_DCT )
	618	{
	619	dct->p_clk (this->p_clk);
	620	dct->p_resetn (this->p_resetn);
	621	dct->p_in (signal_to_coproc[0]);
	622	dct->p_out (signal_from_coproc[0]);
	623	dct->p_config (signal_config_coproc[0]);
	624
	625	mwmr->p_clk (this->p_clk);
	626	mwmr->p_resetn (this->p_resetn);
	627	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
	628	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
	629	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
	630	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
	631	mwmr->p_config[0] (signal_config_coproc[0]);
	632	mwmr->p_irq (signal_irq_mwmr);
	633	}
	634
	635	/////////////////////////////////// CPY coprocessor
	636	if ( coproc_type == MWR_COPROC_CPY )
	637	{
	638	cpy->p_clk (this->p_clk);
	639	cpy->p_resetn (this->p_resetn);
	640	cpy->p_load (signal_to_coproc[0]);
	641	cpy->p_store (signal_from_coproc[0]);
	642	cpy->p_config (signal_config_coproc[0]);
	643
	644	mwmr->p_clk (this->p_clk);
	645	mwmr->p_resetn (this->p_resetn);
	646	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
	647	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
	648	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
	649	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
	650	mwmr->p_config[0] (signal_config_coproc[0]);
	651	mwmr->p_irq (signal_irq_mwmr);
	652	}
	653
[550]	654	//////////////////////////// RAM network CMD & RSP routers
[707]	655	ram_router_cmd->p_clk (this->p_clk);
	656	ram_router_cmd->p_resetn (this->p_resetn);
	657	ram_router_rsp->p_clk (this->p_clk);
	658	ram_router_rsp->p_resetn (this->p_resetn);
[550]	659	for( size_t n=0 ; n<4 ; n++)
[450]	660	{
[707]	661	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
	662	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
	663	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
	664	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
[450]	665	}
[718]	666
[707]	667	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
	668	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
[718]	669
	670	if ( is_io )
	671	{
	672	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
	673	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
	674	}
	675	else
	676	{
	677	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
	678	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
	679	}
[802]	680
	681	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
[718]	682	if ( is_io )
[450]	683	{
	684	// IO bridge
[718]	685	iob->p_clk (this->p_clk);
	686	iob->p_resetn (this->p_resetn);
	687	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
	688	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
	689	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
	690	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
	691	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
[550]	692
[450]	693	// initiator wrapper to RAM network
[718]	694	iob_ram_wi->p_clk (this->p_clk);
	695	iob_ram_wi->p_resetn (this->p_resetn);
	696	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
	697	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
	698	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
	699
	700	// crossbar between MEMC and IOB to RAM network
	701	ram_xbar_cmd->p_clk (this->p_clk);
	702	ram_xbar_cmd->p_resetn (this->p_resetn);
	703	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
	704	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
	705	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
	706	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
	707
	708	ram_xbar_rsp->p_clk (this->p_clk);
	709	ram_xbar_rsp->p_resetn (this->p_resetn);
	710	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
	711	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
	712	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
	713	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
[550]	714	}
[450]	715
[739]	716	SC_METHOD(init);
	717
[450]	718	} // end constructor
	719
[718]	720	tmpl(void)::init()
	721	{
	722	signal_ram_dspin_cmd_false.write = false;
[739]	723	signal_ram_dspin_rsp_false.read = true;
[972]	724	}
[718]	725
[450]	726	}}
	727
	728
	729	// Local Variables:
	730	// tab-width: 3
	731	// c-basic-offset: 3
	732	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	733	// indent-tabs-mode: nil
	734	// End:
	735
	736	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
	737

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Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
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Language-Team: en_US <trac-dev@googlegroups.com>
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