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source: trunk/platforms/tsar_generic_leti/arch.py @ 958

Last change on this file since 958 was 954, checked in by alain, 10 years ago
Modify the arch.py file to comply with the new prototype for the addPeriph(): 4 arguments arg0,arg1,arg2,arg3.
Property svn:executable set to ``*
File size: 17.6 KB

Rev	Line
[793]	1	#!/usr/bin/env python
	2
[803]	3	from math import log, ceil
[793]	4	from mapping import *
	5
	6	###############################################################################
[803]	7	# file : arch.py (for the tsar_generic_leti architecture)
[793]	8	# date : may 2014
	9	# author : Alain Greiner
	10	###############################################################################
[803]	11	# This file contains a mapping generator for the "tsar_generic_leti" platform.
[793]	12	# This includes both the hardware architecture (clusters, processors,
[937]	13	# peripherals, physical space segmentation) and the mapping of all boot
	14	# and kernel objects (global vsegs).
[793]	15	#
[937]	16	# The x_size & y_size parameters define the total number of clusters.
	17	# The upper row (y = y_size-1) does not contain processors or memory.
	18	#
	19	# It does not use the IOB component:
	20	# The external peripherals are located in cluster[x_size-1][y_size-1].
	21	#
	22	# It does not use an external ROM, as the preloader code is (pre)loaded
	23	# at address 0x0, in the physical memory of cluster[0][0].
	24	#
	25	# It can use an - optional - RAMDISK located in cluster[0][0].
	26	#
	27	# The others hardware parameters are:
[820]	28	# - fbf_width : frame_buffer width = frame_buffer heigth
[793]	29	# - nb_ttys : number of TTY channels
	30	# - nb_nics : number of NIC channels
[937]	31	# - nb_cmas : number of CMA channels
[793]	32	# - irq_per_proc : number of input IRQs per processor
[937]	33	# - use_ramdisk : use a RAMDISK when True
[793]	34	# - peri_increment : address increment for replicated peripherals
[820]	35	#
[937]	36	# Regarding the boot and kernel vsegs mapping :
	37	# - We use one big physical page (2 Mbytes) for the preloader and the four
	38	# boot vsegs, all allocated in cluster[0,0].
	39	# - We use the 16 next big pages in cluster[0][0] to implement the RAMDISK.
	40	# - We use one big page per cluster for the replicated kernel code vsegs.
	41	# - We use one big page in cluster[0][0] for the kernel data vseg.
	42	# - We use one big page per cluster for the distributed kernel heap vsegs.
	43	# - We use one big page per cluster for the distributed ptab vsegs.
	44	# - We use small physical pages (4 Kbytes) per cluster for the schedulers.
	45	# - We use one big page for each external peripheral in IO cluster,
	46	# - We use one small page per cluster for each internal peripheral.
	47	###############################################################################
[793]	48
	49	########################
[820]	50	def arch( x_size = 2,
	51	y_size = 2,
[937]	52	nb_procs = 4,
	53	nb_ttys = 1,
[820]	54	fbf_width = 128 ):
[793]	55
	56	### define architecture constants
	57
[937]	58	nb_nics = 1
	59	nb_cmas = 2
	60	x_io = x_size - 1
	61	y_io = y_size - 1
[820]	62	x_width = 4
	63	y_width = 4
[822]	64	p_width = 2
[820]	65	paddr_width = 40
	66	irq_per_proc = 4
[937]	67	use_ramdisk = False
	68	peri_increment = 0x10000 # distributed peripherals vbase increment
	69	reset_address = 0x00000000 # wired preloader pbase address
[793]	70
	71	### parameters checking
	72
[803]	73	assert( nb_procs <= (1 << p_width) )
[793]	74
[937]	75	assert( x_size <= (1 << x_width) )
[793]	76
[937]	77	assert( y_size <= (1 << y_width) )
[793]	78
[937]	79	### define type and name
[793]	80
[937]	81	platform_type = 'tsar_leti'
	82	platform_name = '%s_%d_%d_%d' % (platform_type, x_size, y_size, nb_procs )
[793]	83
[937]	84	### define physical segments replicated in all clusters
	85	### the base address is extended by the cluster_xy (8 bits)
[793]	86
[937]	87	ram_base = 0x00000000
[793]	88	ram_size = 0x4000000 # 64 Mbytes
	89
[937]	90	xcu_base = 0xF0000000
[793]	91	xcu_size = 0x1000 # 4 Kbytes
	92
[937]	93	mmc_base = 0xF1000000
[793]	94	mmc_size = 0x1000 # 4 Kbytes
	95
[820]	96	### define physical segments for external peripherals
	97	## These segments are only defined in cluster_io
	98
[944]	99	bdv_base = 0xF2000000
[793]	100	bdv_size = 0x1000 # 4kbytes
	101
[944]	102	tty_base = 0xF4000000
[793]	103	tty_size = 0x4000 # 16 Kbytes
	104
[944]	105	nic_base = 0xF7000000
[793]	106	nic_size = 0x80000 # 512 kbytes
	107
[944]	108	cma_base = 0xF8000000
[793]	109	cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics
	110
[944]	111	pic_base = 0xF9000000
[937]	112	pic_size = 0x1000 # 4 Kbytes
	113
[944]	114	fbf_base = 0xF3000000
[793]	115	fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes
	116
	117
[819]	118	### define preloader & bootloader vsegs base addresses and sizes
[820]	119	### We want to pack these 5 vsegs in the same big page
	120	### => boot cost is one BPP in cluster[0][0]
[803]	121
	122	preloader_vbase = 0x00000000 # ident
	123	preloader_size = 0x00010000 # 64 Kbytes
	124
	125	boot_mapping_vbase = 0x00010000 # ident
[793]	126	boot_mapping_size = 0x00080000 # 512 Kbytes
	127
[803]	128	boot_code_vbase = 0x00090000 # ident
[793]	129	boot_code_size = 0x00040000 # 256 Kbytes
	130
[803]	131	boot_data_vbase = 0x000D0000 # ident
[939]	132	boot_data_size = 0x000B0000 # 704 Kbytes
[793]	133
[939]	134	boot_stack_vbase = 0x00180000 # ident
	135	boot_stack_size = 0x00080000 # 512 Kbytes
[793]	136
[937]	137	### define ramdisk vseg / must be identity mapping in cluster[0][0]
	138	### occupies 15 BPP after the boot
	139	ramdisk_vbase = 0x00200000
	140	ramdisk_size = 0x02000000 # 32 Mbytes
	141
[793]	142	### define kernel vsegs base addresses and sizes
[937]	143	### code, init, ptab, heap & sched vsegs are replicated in all clusters.
[820]	144	### data & uncdata vsegs are only mapped in cluster[0][0].
	145
[793]	146	kernel_code_vbase = 0x80000000
[937]	147	kernel_code_size = 0x00100000 # 1 Mbytes per cluster
[793]	148
[937]	149	kernel_init_vbase = 0x80100000
	150	kernel_init_size = 0x00100000 # 1 Mbytes per cluster
[793]	151
[937]	152	kernel_data_vbase = 0x90000000
	153	kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0][0]
[793]	154
[937]	155	kernel_ptab_vbase = 0xE0000000
[825]	156	kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster
	157
[937]	158	kernel_heap_vbase = 0xD0000000
	159	kernel_heap_size = 0x00200000 # 2 Mbytes per cluster
	160
	161	kernel_sched_vbase = 0xA0000000
	162	kernel_sched_size = 0x00002000 * nb_procs # 8 kbytes per proc per cluster
	163
	164	#####################
[793]	165	### create mapping
[937]	166	#####################
[793]	167
	168	mapping = Mapping( name = platform_name,
	169	x_size = x_size,
	170	y_size = y_size,
[819]	171	nprocs = nb_procs,
[793]	172	x_width = x_width,
	173	y_width = y_width,
[803]	174	p_width = p_width,
[793]	175	paddr_width = paddr_width,
	176	coherence = True,
	177	irq_per_proc = irq_per_proc,
	178	use_ramdisk = use_ramdisk,
	179	x_io = x_io,
	180	y_io = y_io,
	181	peri_increment = peri_increment,
	182	reset_address = reset_address,
	183	ram_base = ram_base,
	184	ram_size = ram_size )
	185
[937]	186	###########################
	187	### Hardware Description
	188	###########################
[793]	189
[937]	190	for x in xrange( x_size ):
	191	for y in xrange( y_size ):
	192	cluster_xy = (x << y_width) + y;
	193	offset = cluster_xy << (paddr_width - x_width - y_width)
	194
	195	### components replicated in all clusters but the upper row
	196	if ( y < (y_size - 1) ):
[793]	197
[937]	198	ram = mapping.addRam( 'RAM', base = ram_base + offset,
	199	size = ram_size )
[793]	200
[937]	201	mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset,
	202	size = mmc_size, ptype = 'MMC' )
[793]	203
[937]	204	xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset,
	205	size = xcu_size, ptype = 'XCU',
[954]	206	channels = nb_procs * irq_per_proc,
	207	arg0 = 16, arg1 = 16, arg2 = 16, arg3 = 16 )
[793]	208
[937]	209	mapping.addIrq( xcu, index = 8, isrtype = 'ISR_MMC' )
[793]	210
[937]	211	for p in xrange ( nb_procs ):
	212	mapping.addProc( x, y, p )
[793]	213
[937]	214	### external peripherals in cluster_io
	215	if ( (x==x_io) and (y==y_io) ):
[793]	216
[944]	217	bdv = mapping.addPeriph( 'BDV', base = bdv_base + offset, size = bdv_size,
[937]	218	ptype = 'IOC', subtype = 'BDV' )
[826]	219
[944]	220	tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size,
[937]	221	ptype = 'TTY', channels = nb_ttys )
[793]	222
[944]	223	nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size,
[937]	224	ptype = 'NIC', channels = nb_nics )
[793]	225
[944]	226	cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size,
[937]	227	ptype = 'CMA', channels = nb_cmas )
[793]	228
[944]	229	fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size,
[954]	230	ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width )
[793]	231
[944]	232	pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size,
[937]	233	ptype = 'PIC', channels = 32 )
[793]	234
[937]	235	mapping.addIrq( pic, index = 0 , isrtype = 'ISR_NIC_RX', channel = 0 )
	236	mapping.addIrq( pic, index = 1 , isrtype = 'ISR_NIC_RX', channel = 1 )
[793]	237
[937]	238	mapping.addIrq( pic, index = 2 , isrtype = 'ISR_NIC_TX', channel = 0 )
	239	mapping.addIrq( pic, index = 3 , isrtype = 'ISR_NIC_TX', channel = 1 )
[793]	240
[937]	241	mapping.addIrq( pic, index = 4 , isrtype = 'ISR_CMA' , channel = 0 )
	242	mapping.addIrq( pic, index = 5 , isrtype = 'ISR_CMA' , channel = 1 )
	243	mapping.addIrq( pic, index = 6 , isrtype = 'ISR_CMA' , channel = 2 )
	244	mapping.addIrq( pic, index = 7 , isrtype = 'ISR_CMA' , channel = 3 )
[793]	245
[937]	246	mapping.addIrq( pic, index = 8 , isrtype = 'ISR_BDV' , channel = 0 )
	247
	248	mapping.addIrq( pic, index = 16, isrtype = 'ISR_TTY_RX', channel = 0 )
	249	mapping.addIrq( pic, index = 17, isrtype = 'ISR_TTY_RX', channel = 1 )
	250	mapping.addIrq( pic, index = 18, isrtype = 'ISR_TTY_RX', channel = 2 )
	251	mapping.addIrq( pic, index = 19, isrtype = 'ISR_TTY_RX', channel = 3 )
	252	mapping.addIrq( pic, index = 20, isrtype = 'ISR_TTY_RX', channel = 4 )
	253	mapping.addIrq( pic, index = 21, isrtype = 'ISR_TTY_RX', channel = 5 )
	254	mapping.addIrq( pic, index = 22, isrtype = 'ISR_TTY_RX', channel = 6 )
	255	mapping.addIrq( pic, index = 23, isrtype = 'ISR_TTY_RX', channel = 7 )
	256
	257	###################################
	258	### boot & kernel vsegs mapping
	259	###################################
	260
	261	### global vsegs for preloader & boot_loader are mapped in cluster[0][0]
[820]	262	### => same flags CXW_ / identity mapping / non local / big page
[793]	263
[820]	264	mapping.addGlobal( 'seg_preloader', preloader_vbase, preloader_size,
[819]	265	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	266	identity = True, local = False, big = True )
	267
[793]	268	mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size,
[819]	269	'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM',
	270	identity = True, local = False, big = True )
[793]	271
	272	mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size,
	273	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
[819]	274	identity = True, local = False, big = True )
[793]	275
	276	mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size,
[819]	277	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	278	identity = True, local = False, big = True )
[793]	279
	280	mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size,
[819]	281	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	282	identity = True, local = False, big = True )
[793]	283
[937]	284	### global vseg for RAM-DISK in cluster[0][0]
	285	### identity mapping / non local / big pages
	286	if use_ramdisk:
	287
	288	mapping.addGlobal( 'seg_ramdisk', ramdisk_vbase, ramdisk_size,
	289	'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	290	identity = True, local = True, big = True )
	291
[820]	292	### global vsegs kernel_code, kernel_init : local / big page
[937]	293	### replicated in all clusters containing processors
	294	### same content => same name / same vbase
[819]	295	for x in xrange( x_size ):
[937]	296	for y in xrange( y_size - 1 ):
	297
	298	mapping.addGlobal( 'seg_kernel_code',
	299	kernel_code_vbase, kernel_code_size,
[820]	300	'CXW_', vtype = 'ELF', x = x, y = y, pseg = 'RAM',
	301	binpath = 'build/kernel/kernel.elf',
[819]	302	local = True, big = True )
[793]	303
[937]	304	mapping.addGlobal( 'seg_kernel_init',
	305	kernel_init_vbase, kernel_init_size,
[820]	306	'CXW_', vtype = 'ELF', x = x, y = y, pseg = 'RAM',
[819]	307	binpath = 'build/kernel/kernel.elf',
	308	local = True, big = True )
[793]	309
[820]	310	### global vseg kernel_data: non local / big page
	311	### Only mapped in cluster[0][0]
[937]	312	mapping.addGlobal( 'seg_kernel_data',
	313	kernel_data_vbase, kernel_data_size,
	314	'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM',
	315	binpath = 'build/kernel/kernel.elf',
[825]	316	local = False, big = True )
[793]	317
[937]	318	### Global vsegs kernel_ptab_x_y: non local / big page
	319	### replicated in all clusters containing processors
	320	### different content => name & vbase indexed by (x,y)
[820]	321	for x in xrange( x_size ):
[937]	322	for y in xrange( y_size - 1 ):
	323	offset = ((x << y_width) + y) * kernel_ptab_size
[820]	324
[937]	325	mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y),
	326	kernel_ptab_vbase + offset, kernel_ptab_size,
[820]	327	'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM',
	328	local = False, big = True )
	329
[937]	330	### global vsegs kernel_heap_x_y : non local / big pages
	331	### distributed in all clusters containing processors
	332	### different content => name & vbase indexed by (x,y)
	333	for x in xrange( x_size ):
	334	for y in xrange( y_size - 1 ):
	335	offset = ((x << y_width) + y) * kernel_heap_size
[820]	336
[937]	337	mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y),
	338	kernel_heap_vbase + offset , kernel_heap_size,
	339	'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM',
	340	local = False, big = True )
	341
[820]	342	### global vsegs for external peripherals: non local / big page
[937]	343	### only mapped in cluster_io
[944]	344	mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size,
[937]	345	'__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'BDV',
[820]	346	local = False, big = True )
	347
[944]	348	mapping.addGlobal( 'seg_tty', tty_base, tty_size,
[937]	349	'__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'TTY',
[820]	350	local = False, big = True )
	351
[944]	352	mapping.addGlobal( 'seg_nic', nic_base, nic_size,
[937]	353	'__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'NIC',
	354	local = False, big = True )
	355
[944]	356	mapping.addGlobal( 'seg_cma', cma_base, cma_size,
[937]	357	'__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'CMA',
	358	local = False, big = True )
	359
[944]	360	mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size,
[937]	361	'__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'FBF',
	362	local = False, big = True )
	363
[944]	364	mapping.addGlobal( 'seg_pic', pic_base, pic_size,
[937]	365	'__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'PIC',
	366	local = False, big = True )
	367
[820]	368	### global vsegs for internal peripherals : non local / small pages
[937]	369	### allocated in all clusters containing processors
	370	### name and vbase indexed by (x,y)
[820]	371	for x in xrange( x_size ):
[937]	372	for y in xrange( y_size - 1 ):
[820]	373	offset = ((x << y_width) + y) * peri_increment
	374
[937]	375	mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y),
	376	xcu_base + offset, xcu_size,
[820]	377	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU',
	378	local = False, big = False )
	379
[937]	380	mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y),
	381	mmc_base + offset, mmc_size,
[820]	382	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC',
	383	local = False, big = False )
	384
[939]	385	### global vsegs kernel_sched : non local / small pages
	386	### allocated in all clusters containing processors
	387	### different content => name & vbase indexed by (x,y)
	388	for x in xrange( x_size ):
	389	for y in xrange( y_size - 1 ):
	390	offset = ((x << y_width) + y) * kernel_ptab_size
	391
	392	mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y),
	393	kernel_sched_vbase + offset , kernel_sched_size,
	394	'C_W_', vtype = 'SCHED', x = x, y = y, pseg = 'RAM',
	395	local = False, big = False )
	396
[793]	397	return mapping
	398
[937]	399	########################## platform test #############################################
[793]	400
	401	if __name__ == '__main__':
	402
	403	mapping = arch( x_size = 2,
	404	y_size = 2,
	405	nb_procs = 2 )
	406
	407	# print mapping.netbsd_dts()
	408
	409	print mapping.xml()
	410
	411	# print mapping.giet_vsegs()
	412
	413
	414	# Local Variables:
	415	# tab-width: 4;
	416	# c-basic-offset: 4;
	417	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	418	# indent-tabs-mode: nil;
	419	# End:
	420	#
	421	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	422

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