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source: trunk/platforms/tsar_generic_leti/top.cpp @ 634

Last change on this file since 634 was 630, checked in by alain, 11 years ago
Integrating support for RAMDISK in tsar_generic_leti platform.
File size: 53.2 KB

Rev	Line
[621]	1	/////////////////////////////////////////////////////////////////////////
	2	// File: top.cpp
	3	// Author: Alain Greiner
	4	// Copyright: UPMC/LIP6
[628]	5	// Date : february 2014
[621]	6	// This program is released under the GNU public license
	7	/////////////////////////////////////////////////////////////////////////
	8	// This file define a generic TSAR architecture.
	9	// The processor is a MIPS32 processor wrapped in a GDB server
	10	// (this is defined in the tsar_xbar_cluster).
	11	//
	12	// The seg_reset_base and seg_kcode_base addresses are not constrained
	13	// to be 0xBFC00000 and 0x80000000.
	14	//
[628]	15	// It does not use an external ROM, as the boot code must be (pre)loaded
[621]	16	// in cluster (0,0) memory.
	17	//
	18	// The physical address space is 40 bits.
	19	// The 8 address MSB bits define the cluster index.
	20	//
[628]	21	// The main hardware parameters are the mesh size (X_SIZE / Y_SIZE),
	22	// and the number of ptocessors per cluster (NB_PROCS_MAX).
[621]	23	// The number of clusters cannot be larger than 256.
	24	// The number of processors per cluster cannot be larger than 4.
	25	//
[628]	26	// Each cluster contains:
	27	// - 5 dspin_local_crossbar (local interconnect)
	28	// - 5 dspin_router (global interconnect)
	29	// - up to 4 vci_cc_vcache wrapping a MIPS32 processor
	30	// - 1 vci_mem_cache
	31	// - 1 vci_xicu
	32	// - 1 vci_simple_ram (to model the L3 cache).
[621]	33	//
[628]	34	// Each processor receive 4 consecutive IRQ lines from the local XICU.
	35	// In all clusters, the MEMC IRQ line (signaling a late write error)
	36	// is connected to XICU HWI[8]
[621]	37	//
[628]	38	// The cluster 0 contains two more peripherals:
	39	// - one block device controller, whose IRQ is connected to XICU HWI[9].
	40	// - one single channel TTY controller, whose IRQ is connected to XICU HWI[10].
[621]	41	//
[628]	42	// The cluster internal architecture is defined in file tsar_leti_cluster,
	43	// that must be considered as an extension of this top.cpp file.
[621]	44	//
[628]	45	// Besides the hardware components contained in clusters, external peripherals
	46	// are connected to an external IO bus (implemented as a vci_local_crossbar):
	47	// - one disk controller
	48	// - one multi-channel ethernet controller
	49	// - one multi-channel chained buffer dma controller
	50	// - one multi-channel tty controller
	51	// - one frame buffer controller
	52	// - one 16 channels iopic controller
	53	//
	54	// This IOBUS is connected to the north port of the DIR_CMD
	55	// and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1).
	56	// For all external peripherals, the hardware interrupts (HWI) are
	57	// translated to software interrupts (SWI) by the iopic component:
	58	// - IRQ_MNIC_RX[1:0] connected to IOPIC HWI[1:0]
	59	// - IRQ_MNIC_TX[1:0] connected to IOPIC HWI[3:2]
	60	// - IRQ_CDMA[3:0] connected to IOPIC HWI[7:4]
	61	// - IRQ_BDEV connected to IOPIC HWI[9]
	62	// - IRQ_MTTY[3:0] connected to IOPIC HWI[15:12]
	63	////////////////////////////////////////////////////////////////////////////
	64	// The following parameters must be defined in the hard_config.h file :
[621]	65	// - X_WIDTH : number of bits for x coordinate (must be 4)
	66	// - Y_WIDTH : number of bits for y coordinate (must be 4)
	67	// - X_SIZE : number of clusters in a row
	68	// - Y_SIZE : number of clusters in a column
[628]	69	// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
	70	// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (8 max)
	71	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (16 max)
	72	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
	73	// - USE_EXT_IO : use external peripherals if non zero
[621]	74	//
	75	// Some other hardware parameters are not used when compiling the OS,
[628]	76	// and are only defined in this top.cpp file:
[621]	77	// - XRAM_LATENCY : external ram latency
	78	// - MEMC_WAYS : L2 cache number of ways
	79	// - MEMC_SETS : L2 cache number of sets
[628]	80	// - L1_IWAYS : L1 cache instruction number of ways
	81	// - L1_ISETS : L1 cache instruction number of sets
	82	// - L1_DWAYS : L1 cache data number of ways
	83	// - L1_DSETS : L1 cache data number of sets
[621]	84	// - FBUF_X_SIZE : width of frame buffer (pixels)
	85	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
	86	// - BDEV_IMAGE_NAME : file pathname for block device
	87	// - NIC_RX_NAME : file pathname for NIC received packets
	88	// - NIC_TX_NAME : file pathname for NIC transmited packets
[628]	89	// - NIC_MAC4 : MAC address
	90	// - NIC_MAC2 : MAC address
[621]	91	/////////////////////////////////////////////////////////////////////////
	92	// General policy for 40 bits physical address decoding:
	93	// All physical segments base addresses are multiple of 1 Mbytes
	94	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
	95	// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
	96	// the cluster index, and the LADR bits define the local index:
	97	// \|X_ID\|Y_ID\| LADR \| OFFSET \|
	98	// \| 4 \| 4 \| 8 \| 24 \|
	99	/////////////////////////////////////////////////////////////////////////
	100	// General policy for 14 bits SRCID decoding:
	101	// Each component is identified by (x_id, y_id, l_id) tuple.
	102	// \|X_ID\|Y_ID\| L_ID \|
	103	// \| 4 \| 4 \| 6 \|
	104	/////////////////////////////////////////////////////////////////////////
	105
	106	#include <systemc>
	107	#include <sys/time.h>
	108	#include <iostream>
	109	#include <sstream>
	110	#include <cstdlib>
	111	#include <cstdarg>
	112	#include <stdint.h>
	113
	114	#include "gdbserver.h"
	115	#include "mapping_table.h"
	116	#include "tsar_leti_cluster.h"
[628]	117	#include "vci_local_crossbar.h"
	118	#include "vci_dspin_initiator_wrapper.h"
	119	#include "vci_dspin_target_wrapper.h"
	120	#include "vci_multi_tty.h"
	121	#include "vci_multi_nic.h"
	122	#include "vci_chbuf_dma.h"
	123	#include "vci_block_device_tsar.h"
	124	#include "vci_framebuffer.h"
	125	#include "vci_iopic.h"
[621]	126	#include "alloc_elems.h"
	127
	128	///////////////////////////////////////////////////
	129	// OS
	130	///////////////////////////////////////////////////
	131
	132	#define USE_GIET_VM 0
	133	#define USE_GIET_TSAR 1
	134
	135	#if ( USE_GIET_VM and USE_GIET_TSAR )
	136	#error "Can't use Two different OS"
	137	#endif
	138
	139	#if ( (not USE_GIET_VM) and (not USE_GIET_TSAR) )
	140	#error "You need to specify one OS"
	141	#endif
	142
	143	///////////////////////////////////////////////////
	144	// Parallelisation
	145	///////////////////////////////////////////////////
	146	#define USE_OPENMP 0
	147
	148	#if USE_OPENMP
	149	#include <omp.h>
	150	#endif
	151
	152	///////////////////////////////////////////////////
	153	// cluster index (from x,y coordinates)
	154	///////////////////////////////////////////////////
	155
	156	#define cluster(x,y) (y + (x << Y_WIDTH))
	157
	158	#define min(a, b) (a < b ? a : b)
	159
	160	///////////////////////////////////////////////////////////
	161	// DSPIN parameters
	162	///////////////////////////////////////////////////////////
	163
	164	#define dspin_cmd_width 39
	165	#define dspin_rsp_width 32
	166
	167	///////////////////////////////////////////////////////////
	168	// VCI parameters
	169	///////////////////////////////////////////////////////////
	170
	171	#define vci_cell_width_int 4
	172	#define vci_cell_width_ext 8
	173	#define vci_address_width 40
	174	#define vci_plen_width 8
	175	#define vci_rerror_width 1
	176	#define vci_clen_width 1
	177	#define vci_rflag_width 1
	178	#define vci_srcid_width 14
	179	#define vci_pktid_width 4
	180	#define vci_trdid_width 4
	181	#define vci_wrplen_width 1
	182
	183	////////////////////////////////////////////////////////////
	184	// Main Hardware Parameters values
	185	//////////////////////i/////////////////////////////////////
	186
[628]	187	#include "../../softs/soft_transpose_giet/hard_config.h"
[621]	188
	189	////////////////////////////////////////////////////////////
	190	// Secondary Hardware Parameters
	191	//////////////////////i/////////////////////////////////////
	192
	193	#define RESET_ADDRESS 0x0
	194
	195	#define XRAM_LATENCY 0
	196
	197	#define MEMC_WAYS 16
	198	#define MEMC_SETS 256
	199
	200	#define L1_IWAYS 4
	201	#define L1_ISETS 64
	202
	203	#define L1_DWAYS 4
	204	#define L1_DSETS 64
	205
	206	#define FBUF_X_SIZE 128
	207	#define FBUF_Y_SIZE 128
	208
[628]	209	#define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw"
[621]	210
[628]	211	#define NIC_MAC4 0XBABEF00D
	212	#define NIC_MAC2 0xBEEF
[621]	213	#define NIC_RX_NAME "../../softs/soft_hello_giet/fake"
	214	#define NIC_TX_NAME "../../softs/soft_hello_giet/fake"
	215
	216	#define NORTH 0
	217	#define SOUTH 1
	218	#define EAST 2
	219	#define WEST 3
	220
	221	////////////////////////////////////////////////////////////
	222	// Arguments for the SoCLib loader
	223	//////////////////////i/////////////////////////////////////
	224
[630]	225	#define elf_loader "../../softs/soft_transpose_giet/bin.soft"
	226	#define ramdisk_loader "../../softs/soft_transpose_giet/images.raw@0x00800000:"
[621]	227
	228	////////////////////////////////////////////////////////////
	229	// DEBUG Parameters default values
	230	//////////////////////i/////////////////////////////////////
	231
[628]	232	#define MAX_FROZEN_CYCLES 10000
[621]	233
	234	////////////////////////////////////////////////////////////////////
[628]	235	// LOCAL TGTID & SRCID definition
[621]	236	// For all components: global TGTID = global SRCID = cluster_index
	237	////////////////////////////////////////////////////////////////////
	238
	239	#define MEMC_TGTID 0
	240	#define XICU_TGTID 1
[628]	241	#define MTTY_TGTID 2
	242	#define BDEV_TGTID 3
[621]	243	#define FBUF_TGTID 4
[628]	244	#define MNIC_TGTID 5
	245	#define CDMA_TGTID 6
	246	#define IOPI_TGTID 7
[621]	247
[628]	248	#define BDEV_SRCID NB_PROCS_MAX
	249	#define CDMA_SRCID NB_PROCS_MAX + 1
	250	#define IOPI_SRCID NB_PROCS_MAX + 2
	251
	252	/////////////////////////////////////////////////////////////////////
[621]	253	// Physical segments definition
[628]	254	/////////////////////////////////////////////////////////////////////
	255	// - 3 segments are replicated in all clusters
	256	// - 2 segments are replicated in cluster[0,0] & [X_SIZE-1,Y_SIZE-1]
	257	// - 4 segments are only in cluster [X_SIZE-1,Y_SIZE]
	258	// The following values are for segments in cluster 0,
	259	// and these 32 bits values must be concatenate with the cluster
[621]	260	// index (on 8 bits) to obtain the 40 bits address.
[628]	261	/////////////////////////////////////////////////////////////////////
[621]	262
[628]	263	// in cluster [0,0] & [X_SIZE-1,Y_SIZE]
[621]	264
[628]	265	#define MTTY_BASE 0xF4000000
	266	#define MTTY_SIZE 0x00001000 // 4 Kbytes
[621]	267
[628]	268	#define BDEV_BASE 0xF2000000
[621]	269	#define BDEV_SIZE 0x00001000 // 4 Kbytes
	270
[628]	271	// in cluster [X_SIZE-1,Y_SIZE]
[621]	272
[628]	273	#define FBUF_BASE 0xF3000000
	274	#define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2)
	275
	276	#define MNIC_BASE 0xF7000000
[621]	277	#define MNIC_SIZE 0x00800000 // 512 Kbytes (for 8 channels)
	278
[628]	279	#define CDMA_BASE 0xF8000000
[621]	280	#define CDMA_SIZE 0x00004000 * NB_CMA_CHANNELS
	281
[628]	282	#define IOPI_BASE 0xF9000000
	283	#define IOPI_SIZE 0x00001000 // 4 Kbytes
	284
[621]	285	// replicated segments : address is extended to 40 bits by cluster_xy
	286
	287	#define MEMC_BASE 0x00000000
	288	#define MEMC_SIZE 0x01000000 // 16 Mbytes per cluster
	289
[628]	290	#define MCFG_BASE 0xE0000000
	291	#define MCFG_SIZE 0x00001000 // 4 Kbytes per cluster
	292
[621]	293	#define XICU_BASE 0xF0000000
[628]	294	#define XICU_SIZE 0x00001000 // 4 Kbytes per cluster
[621]	295
	296	bool stop_called = false;
	297
	298	/////////////////////////////////
	299	int _main(int argc, char *argv[])
	300	{
	301	using namespace sc_core;
	302	using namespace soclib::caba;
	303	using namespace soclib::common;
	304
[628]	305	uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
	306	size_t threads = 1; // simulator's threads number
[621]	307	bool trace_ok = false; // trace activated
	308	uint32_t trace_from = 0; // trace start cycle
	309	bool trace_proc_ok = false; // detailed proc trace activated
	310	size_t trace_memc_ok = false; // detailed memc trace activated
	311	size_t trace_memc_id = 0; // index of memc to be traced
	312	size_t trace_proc_id = 0; // index of proc to be traced
	313	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
	314	struct timeval t1,t2;
	315	uint64_t ms1,ms2;
	316
	317	////////////// command line arguments //////////////////////
	318	if (argc > 1)
	319	{
	320	for (int n = 1; n < argc; n = n + 2)
	321	{
	322	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
	323	{
	324	ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
	325	}
	326	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
	327	{
	328	trace_ok = true;
	329	trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
	330	}
	331	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
	332	{
	333	trace_memc_ok = true;
	334	trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
	335	size_t x = trace_memc_id >> Y_WIDTH;
	336	size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
	337
	338	assert( (x <= X_SIZE) and (y <= Y_SIZE) &&
	339	"MEMCID parameter refers a not valid memory cache");
	340	}
	341	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
	342	{
	343	trace_proc_ok = true;
	344	trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
	345	size_t cluster_xy = trace_proc_id / NB_PROCS_MAX ;
	346	size_t x = cluster_xy >> Y_WIDTH;
	347	size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
	348
	349	assert( (x <= X_SIZE) and (y <= Y_SIZE) &&
	350	"PROCID parameter refers a not valid processor");
	351	}
	352	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
	353	{
[628]	354	threads = (size_t) strtol(argv[n + 1], NULL, 0);
	355	threads = (threads < 1) ? 1 : threads;
[621]	356	}
	357	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
	358	{
	359	frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
	360	}
	361	else
	362	{
	363	std::cout << " Arguments are (key,value) couples." << std::endl;
	364	std::cout << " The order is not important." << std::endl;
	365	std::cout << " Accepted arguments are :" << std::endl << std::endl;
	366	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
	367	std::cout << " -DEBUG debug_start_cycle" << std::endl;
	368	std::cout << " -THREADS simulator's threads number" << std::endl;
	369	std::cout << " -FROZEN max_number_of_lines" << std::endl;
	370	std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
	371	std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
	372	std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
	373	exit(0);
	374	}
	375	}
	376	}
	377
	378	// checking hardware parameters
	379	assert( (X_SIZE <= 16) and
	380	"The X_SIZE parameter cannot be larger than 16" );
	381
	382	assert( (Y_SIZE <= 16) and
	383	"The Y_SIZE parameter cannot be larger than 16" );
	384
	385	assert( (NB_PROCS_MAX <= 8) and
[628]	386	"The NB_PROCS_MAX parameter cannot be larger than 4" );
[621]	387
[628]	388	assert( (NB_CMA_CHANNELS <= 4) and
	389	"The NB_CMA_CHANNELS parameter cannot be larger than 4" );
[621]	390
[628]	391	assert( (NB_TTY_CHANNELS <= 4) and
	392	"The NB_TTY_CHANNELS parameter cannot be larger than 4" );
[621]	393
[628]	394	assert( (NB_NIC_CHANNELS <= 2) and
	395	"The NB_NIC_CHANNELS parameter cannot be larger than 2" );
[621]	396
	397	assert( (vci_address_width == 40) and
	398	"VCI address width with the GIET must be 40 bits" );
	399
	400	assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
	401	"ERROR: you must have X_WIDTH == Y_WIDTH == 4");
	402
	403	std::cout << std::endl;
	404
	405	std::cout << " - X_SIZE = " << X_SIZE << std::endl;
	406	std::cout << " - Y_SIZE = " << Y_SIZE << std::endl;
	407	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
	408	std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
	409	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
	410	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
	411	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
	412	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
	413	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
	414	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
	415	std::cout << " - MAX_CYCLES = " << ncycles << std::endl;
	416	std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl;
[630]	417	std::cout << " - SOFT_FILENAME = " << elf_loader << std::endl;
	418	std::cout << " - RAMDISK_FILENAME = " << ramdisk_loader << std::endl;
[621]	419
	420	std::cout << std::endl;
	421
	422	// Internal and External VCI parameters definition
	423	typedef soclib::caba::VciParams<vci_cell_width_int,
	424	vci_plen_width,
	425	vci_address_width,
	426	vci_rerror_width,
	427	vci_clen_width,
	428	vci_rflag_width,
	429	vci_srcid_width,
	430	vci_pktid_width,
	431	vci_trdid_width,
	432	vci_wrplen_width> vci_param_int;
	433
	434	typedef soclib::caba::VciParams<vci_cell_width_ext,
	435	vci_plen_width,
	436	vci_address_width,
	437	vci_rerror_width,
	438	vci_clen_width,
	439	vci_rflag_width,
	440	vci_srcid_width,
	441	vci_pktid_width,
	442	vci_trdid_width,
	443	vci_wrplen_width> vci_param_ext;
	444
	445	#if USE_OPENMP
	446	omp_set_dynamic(false);
[628]	447	omp_set_num_threads(threads);
[621]	448	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
	449	#endif
	450
	451
[628]	452	///////////////////////////////////////
	453	// Direct Network Mapping Table
	454	///////////////////////////////////////
[621]	455
	456	MappingTable maptabd(vci_address_width,
	457	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
	458	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
[628]	459	0x00FF000000ULL);
[621]	460
[628]	461	// replicated segments
[621]	462	for (size_t x = 0; x < X_SIZE; x++)
	463	{
	464	for (size_t y = 0; y < Y_SIZE; y++)
	465	{
	466	sc_uint<vci_address_width> offset;
[628]	467	offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
[621]	468
	469	std::ostringstream si;
	470	si << "seg_xicu_" << x << "_" << y;
	471	maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE,
	472	IntTab(cluster(x,y),XICU_TGTID), false));
	473
	474	std::ostringstream sd;
[628]	475	sd << "seg_mcfg_" << x << "_" << y;
	476	maptabd.add(Segment(sd.str(), MCFG_BASE + offset, MCFG_SIZE,
	477	IntTab(cluster(x,y),MEMC_TGTID), false));
[621]	478
	479	std::ostringstream sh;
	480	sh << "seg_memc_" << x << "_" << y;
	481	maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE,
	482	IntTab(cluster(x,y),MEMC_TGTID), true));
	483	}
	484	}
[628]	485
	486	// segments in cluster(0,0)
	487	maptabd.add(Segment("seg_tty0", MTTY_BASE, MTTY_SIZE,
	488	IntTab(cluster(0,0),MTTY_TGTID), false));
	489
	490	maptabd.add(Segment("seg_ioc0", BDEV_BASE, BDEV_SIZE,
	491	IntTab(cluster(0,0),BDEV_TGTID), false));
	492
	493	// segments in cluster_io (X_SIZE-1,Y_SIZE)
	494	sc_uint<vci_address_width> offset;
	495	offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE)) << 32;
	496
	497	maptabd.add(Segment("seg_mtty", MTTY_BASE + offset, MTTY_SIZE,
	498	IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false));
	499
	500	maptabd.add(Segment("seg_fbuf", FBUF_BASE + offset, FBUF_SIZE,
	501	IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false));
	502
	503	maptabd.add(Segment("seg_bdev", BDEV_BASE + offset, BDEV_SIZE,
	504	IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false));
	505
	506	maptabd.add(Segment("seg_mnic", MNIC_BASE + offset, MNIC_SIZE,
	507	IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false));
	508
	509	maptabd.add(Segment("seg_cdma", CDMA_BASE + offset, CDMA_SIZE,
	510	IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false));
	511
	512	maptabd.add(Segment("seg_iopi", IOPI_BASE + offset, IOPI_SIZE,
	513	IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false));
	514
[621]	515	std::cout << maptabd << std::endl;
	516
[628]	517	/////////////////////////////////////////////////
	518	// Ram network mapping table
	519	/////////////////////////////////////////////////
[621]	520
[628]	521	MappingTable maptabx(vci_address_width,
	522	IntTab(X_WIDTH+Y_WIDTH),
	523	IntTab(X_WIDTH+Y_WIDTH),
	524	0x00FF000000ULL);
[621]	525
[628]	526	for (size_t x = 0; x < X_SIZE; x++)
	527	{
	528	for (size_t y = 0; y < Y_SIZE ; y++)
	529	{
	530	sc_uint<vci_address_width> offset;
	531	offset = (sc_uint<vci_address_width>)cluster(x,y)
	532	<< (vci_address_width-X_WIDTH-Y_WIDTH);
[621]	533
[628]	534	std::ostringstream sh;
	535	sh << "x_seg_memc_" << x << "_" << y;
[621]	536
[628]	537	maptabx.add(Segment(sh.str(), MEMC_BASE + offset,
[621]	538	MEMC_SIZE, IntTab(cluster(x,y)), false));
[628]	539	}
	540	}
	541	std::cout << maptabx << std::endl;
[621]	542
[628]	543	////////////////////
	544	// Signals
	545	///////////////////
[621]	546
[628]	547	sc_clock signal_clk("clk");
	548	sc_signal<bool> signal_resetn("resetn");
[621]	549
[628]	550	// IRQs from external peripherals
	551	sc_signal<bool> signal_irq_bdev;
	552	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
	553	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
	554	sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS];
	555	sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
	556	sc_signal<bool> signal_irq_false;
	557
[621]	558	// Horizontal inter-clusters DSPIN signals
[628]	559	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
	560	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE);
	561	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
	562	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE);
[621]	563
[628]	564	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
	565	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE);
	566	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
	567	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE);
	568
	569	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
	570	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE);
	571	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
	572	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE);
	573
	574	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
	575	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE);
	576	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
	577	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE);
	578
	579	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
	580	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE);
	581	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
	582	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE);
	583
[621]	584	// Vertical inter-clusters DSPIN signals
[628]	585	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
	586	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1);
	587	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
	588	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1);
[621]	589
[628]	590	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
	591	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1);
	592	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
	593	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1);
[621]	594
[628]	595	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
	596	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1);
	597	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
	598	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1);
[621]	599
[628]	600	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
	601	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1);
	602	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
	603	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1);
	604
	605	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
	606	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1);
	607	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
	608	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1);
	609
	610	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
	611	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
	612	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4);
	613	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
	614	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4);
	615
	616	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
	617	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4);
	618	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
	619	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4);
	620
	621	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
	622	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4);
	623	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
	624	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4);
	625
	626	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
	627	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4);
	628	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
	629	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4);
	630
	631	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
	632	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4);
	633	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
	634	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4);
	635
	636	// VCI signals for iobus and peripherals
	637	VciSignals<vci_param_int> signal_vci_ini_bdev("signal_vci_ini_bdev");
	638	VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
	639	VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
	640
	641	VciSignals<vci_param_int>* signal_vci_ini_proc =
	642	alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
	643
	644	VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
	645	VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
	646	VciSignals<vci_param_int> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
	647	VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
	648	VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
	649	VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
	650	VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
	651	VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
	652
	653	VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
	654	VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
	655
[621]	656	////////////////////////////
	657	// Loader
	658	////////////////////////////
	659
[630]	660	soclib::common::Loader loader( elf_loader, ramdisk_loader );
[621]	661
[630]	662	///////////////////////////
	663	// processor iss
	664	///////////////////////////
	665
[621]	666	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
[630]	667	proc_iss::set_loader( loader );
[621]	668
	669	////////////////////////////
	670	// Clusters construction
	671	////////////////////////////
	672
	673	TsarLetiCluster<dspin_cmd_width,
	674	dspin_rsp_width,
	675	vci_param_int,
	676	vci_param_ext>* clusters[X_SIZE][Y_SIZE];
	677
	678	#if USE_OPENMP
	679	#pragma omp parallel
	680	{
	681	#pragma omp for
	682	#endif
	683	for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++)
	684	{
	685	size_t x = i / Y_SIZE;
	686	size_t y = i % Y_SIZE;
	687
	688	#if USE_OPENMP
	689	#pragma omp critical
	690	{
	691	#endif
	692	std::cout << std::endl;
[628]	693	std::cout << "Cluster_" << std::dec << x << "_" << y
	694	<< " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
[621]	695	std::cout << std::endl;
	696
	697	clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
	698	dspin_rsp_width,
	699	vci_param_int,
	700	vci_param_ext>
	701	(
[628]	702	"cluster",
[621]	703	NB_PROCS_MAX,
	704	x,
	705	y,
	706	cluster(x,y),
	707	maptabd,
	708	maptabx,
	709	RESET_ADDRESS,
	710	X_WIDTH,
	711	Y_WIDTH,
	712	vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
	713	MEMC_TGTID,
	714	XICU_TGTID,
	715	MTTY_TGTID,
	716	BDEV_TGTID,
[628]	717	BDEV_IMAGE_NAME,
[621]	718	MEMC_WAYS,
	719	MEMC_SETS,
	720	L1_IWAYS,
	721	L1_ISETS,
	722	L1_DWAYS,
	723	L1_DSETS,
	724	XRAM_LATENCY,
	725	loader,
	726	frozen_cycles,
	727	trace_from,
	728	trace_proc_ok,
	729	trace_proc_id,
	730	trace_memc_ok,
	731	trace_memc_id
	732	);
	733
	734	#if USE_OPENMP
	735	} // end critical
	736	#endif
	737	} // end for
	738	#if USE_OPENMP
	739	}
	740	#endif
	741
[628]	742	//////////////////////////////////////////////////////////////////
	743	// IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE]
	744	//////////////////////////////////////////////////////////////////
[621]	745
[628]	746	size_t cluster_io = cluster(X_SIZE-1, Y_SIZE);
[621]	747
[628]	748	//////////// vci_local_crossbar
	749	VciLocalCrossbar<vci_param_int>*
	750	iobus = new VciLocalCrossbar<vci_param_int>(
	751	"iobus",
	752	maptabd, // mapping table
	753	cluster_io, // cluster_xy
	754	NB_PROCS_MAX + 3, // number of local initiators
	755	8, // number of local targets
	756	BDEV_TGTID ); // default target index
[621]	757
[628]	758	//////////// vci_framebuffer
	759	VciFrameBuffer<vci_param_int>*
	760	fbuf = new VciFrameBuffer<vci_param_int>(
	761	"fbuf",
	762	IntTab(cluster_io, FBUF_TGTID),
	763	maptabd,
	764	FBUF_X_SIZE, FBUF_Y_SIZE );
[621]	765
[628]	766	//////////// vci_block_device
	767	VciBlockDeviceTsar<vci_param_int>*
	768	bdev = new VciBlockDeviceTsar<vci_param_int>(
	769	"bdev",
	770	maptabd,
	771	IntTab(cluster_io, BDEV_SRCID),
	772	IntTab(cluster_io, BDEV_TGTID),
	773	BDEV_IMAGE_NAME,
	774	512, // block size
	775	64 ); // burst size
	776
	777	//////////// vci_multi_nic
	778	VciMultiNic<vci_param_int>*
	779	mnic = new VciMultiNic<vci_param_int>(
	780	"mnic",
	781	IntTab(cluster_io, MNIC_TGTID),
	782	maptabd,
	783	NB_NIC_CHANNELS,
	784	NIC_MAC4,
	785	NIC_MAC2,
	786	NIC_RX_NAME,
	787	NIC_TX_NAME );
	788
	789	///////////// vci_chbuf_dma
	790	VciChbufDma<vci_param_int>*
	791	cdma = new VciChbufDma<vci_param_int>(
	792	"cdma",
	793	maptabd,
	794	IntTab(cluster_io, CDMA_SRCID),
	795	IntTab(cluster_io, CDMA_TGTID),
	796	64, // burst size
	797	NB_CMA_CHANNELS );
	798
	799	////////////// vci_multi_tty
	800	std::vector<std::string> vect_names;
	801	for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
	802	{
	803	std::ostringstream term_name;
	804	term_name << "ext_" << id;
	805	vect_names.push_back(term_name.str().c_str());
	806	}
	807
	808	VciMultiTty<vci_param_int>*
	809	mtty = new VciMultiTty<vci_param_int>(
	810	"mtty",
	811	IntTab(cluster_io, MTTY_TGTID),
	812	maptabd,
	813	vect_names );
	814
	815	///////////// vci_iopic
	816	VciIopic<vci_param_int>*
	817	iopic = new VciIopic<vci_param_int>(
	818	"iopic",
	819	maptabd,
	820	IntTab(cluster_io, IOPI_SRCID),
	821	IntTab(cluster_io, IOPI_TGTID),
	822	16 );
	823
	824	////////////// vci_dspin wrappers
	825	VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	826	wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
	827	"wt_bdev",
	828	vci_srcid_width );
	829
	830	VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	831	wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
	832	"wi_bdev",
	833	vci_srcid_width );
	834
	835	///////////////////////////////////////////////////////////////
	836	// Net-list
	837	///////////////////////////////////////////////////////////////
	838
	839	// iobus
	840	iobus->p_clk (signal_clk);
	841	iobus->p_resetn (signal_resetn);
	842
	843	iobus->p_target_to_up (signal_vci_cmd_from_noc);
	844	iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
	845
	846	iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
	847	iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
	848	iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
	849	iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
	850	iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
	851	iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev);
	852	iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
	853	iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
	854
	855	for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
	856	{
	857	iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
	858	}
	859	iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev);
	860	iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
	861	iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
	862
	863	std::cout << " - IOBUS connected" << std::endl;
	864
	865	// block_device
	866	bdev->p_clk (signal_clk);
	867	bdev->p_resetn (signal_resetn);
	868	bdev->p_vci_target (signal_vci_tgt_bdev);
	869	bdev->p_vci_initiator (signal_vci_ini_bdev);
	870	bdev->p_irq (signal_irq_bdev);
	871
	872	std::cout << " - BDEV connected" << std::endl;
	873
	874	// frame_buffer
	875	fbuf->p_clk (signal_clk);
	876	fbuf->p_resetn (signal_resetn);
	877	fbuf->p_vci (signal_vci_tgt_fbuf);
	878
	879	std::cout << " - FBUF connected" << std::endl;
	880
	881	// multi_nic
	882	mnic->p_clk (signal_clk);
	883	mnic->p_resetn (signal_resetn);
	884	mnic->p_vci (signal_vci_tgt_mnic);
	885	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
	886	{
	887	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
	888	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
	889	}
	890
	891	std::cout << " - MNIC connected" << std::endl;
	892
	893	// chbuf_dma
	894	cdma->p_clk (signal_clk);
	895	cdma->p_resetn (signal_resetn);
	896	cdma->p_vci_target (signal_vci_tgt_cdma);
	897	cdma->p_vci_initiator (signal_vci_ini_cdma);
	898	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
	899	{
	900	cdma->p_irq[i] (signal_irq_cdma[i]);
	901	}
	902
	903	std::cout << " - CDMA connected" << std::endl;
	904
	905	// multi_tty
	906	mtty->p_clk (signal_clk);
	907	mtty->p_resetn (signal_resetn);
	908	mtty->p_vci (signal_vci_tgt_mtty);
	909	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
	910	{
	911	mtty->p_irq[i] (signal_irq_mtty[i]);
	912	}
	913
	914	std::cout << " - MTTY connected" << std::endl;
	915
	916	// iopic
	917	iopic->p_clk (signal_clk);
	918	iopic->p_resetn (signal_resetn);
	919	iopic->p_vci_target (signal_vci_tgt_iopi);
	920	iopic->p_vci_initiator (signal_vci_ini_iopi);
	921	for ( size_t i=0 ; i<16 ; i++)
	922	{
	923	if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
	924	else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
	925	else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
	926	else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
	927	else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
	928	else if(i < 9) iopic->p_hwi[i] (signal_irq_false);
	929	else if(i == 9) iopic->p_hwi[i] (signal_irq_bdev);
	930	else if(i < 12) iopic->p_hwi[i] (signal_irq_false);
	931	else if(i < 12+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty[i-12]);
	932	else iopic->p_hwi[i] (signal_irq_false);
	933	}
	934
	935	// vci/dspin wrappers
	936	wi_iobus->p_clk (signal_clk);
	937	wi_iobus->p_resetn (signal_resetn);
	938	wi_iobus->p_vci (signal_vci_cmd_to_noc);
	939	wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]);
	940	wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]);
	941
	942	// vci/dspin wrappers
	943	wt_iobus->p_clk (signal_clk);
	944	wt_iobus->p_resetn (signal_resetn);
	945	wt_iobus->p_vci (signal_vci_cmd_from_noc);
	946	wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]);
	947	wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]);
	948
	949	// Clock & RESET for clusters
	950	for (size_t x = 0; x < (X_SIZE); x++)
	951	{
	952	for (size_t y = 0; y < Y_SIZE; y++)
	953	{
	954	clusters[x][y]->p_clk (signal_clk);
	955	clusters[x][y]->p_resetn (signal_resetn);
	956	}
	957	}
	958
	959	// Inter Clusters horizontal connections
	960	if (X_SIZE > 1)
	961	{
	962	for (size_t x = 0; x < (X_SIZE-1); x++)
	963	{
	964	for (size_t y = 0; y < Y_SIZE; y++)
	965	{
	966	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
	967	clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
	968	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
	969	clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
	970
	971	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
	972	clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
	973	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
	974	clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
	975
	976	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
	977	clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
	978	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
	979	clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
	980
	981	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
	982	clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
	983	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
	984	clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
	985
	986	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
	987	clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
	988	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
	989	clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
[621]	990	}
[628]	991	}
	992	}
	993	std::cout << std::endl << "Horizontal connections done" << std::endl;
[621]	994
[628]	995	// Inter Clusters vertical connections
	996	if (Y_SIZE > 1)
	997	{
	998	for (size_t y = 0; y < (Y_SIZE-1); y++)
	999	{
	1000	for (size_t x = 0; x < X_SIZE; x++)
	1001	{
	1002	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
	1003	clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
	1004	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
	1005	clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
	1006
	1007	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
	1008	clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
	1009	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
	1010	clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
	1011
	1012	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
	1013	clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
	1014	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
	1015	clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
	1016
	1017	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
	1018	clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
	1019	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
	1020	clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
	1021
	1022	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
	1023	clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
	1024	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
	1025	clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
[621]	1026	}
[628]	1027	}
	1028	}
	1029	std::cout << std::endl << "Vertical connections done" << std::endl;
[621]	1030
[628]	1031	// East & West boundary cluster connections
	1032	for (size_t y = 0; y < Y_SIZE; y++)
	1033	{
	1034	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
	1035	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
	1036	clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]);
	1037	clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]);
[621]	1038
[628]	1039	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
	1040	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
	1041	clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]);
	1042	clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]);
[621]	1043
[628]	1044	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
	1045	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
	1046	clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]);
	1047	clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]);
[621]	1048
[628]	1049	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
	1050	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
	1051	clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]);
	1052	clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]);
[621]	1053
[628]	1054	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
	1055	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
	1056	clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]);
	1057	clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]);
	1058	}
[621]	1059
[628]	1060	// North & South boundary clusters connections
	1061	for (size_t x = 0; x < X_SIZE; x++)
	1062	{
	1063	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
	1064	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
	1065	clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);
	1066	clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);
[621]	1067
[628]	1068	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
	1069	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
	1070	clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);
	1071	clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);
[621]	1072
[628]	1073	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
	1074	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
	1075	clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);
	1076	clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);
[621]	1077
[628]	1078	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
	1079	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
	1080	clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);
	1081	clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);
	1082
	1083	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
	1084	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
	1085	clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]);
	1086	clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]);
	1087	}
	1088
	1089	std::cout << std::endl << "North, South, West, East connections done" << std::endl;
	1090	std::cout << std::endl;
	1091
	1092	////////////////////////////////////////////////////////
	1093	// Simulation
	1094	///////////////////////////////////////////////////////
	1095
	1096	sc_start(sc_core::sc_time(0, SC_NS));
	1097	signal_resetn = false;
	1098	signal_irq_false = false;
	1099
	1100	// set network boundaries signals default values
	1101	// for all boundary clusters but the IO cluster
	1102	for (size_t x = 0; x < X_SIZE ; x++)
	1103	{
	1104	for (size_t y = 0; y < Y_SIZE ; y++)
	1105	{
	1106	for (size_t face = 0; face < 4; face++)
	1107	{
	1108	if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) )
	1109	{
	1110	signal_dspin_bound_cmd_in [x][y][face].write = false;
	1111	signal_dspin_bound_cmd_in [x][y][face].read = true;
	1112	signal_dspin_bound_cmd_out[x][y][face].write = false;
	1113	signal_dspin_bound_cmd_out[x][y][face].read = true;
	1114
	1115	signal_dspin_bound_rsp_in [x][y][face].write = false;
	1116	signal_dspin_bound_rsp_in [x][y][face].read = true;
	1117	signal_dspin_bound_rsp_out[x][y][face].write = false;
	1118	signal_dspin_bound_rsp_out[x][y][face].read = true;
	1119	}
	1120
	1121	signal_dspin_bound_m2p_in [x][y][face].write = false;
	1122	signal_dspin_bound_m2p_in [x][y][face].read = true;
	1123	signal_dspin_bound_m2p_out[x][y][face].write = false;
	1124	signal_dspin_bound_m2p_out[x][y][face].read = true;
	1125
	1126	signal_dspin_bound_p2m_in [x][y][face].write = false;
	1127	signal_dspin_bound_p2m_in [x][y][face].read = true;
	1128	signal_dspin_bound_p2m_out[x][y][face].write = false;
	1129	signal_dspin_bound_p2m_out[x][y][face].read = true;
	1130
	1131	signal_dspin_bound_cla_in [x][y][face].write = false;
	1132	signal_dspin_bound_cla_in [x][y][face].read = true;
	1133	signal_dspin_bound_cla_out[x][y][face].write = false;
	1134	signal_dspin_bound_cla_out[x][y][face].read = true;
[621]	1135	}
[628]	1136	}
	1137	}
[621]	1138
[628]	1139	sc_start(sc_core::sc_time(1, SC_NS));
	1140	signal_resetn = true;
[621]	1141
[628]	1142	if (gettimeofday(&t1, NULL) != 0)
	1143	{
	1144	perror("gettimeofday");
	1145	return EXIT_FAILURE;
	1146	}
[621]	1147
	1148	for (uint64_t n = 1; n < ncycles && !stop_called; n++)
	1149	{
	1150	// Monitor a specific address for L1 & L2 caches
[628]	1151	// clusters[0][0]->proc[0]->cache_monitor(0x0000010000ULL);
	1152	// clusters[0][0]->memc->cache_monitor(0x0000030000ULL);
[621]	1153
	1154	if( (n % 5000000) == 0)
	1155	{
	1156
	1157	if (gettimeofday(&t2, NULL) != 0)
	1158	{
	1159	perror("gettimeofday");
	1160	return EXIT_FAILURE;
	1161	}
	1162
	1163	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
	1164	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
	1165	std::cerr << "platform clock frequency "
	1166	<< (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
	1167
	1168	if (gettimeofday(&t1, NULL) != 0)
	1169	{
	1170	perror("gettimeofday");
	1171	return EXIT_FAILURE;
	1172	}
	1173	}
	1174
	1175	if ( trace_ok and (n > trace_from) )
	1176	{
	1177	std::cout << "****************** cycle " << std::dec << n ;
	1178	std::cout << " ************************************************" << std::endl;
	1179
	1180	// trace proc[trace_proc_id]
	1181	size_t l = trace_proc_id % NB_PROCS_MAX ;
	1182	size_t x = (trace_proc_id / NB_PROCS_MAX) >> Y_WIDTH ;
	1183	size_t y = (trace_proc_id / NB_PROCS_MAX) & ((1<<Y_WIDTH) - 1);
	1184
	1185	std::ostringstream proc_signame;
	1186	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
[628]	1187	std::ostringstream xicu_signame;
	1188	xicu_signame << "[SIG]XICU_" << x << "_" << y ;
[621]	1189
[628]	1190	clusters[x][y]->proc[l]->print_trace(0x1);
[621]	1191	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
	1192
[628]	1193	clusters[x][y]->xicu->print_trace(0);
	1194	clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
	1195
	1196	if ( clusters[x][y]->signal_proc_irq[0].read() )
	1197	std::cout << " IRQ_PROC active in cluster " << cluster(x,y) << std::endl;
	1198
	1199	if ( signal_irq_bdev.read() )
	1200	std::cout << " IRQ_BDEV in cluster_io active" << std::endl;
	1201
	1202	// trace memc[trace_memc_id] and xram[trace_memc_id]
[621]	1203	x = trace_memc_id >> Y_WIDTH;
	1204	y = trace_memc_id & ((1<<Y_WIDTH) - 1);
	1205
	1206	std::ostringstream smemc;
	1207	smemc << "[SIG]MEMC_" << x << "_" << y;
	1208	std::ostringstream sxram;
	1209	sxram << "[SIG]XRAM_" << x << "_" << y;
	1210
	1211	clusters[x][y]->memc->print_trace();
	1212	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
	1213	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
	1214
[628]	1215	// trace coherence signals
	1216	// clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
	1217	// clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
	1218	// clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
	1219	// clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
	1220
	1221	// clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
	1222	// clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
	1223	// clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
	1224	// clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
	1225
	1226	// trace xbar(s) m2p
	1227	// clusters[0][0]->xbar_m2p->print_trace();
	1228	// clusters[1][0]->xbar_m2p->print_trace();
	1229	// clusters[0][1]->xbar_m2p->print_trace();
	1230	// clusters[1][1]->xbar_m2p->print_trace();
[621]	1231
[628]	1232	// trace router(s) m2p
	1233	// clusters[0][0]->router_m2p->print_trace();
	1234	// clusters[1][0]->router_m2p->print_trace();
	1235	// clusters[0][1]->router_m2p->print_trace();
	1236	// clusters[1][1]->router_m2p->print_trace();
	1237
[621]	1238	// trace external peripherals
[628]	1239	bdev->print_trace();
	1240	signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
	1241	signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
[621]	1242
[628]	1243	iopic->print_trace();
	1244	signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
	1245	signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
[621]	1246
[628]	1247	clusters[0][0]->mtty->print_trace();
	1248	clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY");
	1249	} // end trace
	1250
[621]	1251	sc_start(sc_core::sc_time(1, SC_NS));
	1252	}
	1253
	1254
	1255	// Free memory
	1256	for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++)
	1257	{
	1258	size_t x = i / Y_SIZE;
	1259	size_t y = i % Y_SIZE;
	1260	delete clusters[x][y];
	1261	}
	1262
	1263	return EXIT_SUCCESS;
	1264	}
	1265
	1266
[628]	1267	void handler(int dummy = 0)
	1268	{
[621]	1269	stop_called = true;
	1270	sc_stop();
	1271	}
	1272
	1273	void voidhandler(int dummy = 0) {}
	1274
	1275	int sc_main (int argc, char *argv[])
	1276	{
	1277	signal(SIGINT, handler);
	1278	signal(SIGPIPE, voidhandler);
	1279
	1280	try {
	1281	return _main(argc, argv);
	1282	} catch (std::exception &e) {
	1283	std::cout << e.what() << std::endl;
	1284	} catch (...) {
	1285	std::cout << "Unknown exception occured" << std::endl;
	1286	throw;
	1287	}
	1288	return 1;
	1289	}
	1290
	1291
	1292	// Local Variables:
	1293	// tab-width: 3
	1294	// c-basic-offset: 3
	1295	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	1296	// indent-tabs-mode: nil
	1297	// End:
	1298
	1299	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
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