Changeset 628 for trunk/platforms/tsar_generic_leti/top.cpp
- Timestamp:
- Feb 12, 2014, 9:43:49 AM (11 years ago)
- File:
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- 1 edited
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trunk/platforms/tsar_generic_leti/top.cpp (modified) (29 diffs)
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trunk/platforms/tsar_generic_leti/top.cpp
r621 r628 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 // Date : may 20135 // Date : february 2014 6 6 // This program is released under the GNU public license 7 7 ///////////////////////////////////////////////////////////////////////// … … 13 13 // to be 0xBFC00000 and 0x80000000. 14 14 // 15 // It does not use an external ROM, as the boot code is stored15 // It does not use an external ROM, as the boot code must be (pre)loaded 16 16 // in cluster (0,0) memory. 17 17 // … … 19 19 // The 8 address MSB bits define the cluster index. 20 20 // 21 // The main hardware parameters are the mesh size (X_SIZE / Y_SIZE), 22 // and the number of ptocessors per cluster (NB_PROCS_MAX). 21 23 // The number of clusters cannot be larger than 256. 22 24 // The number of processors per cluster cannot be larger than 4. 23 25 // 24 // - It uses four dspin_local_crossbar per cluster as local interconnect25 // - It uses two virtual_dspin routers per cluster as global interconnect26 // - It uses the vci_cc_vcache_wrapper27 // - It uses the vci_mem_cache28 // - It contains one vci_xicu per cluster.29 // - It contains one vci_multi_dma per cluster.30 // - It contains one vci_simple_ram per cluster to model the L3 cache.26 // Each cluster contains: 27 // - 5 dspin_local_crossbar (local interconnect) 28 // - 5 dspin_router (global interconnect) 29 // - up to 4 vci_cc_vcache wrapping a MIPS32 processor 30 // - 1 vci_mem_cache 31 // - 1 vci_xicu 32 // - 1 vci_simple_ram (to model the L3 cache). 31 33 // 32 // The communication between the MemCache and the Xram is 64 bits. 34 // Each processor receive 4 consecutive IRQ lines from the local XICU. 35 // In all clusters, the MEMC IRQ line (signaling a late write error) 36 // is connected to XICU HWI[8] 33 37 // 34 // All clusters are identical, but the cluster 0 (called io_cluster), 35 // contains 6 extra components: 36 // - the disk controller (BDEV) 37 // - the multi-channel network controller (MNIC) 38 // - the multi-channel chained buffer dma controller (CDMA) 39 // - the multi-channel tty controller (MTTY) 40 // - the frame buffer controller (FBUF) 38 // The cluster 0 contains two more peripherals: 39 // - one block device controller, whose IRQ is connected to XICU HWI[9]. 40 // - one single channel TTY controller, whose IRQ is connected to XICU HWI[10]. 41 41 // 42 // It is build with one single component implementing acluster,43 // defined in files tsar_leti_cluster.* (with * = cpp, h, sd)42 // The cluster internal architecture is defined in file tsar_leti_cluster, 43 // that must be considered as an extension of this top.cpp file. 44 44 // 45 // The IRQs are connected to XICUs as follow: 46 // - The BDEV IRQ is connected to IRQ_IN[0] in I/O cluster. 47 // - The IRQ_IN[1] to IRQ_IN[7] ports are not used in all clusters. 48 // - The DMA IRQs are connected to IRQ_IN[8:11] in all clusters. 49 // - The MEMC IRQ is connected to IRQ_IN[12] in all clusters. 50 // - The TTY IRQs are connected to IRQ_IN[16:31] in I/O cluster. 51 // 52 // Some hardware parameters are used when compiling the OS, and are used 53 // by this top.cpp file. They must be defined in the hard_config.h file : 45 // Besides the hardware components contained in clusters, external peripherals 46 // are connected to an external IO bus (implemented as a vci_local_crossbar): 47 // - one disk controller 48 // - one multi-channel ethernet controller 49 // - one multi-channel chained buffer dma controller 50 // - one multi-channel tty controller 51 // - one frame buffer controller 52 // - one 16 channels iopic controller 53 // 54 // This IOBUS is connected to the north port of the DIR_CMD 55 // and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1). 56 // For all external peripherals, the hardware interrupts (HWI) are 57 // translated to software interrupts (SWI) by the iopic component: 58 // - IRQ_MNIC_RX[1:0] connected to IOPIC HWI[1:0] 59 // - IRQ_MNIC_TX[1:0] connected to IOPIC HWI[3:2] 60 // - IRQ_CDMA[3:0] connected to IOPIC HWI[7:4] 61 // - IRQ_BDEV connected to IOPIC HWI[9] 62 // - IRQ_MTTY[3:0] connected to IOPIC HWI[15:12] 63 //////////////////////////////////////////////////////////////////////////// 64 // The following parameters must be defined in the hard_config.h file : 54 65 // - X_WIDTH : number of bits for x coordinate (must be 4) 55 66 // - Y_WIDTH : number of bits for y coordinate (must be 4) 56 67 // - X_SIZE : number of clusters in a row 57 68 // - Y_SIZE : number of clusters in a column 58 // - NB_PROCS_MAX : number of processors per cluster (power of 2) 59 // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) 60 // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 17) 61 // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) 69 // - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4) 70 // - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (8 max) 71 // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (16 max) 72 // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max) 73 // - USE_EXT_IO : use external peripherals if non zero 62 74 // 63 75 // Some other hardware parameters are not used when compiling the OS, 64 // and can be directly defined in this top.cpp file:76 // and are only defined in this top.cpp file: 65 77 // - XRAM_LATENCY : external ram latency 66 78 // - MEMC_WAYS : L2 cache number of ways 67 79 // - MEMC_SETS : L2 cache number of sets 68 // - L1_IWAYS 69 // - L1_ISETS 70 // - L1_DWAYS 71 // - L1_DSETS 80 // - L1_IWAYS : L1 cache instruction number of ways 81 // - L1_ISETS : L1 cache instruction number of sets 82 // - L1_DWAYS : L1 cache data number of ways 83 // - L1_DSETS : L1 cache data number of sets 72 84 // - FBUF_X_SIZE : width of frame buffer (pixels) 73 85 // - FBUF_Y_SIZE : heigth of frame buffer (lines) 74 // - BDEV_SECTOR_SIZE : block size for block drvice75 86 // - BDEV_IMAGE_NAME : file pathname for block device 76 87 // - NIC_RX_NAME : file pathname for NIC received packets 77 88 // - NIC_TX_NAME : file pathname for NIC transmited packets 78 // - NIC_TIMEOUT : max number of cycles before closing a container 89 // - NIC_MAC4 : MAC address 90 // - NIC_MAC2 : MAC address 79 91 ///////////////////////////////////////////////////////////////////////// 80 92 // General policy for 40 bits physical address decoding: … … 103 115 #include "mapping_table.h" 104 116 #include "tsar_leti_cluster.h" 117 #include "vci_local_crossbar.h" 118 #include "vci_dspin_initiator_wrapper.h" 119 #include "vci_dspin_target_wrapper.h" 120 #include "vci_multi_tty.h" 121 #include "vci_multi_nic.h" 122 #include "vci_chbuf_dma.h" 123 #include "vci_block_device_tsar.h" 124 #include "vci_framebuffer.h" 125 #include "vci_iopic.h" 105 126 #include "alloc_elems.h" 106 127 … … 150 171 #define vci_cell_width_int 4 151 172 #define vci_cell_width_ext 8 152 153 #if USE_ALMOS154 #define vci_address_width 32155 #endif156 157 #if (USE_GIET_VM or USE_GIET_TSAR)158 173 #define vci_address_width 40 159 #endif160 161 174 #define vci_plen_width 8 162 175 #define vci_rerror_width 1 … … 177 190 178 191 #if USE_GIET_TSAR 179 #include "../../softs/soft_ hello_giet/hard_config.h"192 #include "../../softs/soft_transpose_giet/hard_config.h" 180 193 #endif 181 182 194 183 195 //////////////////////////////////////////////////////////// … … 201 213 #define FBUF_Y_SIZE 128 202 214 203 #define BDEV_ SECTOR_SIZE 512204 #define BDEV_IMAGE_NAME "../../softs/soft_hello_giet/fake" 205 206 #define NIC_ TIMEOUT 10000215 #define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw" 216 217 #define NIC_MAC4 0XBABEF00D 218 #define NIC_MAC2 0xBEEF 207 219 #define NIC_RX_NAME "../../softs/soft_hello_giet/fake" 208 220 #define NIC_TX_NAME "../../softs/soft_hello_giet/fake" … … 222 234 223 235 #if USE_GIET_TSAR 224 #define loader_args "../../softs/soft_ hello_giet/bin.soft"236 #define loader_args "../../softs/soft_transpose_giet/bin.soft" 225 237 #endif 226 238 … … 229 241 //////////////////////i///////////////////////////////////// 230 242 231 #define MAX_FROZEN_CYCLES 10000 00243 #define MAX_FROZEN_CYCLES 10000 232 244 233 245 //////////////////////////////////////////////////////////////////// 234 // TGTID definition in direct space246 // LOCAL TGTID & SRCID definition 235 247 // For all components: global TGTID = global SRCID = cluster_index 236 248 //////////////////////////////////////////////////////////////////// … … 238 250 #define MEMC_TGTID 0 239 251 #define XICU_TGTID 1 240 #define M DMA_TGTID 2241 #define MTTY_TGTID 3252 #define MTTY_TGTID 2 253 #define BDEV_TGTID 3 242 254 #define FBUF_TGTID 4 243 #define BDEV_TGTID 5 244 #define MNIC_TGTID 6 245 #define CDMA_TGTID 7 246 #define SIMH_TGTID 8 247 248 /////////////////////////////////////////////////////////////// 255 #define MNIC_TGTID 5 256 #define CDMA_TGTID 6 257 #define IOPI_TGTID 7 258 259 #define BDEV_SRCID NB_PROCS_MAX 260 #define CDMA_SRCID NB_PROCS_MAX + 1 261 #define IOPI_SRCID NB_PROCS_MAX + 2 262 263 ///////////////////////////////////////////////////////////////////// 249 264 // Physical segments definition 250 /////////////////////////////////////////////////////////////// 251 // There is 4 segments replicated in all clusters, 252 // and 5 specific segments in cluster 0 (IO cluster) 253 // The following values are for segments in cluster 0. 254 // These 32 bits values must be concatenate with the cluster 265 ///////////////////////////////////////////////////////////////////// 266 // - 3 segments are replicated in all clusters 267 // - 2 segments are replicated in cluster[0,0] & [X_SIZE-1,Y_SIZE-1] 268 // - 4 segments are only in cluster [X_SIZE-1,Y_SIZE] 269 // The following values are for segments in cluster 0, 270 // and these 32 bits values must be concatenate with the cluster 255 271 // index (on 8 bits) to obtain the 40 bits address. 256 /////////////////////////////////////////////////////////////// 257 258 // non replicated segments / only in cluster(0,0) 272 ///////////////////////////////////////////////////////////////////// 273 274 // in cluster [0,0] & [X_SIZE-1,Y_SIZE] 275 276 #define MTTY_BASE 0xF4000000 277 #define MTTY_SIZE 0x00001000 // 4 Kbytes 278 279 #define BDEV_BASE 0xF2000000 280 #define BDEV_SIZE 0x00001000 // 4 Kbytes 281 282 // in cluster [X_SIZE-1,Y_SIZE] 259 283 260 284 #define FBUF_BASE 0xF3000000 261 285 #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) 262 286 263 #define BDEV_BASE 0xF4000000 264 #define BDEV_SIZE 0x00001000 // 4 Kbytes 265 266 #define MTTY_BASE 0xF2000000 267 #define MTTY_SIZE 0x00001000 // 4 Kbytes 268 269 #define MNIC_BASE 0xF5000000 287 #define MNIC_BASE 0xF7000000 270 288 #define MNIC_SIZE 0x00800000 // 512 Kbytes (for 8 channels) 271 289 272 #define CDMA_BASE 0xF 6000000290 #define CDMA_BASE 0xF8000000 273 291 #define CDMA_SIZE 0x00004000 * NB_CMA_CHANNELS 274 292 293 #define IOPI_BASE 0xF9000000 294 #define IOPI_SIZE 0x00001000 // 4 Kbytes 295 275 296 // replicated segments : address is extended to 40 bits by cluster_xy 276 297 … … 278 299 #define MEMC_SIZE 0x01000000 // 16 Mbytes per cluster 279 300 301 #define MCFG_BASE 0xE0000000 302 #define MCFG_SIZE 0x00001000 // 4 Kbytes per cluster 303 280 304 #define XICU_BASE 0xF0000000 281 #define XICU_SIZE 0x00001000 // 4 Kbytes 282 283 #define MDMA_BASE 0xF1000000 284 #define MDMA_SIZE 0x00001000 * NB_DMA_CHANNELS // 4 Kbytes per channel 285 286 #define SIMH_BASE 0xFF000000 287 #define SIMH_SIZE 0x00001000 // 4 Kbytes 305 #define XICU_SIZE 0x00001000 // 4 Kbytes per cluster 288 306 289 307 bool stop_called = false; … … 296 314 using namespace soclib::common; 297 315 298 uint64_t ncycles = 0xFFFFFFFFFFFFFFFF; // simulated cycles 299 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image 300 char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file 301 char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file 302 size_t threads_nr = 1; // simulator's threads number 316 uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles 317 size_t threads = 1; // simulator's threads number 303 318 bool trace_ok = false; // trace activated 304 319 uint32_t trace_from = 0; // trace start cycle … … 319 334 { 320 335 ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0); 321 }322 else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc))323 {324 strcpy(disk_name, argv[n + 1]);325 336 } 326 337 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) … … 352 363 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) 353 364 { 354 threads _nr = (ssize_t) strtol(argv[n + 1], NULL, 0);355 threads _nr = (threads_nr < 1) ? 1 : threads_nr;365 threads = (size_t) strtol(argv[n + 1], NULL, 0); 366 threads = (threads < 1) ? 1 : threads; 356 367 } 357 368 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) … … 364 375 std::cout << " The order is not important." << std::endl; 365 376 std::cout << " Accepted arguments are :" << std::endl << std::endl; 366 std::cout << " -DISK pathname_for_disk_image" << std::endl;367 377 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; 368 378 std::cout << " -DEBUG debug_start_cycle" << std::endl; … … 385 395 386 396 assert( (NB_PROCS_MAX <= 8) and 387 "The NB_PROCS_MAX parameter cannot be larger than 8" );388 389 assert( (NB_ DMA_CHANNELS < 9) and390 "The NB_ DMA_CHANNELS parameter cannot be larger than 8" );391 392 assert( (NB_TTY_CHANNELS <= 16) and393 "The NB_TTY_CHANNELS parameter cannot be larger than 16" );394 395 assert( (NB_NIC_CHANNELS < 9) and396 "The NB_NIC_CHANNELS parameter cannot be larger than 8" );397 "The NB_PROCS_MAX parameter cannot be larger than 4" ); 398 399 assert( (NB_CMA_CHANNELS <= 4) and 400 "The NB_CMA_CHANNELS parameter cannot be larger than 4" ); 401 402 assert( (NB_TTY_CHANNELS <= 4) and 403 "The NB_TTY_CHANNELS parameter cannot be larger than 4" ); 404 405 assert( (NB_NIC_CHANNELS <= 2) and 406 "The NB_NIC_CHANNELS parameter cannot be larger than 2" ); 397 407 398 408 assert( (vci_address_width == 40) and … … 416 426 std::cout << " - MAX_CYCLES = " << ncycles << std::endl; 417 427 std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl; 428 std::cout << " - SOFT_FILENAME = " << loader_args << std::endl; 418 429 419 430 std::cout << std::endl; … … 444 455 #if USE_OPENMP 445 456 omp_set_dynamic(false); 446 omp_set_num_threads(threads _nr);457 omp_set_num_threads(threads); 447 458 std::cerr << "Built with openmp version " << _OPENMP << std::endl; 448 459 #endif 449 460 450 461 451 ///////////////////// 452 // Mapping Tables 453 ///////////////////// 454 455 // internal network 462 /////////////////////////////////////// 463 // Direct Network Mapping Table 464 /////////////////////////////////////// 465 456 466 MappingTable maptabd(vci_address_width, 457 467 IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), 458 468 IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), 459 0xFF800000); 460 469 0x00FF000000ULL); 470 471 // replicated segments 461 472 for (size_t x = 0; x < X_SIZE; x++) 462 473 { … … 464 475 { 465 476 sc_uint<vci_address_width> offset; 466 offset = (sc_uint<vci_address_width>)cluster(x,y) 467 << (vci_address_width-X_WIDTH-Y_WIDTH); 477 offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32; 468 478 469 479 std::ostringstream si; … … 473 483 474 484 std::ostringstream sd; 475 sd << "seg_m dma_" << x << "_" << y;476 maptabd.add(Segment(sd.str(), M DMA_BASE + offset, MDMA_SIZE,477 IntTab(cluster(x,y),M DMA_TGTID), false));485 sd << "seg_mcfg_" << x << "_" << y; 486 maptabd.add(Segment(sd.str(), MCFG_BASE + offset, MCFG_SIZE, 487 IntTab(cluster(x,y),MEMC_TGTID), false)); 478 488 479 489 std::ostringstream sh; … … 481 491 maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE, 482 492 IntTab(cluster(x,y),MEMC_TGTID), true)); 483 484 if ( cluster(x,y) == 0 )485 {486 maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE,487 IntTab(cluster(x,y),MTTY_TGTID), false));488 maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE,489 IntTab(cluster(x,y),FBUF_TGTID), false));490 maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE,491 IntTab(cluster(x,y),BDEV_TGTID), false));492 maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE,493 IntTab(cluster(x,y),MNIC_TGTID), false));494 maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE,495 IntTab(cluster(x,y),CDMA_TGTID), false));496 maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE,497 IntTab(cluster(x,y),SIMH_TGTID), false));498 }499 493 } 500 494 } 495 496 // segments in cluster(0,0) 497 maptabd.add(Segment("seg_tty0", MTTY_BASE, MTTY_SIZE, 498 IntTab(cluster(0,0),MTTY_TGTID), false)); 499 500 maptabd.add(Segment("seg_ioc0", BDEV_BASE, BDEV_SIZE, 501 IntTab(cluster(0,0),BDEV_TGTID), false)); 502 503 // segments in cluster_io (X_SIZE-1,Y_SIZE) 504 sc_uint<vci_address_width> offset; 505 offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE)) << 32; 506 507 maptabd.add(Segment("seg_mtty", MTTY_BASE + offset, MTTY_SIZE, 508 IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false)); 509 510 maptabd.add(Segment("seg_fbuf", FBUF_BASE + offset, FBUF_SIZE, 511 IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false)); 512 513 maptabd.add(Segment("seg_bdev", BDEV_BASE + offset, BDEV_SIZE, 514 IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false)); 515 516 maptabd.add(Segment("seg_mnic", MNIC_BASE + offset, MNIC_SIZE, 517 IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false)); 518 519 maptabd.add(Segment("seg_cdma", CDMA_BASE + offset, CDMA_SIZE, 520 IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false)); 521 522 maptabd.add(Segment("seg_iopi", IOPI_BASE + offset, IOPI_SIZE, 523 IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false)); 524 501 525 std::cout << maptabd << std::endl; 502 526 503 // external network 504 MappingTable maptabx(vci_address_width, 505 IntTab(X_WIDTH+Y_WIDTH), 506 IntTab(X_WIDTH+Y_WIDTH), 507 0xFFFF000000ULL); 508 509 for (size_t x = 0; x < X_SIZE; x++) 510 { 511 for (size_t y = 0; y < Y_SIZE ; y++) 512 { 513 514 sc_uint<vci_address_width> offset; 515 offset = (sc_uint<vci_address_width>)cluster(x,y) 516 << (vci_address_width-X_WIDTH-Y_WIDTH); 517 518 std::ostringstream sh; 519 sh << "x_seg_memc_" << x << "_" << y; 520 521 maptabx.add(Segment(sh.str(), MEMC_BASE + offset, 527 ///////////////////////////////////////////////// 528 // Ram network mapping table 529 ///////////////////////////////////////////////// 530 531 MappingTable maptabx(vci_address_width, 532 IntTab(X_WIDTH+Y_WIDTH), 533 IntTab(X_WIDTH+Y_WIDTH), 534 0x00FF000000ULL); 535 536 for (size_t x = 0; x < X_SIZE; x++) 537 { 538 for (size_t y = 0; y < Y_SIZE ; y++) 539 { 540 sc_uint<vci_address_width> offset; 541 offset = (sc_uint<vci_address_width>)cluster(x,y) 542 << (vci_address_width-X_WIDTH-Y_WIDTH); 543 544 std::ostringstream sh; 545 sh << "x_seg_memc_" << x << "_" << y; 546 547 maptabx.add(Segment(sh.str(), MEMC_BASE + offset, 522 548 MEMC_SIZE, IntTab(cluster(x,y)), false)); 523 } 524 } 525 std::cout << maptabx << std::endl; 526 527 //////////////////// 528 // Signals 529 /////////////////// 530 531 sc_clock signal_clk("clk"); 532 sc_signal<bool> signal_resetn("resetn"); 549 } 550 } 551 std::cout << maptabx << std::endl; 552 553 //////////////////// 554 // Signals 555 /////////////////// 556 557 sc_clock signal_clk("clk"); 558 sc_signal<bool> signal_resetn("resetn"); 559 560 // IRQs from external peripherals 561 sc_signal<bool> signal_irq_bdev; 562 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; 563 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; 564 sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; 565 sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; 566 sc_signal<bool> signal_irq_false; 533 567 534 568 // Horizontal inter-clusters DSPIN signals 535 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc = 536 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE, 3); 537 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec = 538 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE, 3); 539 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc = 540 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE, 2); 541 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec = 542 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE, 2); 569 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc = 570 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE); 571 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec = 572 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE); 573 574 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc = 575 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE); 576 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec = 577 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE); 578 579 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc = 580 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE); 581 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec = 582 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE); 583 584 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc = 585 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE); 586 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec = 587 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE); 588 589 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc = 590 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE); 591 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec = 592 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE); 543 593 544 594 // Vertical inter-clusters DSPIN signals 545 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc = 546 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1, 3); 547 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec = 548 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1, 3); 549 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc = 550 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1, 2); 551 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec = 552 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1, 2); 553 554 // Mesh boundaries DSPIN signals 555 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in = 556 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , X_SIZE, Y_SIZE, 4, 3); 557 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out = 558 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", X_SIZE, Y_SIZE, 4, 3); 559 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in = 560 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , X_SIZE, Y_SIZE, 4, 2); 561 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out = 562 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", X_SIZE, Y_SIZE, 4, 2); 563 564 595 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc = 596 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1); 597 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec = 598 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1); 599 600 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc = 601 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1); 602 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec = 603 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1); 604 605 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc = 606 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1); 607 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec = 608 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1); 609 610 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc = 611 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1); 612 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec = 613 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1); 614 615 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc = 616 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1); 617 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec = 618 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1); 619 620 // Mesh boundaries DSPIN signals (Most of those signals are not used...) 621 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in = 622 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4); 623 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out = 624 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4); 625 626 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in = 627 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4); 628 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out = 629 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4); 630 631 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in = 632 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4); 633 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out = 634 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4); 635 636 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in = 637 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4); 638 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out = 639 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4); 640 641 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in = 642 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4); 643 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out = 644 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4); 645 646 // VCI signals for iobus and peripherals 647 VciSignals<vci_param_int> signal_vci_ini_bdev("signal_vci_ini_bdev"); 648 VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma"); 649 VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi"); 650 651 VciSignals<vci_param_int>* signal_vci_ini_proc = 652 alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX ); 653 654 VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc"); 655 VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu"); 656 VciSignals<vci_param_int> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); 657 VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); 658 VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); 659 VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); 660 VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); 661 VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi"); 662 663 VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc"); 664 VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc"); 665 565 666 //////////////////////////// 566 667 // Loader … … 596 697 #endif 597 698 std::cout << std::endl; 598 std::cout << "Cluster_" << x << "_" << y599 << " with cluster_xy = " << cluster(x,y) << std::endl;699 std::cout << "Cluster_" << std::dec << x << "_" << y 700 << " with cluster_xy = " << std::hex << cluster(x,y) << std::endl; 600 701 std::cout << std::endl; 601 702 602 std::ostringstream sc;603 sc << "cluster_" << x << "_" << y;604 703 clusters[x][y] = new TsarLetiCluster<dspin_cmd_width, 605 704 dspin_rsp_width, … … 607 706 vci_param_ext> 608 707 ( 609 sc.str().c_str(),708 "cluster", 610 709 NB_PROCS_MAX, 611 NB_TTY_CHANNELS,612 NB_DMA_CHANNELS,613 710 x, 614 711 y, … … 622 719 MEMC_TGTID, 623 720 XICU_TGTID, 624 MDMA_TGTID,625 FBUF_TGTID,626 721 MTTY_TGTID, 627 MNIC_TGTID,628 CDMA_TGTID,629 722 BDEV_TGTID, 630 SIMH_TGTID,723 BDEV_IMAGE_NAME, 631 724 MEMC_WAYS, 632 725 MEMC_SETS, … … 636 729 L1_DSETS, 637 730 XRAM_LATENCY, 638 (cluster(x,y) == 0),639 FBUF_X_SIZE,640 FBUF_Y_SIZE,641 disk_name,642 BDEV_SECTOR_SIZE,643 NB_NIC_CHANNELS,644 nic_rx_name,645 nic_tx_name,646 NIC_TIMEOUT,647 NB_CMA_CHANNELS,648 731 loader, 649 732 frozen_cycles, … … 663 746 #endif 664 747 665 /////////////////////////////////////////////////////////////// 666 // Net-list 667 /////////////////////////////////////////////////////////////// 668 669 // Clock & RESET 670 for (size_t x = 0; x < (X_SIZE); x++){ 671 for (size_t y = 0; y < Y_SIZE; y++){ 672 clusters[x][y]->p_clk (signal_clk); 673 clusters[x][y]->p_resetn (signal_resetn); 674 } 675 } 676 677 // Inter Clusters horizontal connections 678 if (X_SIZE > 1){ 679 for (size_t x = 0; x < (X_SIZE-1); x++){ 680 for (size_t y = 0; y < Y_SIZE; y++){ 681 for (size_t k = 0; k < 3; k++){ 682 clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); 683 clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); 684 clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); 685 clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); 748 ////////////////////////////////////////////////////////////////// 749 // IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE] 750 ////////////////////////////////////////////////////////////////// 751 752 size_t cluster_io = cluster(X_SIZE-1, Y_SIZE); 753 754 //////////// vci_local_crossbar 755 VciLocalCrossbar<vci_param_int>* 756 iobus = new VciLocalCrossbar<vci_param_int>( 757 "iobus", 758 maptabd, // mapping table 759 cluster_io, // cluster_xy 760 NB_PROCS_MAX + 3, // number of local initiators 761 8, // number of local targets 762 BDEV_TGTID ); // default target index 763 764 //////////// vci_framebuffer 765 VciFrameBuffer<vci_param_int>* 766 fbuf = new VciFrameBuffer<vci_param_int>( 767 "fbuf", 768 IntTab(cluster_io, FBUF_TGTID), 769 maptabd, 770 FBUF_X_SIZE, FBUF_Y_SIZE ); 771 772 //////////// vci_block_device 773 VciBlockDeviceTsar<vci_param_int>* 774 bdev = new VciBlockDeviceTsar<vci_param_int>( 775 "bdev", 776 maptabd, 777 IntTab(cluster_io, BDEV_SRCID), 778 IntTab(cluster_io, BDEV_TGTID), 779 BDEV_IMAGE_NAME, 780 512, // block size 781 64 ); // burst size 782 783 //////////// vci_multi_nic 784 VciMultiNic<vci_param_int>* 785 mnic = new VciMultiNic<vci_param_int>( 786 "mnic", 787 IntTab(cluster_io, MNIC_TGTID), 788 maptabd, 789 NB_NIC_CHANNELS, 790 NIC_MAC4, 791 NIC_MAC2, 792 NIC_RX_NAME, 793 NIC_TX_NAME ); 794 795 ///////////// vci_chbuf_dma 796 VciChbufDma<vci_param_int>* 797 cdma = new VciChbufDma<vci_param_int>( 798 "cdma", 799 maptabd, 800 IntTab(cluster_io, CDMA_SRCID), 801 IntTab(cluster_io, CDMA_TGTID), 802 64, // burst size 803 NB_CMA_CHANNELS ); 804 805 ////////////// vci_multi_tty 806 std::vector<std::string> vect_names; 807 for (size_t id = 0; id < NB_TTY_CHANNELS; id++) 808 { 809 std::ostringstream term_name; 810 term_name << "ext_" << id; 811 vect_names.push_back(term_name.str().c_str()); 812 } 813 814 VciMultiTty<vci_param_int>* 815 mtty = new VciMultiTty<vci_param_int>( 816 "mtty", 817 IntTab(cluster_io, MTTY_TGTID), 818 maptabd, 819 vect_names ); 820 821 ///////////// vci_iopic 822 VciIopic<vci_param_int>* 823 iopic = new VciIopic<vci_param_int>( 824 "iopic", 825 maptabd, 826 IntTab(cluster_io, IOPI_SRCID), 827 IntTab(cluster_io, IOPI_TGTID), 828 16 ); 829 830 ////////////// vci_dspin wrappers 831 VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>* 832 wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>( 833 "wt_bdev", 834 vci_srcid_width ); 835 836 VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>* 837 wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>( 838 "wi_bdev", 839 vci_srcid_width ); 840 841 /////////////////////////////////////////////////////////////// 842 // Net-list 843 /////////////////////////////////////////////////////////////// 844 845 // iobus 846 iobus->p_clk (signal_clk); 847 iobus->p_resetn (signal_resetn); 848 849 iobus->p_target_to_up (signal_vci_cmd_from_noc); 850 iobus->p_initiator_to_up (signal_vci_cmd_to_noc); 851 852 iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc); 853 iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu); 854 iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty); 855 iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf); 856 iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic); 857 iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev); 858 iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma); 859 iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi); 860 861 for( size_t p=0 ; p<NB_PROCS_MAX ; p++ ) 862 { 863 iobus->p_to_initiator[p] (signal_vci_ini_proc[p]); 864 } 865 iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev); 866 iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma); 867 iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi); 868 869 std::cout << " - IOBUS connected" << std::endl; 870 871 // block_device 872 bdev->p_clk (signal_clk); 873 bdev->p_resetn (signal_resetn); 874 bdev->p_vci_target (signal_vci_tgt_bdev); 875 bdev->p_vci_initiator (signal_vci_ini_bdev); 876 bdev->p_irq (signal_irq_bdev); 877 878 std::cout << " - BDEV connected" << std::endl; 879 880 // frame_buffer 881 fbuf->p_clk (signal_clk); 882 fbuf->p_resetn (signal_resetn); 883 fbuf->p_vci (signal_vci_tgt_fbuf); 884 885 std::cout << " - FBUF connected" << std::endl; 886 887 // multi_nic 888 mnic->p_clk (signal_clk); 889 mnic->p_resetn (signal_resetn); 890 mnic->p_vci (signal_vci_tgt_mnic); 891 for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) 892 { 893 mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); 894 mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); 895 } 896 897 std::cout << " - MNIC connected" << std::endl; 898 899 // chbuf_dma 900 cdma->p_clk (signal_clk); 901 cdma->p_resetn (signal_resetn); 902 cdma->p_vci_target (signal_vci_tgt_cdma); 903 cdma->p_vci_initiator (signal_vci_ini_cdma); 904 for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++) 905 { 906 cdma->p_irq[i] (signal_irq_cdma[i]); 907 } 908 909 std::cout << " - CDMA connected" << std::endl; 910 911 // multi_tty 912 mtty->p_clk (signal_clk); 913 mtty->p_resetn (signal_resetn); 914 mtty->p_vci (signal_vci_tgt_mtty); 915 for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) 916 { 917 mtty->p_irq[i] (signal_irq_mtty[i]); 918 } 919 920 std::cout << " - MTTY connected" << std::endl; 921 922 // iopic 923 iopic->p_clk (signal_clk); 924 iopic->p_resetn (signal_resetn); 925 iopic->p_vci_target (signal_vci_tgt_iopi); 926 iopic->p_vci_initiator (signal_vci_ini_iopi); 927 for ( size_t i=0 ; i<16 ; i++) 928 { 929 if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]); 930 else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false); 931 else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]); 932 else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false); 933 else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]); 934 else if(i < 9) iopic->p_hwi[i] (signal_irq_false); 935 else if(i == 9) iopic->p_hwi[i] (signal_irq_bdev); 936 else if(i < 12) iopic->p_hwi[i] (signal_irq_false); 937 else if(i < 12+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty[i-12]); 938 else iopic->p_hwi[i] (signal_irq_false); 939 } 940 941 // vci/dspin wrappers 942 wi_iobus->p_clk (signal_clk); 943 wi_iobus->p_resetn (signal_resetn); 944 wi_iobus->p_vci (signal_vci_cmd_to_noc); 945 wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]); 946 wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]); 947 948 // vci/dspin wrappers 949 wt_iobus->p_clk (signal_clk); 950 wt_iobus->p_resetn (signal_resetn); 951 wt_iobus->p_vci (signal_vci_cmd_from_noc); 952 wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]); 953 wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]); 954 955 // Clock & RESET for clusters 956 for (size_t x = 0; x < (X_SIZE); x++) 957 { 958 for (size_t y = 0; y < Y_SIZE; y++) 959 { 960 clusters[x][y]->p_clk (signal_clk); 961 clusters[x][y]->p_resetn (signal_resetn); 962 } 963 } 964 965 // Inter Clusters horizontal connections 966 if (X_SIZE > 1) 967 { 968 for (size_t x = 0; x < (X_SIZE-1); x++) 969 { 970 for (size_t y = 0; y < Y_SIZE; y++) 971 { 972 clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]); 973 clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]); 974 clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]); 975 clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]); 976 977 clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]); 978 clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]); 979 clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]); 980 clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]); 981 982 clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]); 983 clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]); 984 clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]); 985 clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]); 986 987 clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]); 988 clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]); 989 clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]); 990 clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]); 991 992 clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]); 993 clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]); 994 clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]); 995 clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]); 686 996 } 687 688 for (size_t k = 0; k < 2; k++){ 689 clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); 690 clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); 691 clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); 692 clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); 997 } 998 } 999 std::cout << std::endl << "Horizontal connections done" << std::endl; 1000 1001 // Inter Clusters vertical connections 1002 if (Y_SIZE > 1) 1003 { 1004 for (size_t y = 0; y < (Y_SIZE-1); y++) 1005 { 1006 for (size_t x = 0; x < X_SIZE; x++) 1007 { 1008 clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]); 1009 clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]); 1010 clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]); 1011 clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]); 1012 1013 clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]); 1014 clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]); 1015 clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]); 1016 clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]); 1017 1018 clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]); 1019 clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]); 1020 clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]); 1021 clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]); 1022 1023 clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]); 1024 clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]); 1025 clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]); 1026 clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]); 1027 1028 clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]); 1029 clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]); 1030 clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]); 1031 clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]); 693 1032 } 694 } 695 } 696 } 697 std::cout << std::endl << "Horizontal connections established" << std::endl; 698 699 // Inter Clusters vertical connections 700 if (Y_SIZE > 1) { 701 for (size_t y = 0; y < (Y_SIZE-1); y++){ 702 for (size_t x = 0; x < X_SIZE; x++){ 703 for (size_t k = 0; k < 3; k++){ 704 clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); 705 clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); 706 clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); 707 clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); 1033 } 1034 } 1035 std::cout << std::endl << "Vertical connections done" << std::endl; 1036 1037 // East & West boundary cluster connections 1038 for (size_t y = 0; y < Y_SIZE; y++) 1039 { 1040 clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]); 1041 clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]); 1042 clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]); 1043 clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]); 1044 1045 clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]); 1046 clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]); 1047 clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]); 1048 clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]); 1049 1050 clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]); 1051 clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]); 1052 clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]); 1053 clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]); 1054 1055 clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]); 1056 clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]); 1057 clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]); 1058 clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]); 1059 1060 clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]); 1061 clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]); 1062 clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]); 1063 clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]); 1064 } 1065 1066 // North & South boundary clusters connections 1067 for (size_t x = 0; x < X_SIZE; x++) 1068 { 1069 clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]); 1070 clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]); 1071 clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]); 1072 clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]); 1073 1074 clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]); 1075 clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]); 1076 clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]); 1077 clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]); 1078 1079 clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]); 1080 clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]); 1081 clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]); 1082 clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]); 1083 1084 clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]); 1085 clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]); 1086 clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]); 1087 clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]); 1088 1089 clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]); 1090 clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]); 1091 clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]); 1092 clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]); 1093 } 1094 1095 std::cout << std::endl << "North, South, West, East connections done" << std::endl; 1096 std::cout << std::endl; 1097 1098 //////////////////////////////////////////////////////// 1099 // Simulation 1100 /////////////////////////////////////////////////////// 1101 1102 sc_start(sc_core::sc_time(0, SC_NS)); 1103 signal_resetn = false; 1104 signal_irq_false = false; 1105 1106 // set network boundaries signals default values 1107 // for all boundary clusters but the IO cluster 1108 for (size_t x = 0; x < X_SIZE ; x++) 1109 { 1110 for (size_t y = 0; y < Y_SIZE ; y++) 1111 { 1112 for (size_t face = 0; face < 4; face++) 1113 { 1114 if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) ) 1115 { 1116 signal_dspin_bound_cmd_in [x][y][face].write = false; 1117 signal_dspin_bound_cmd_in [x][y][face].read = true; 1118 signal_dspin_bound_cmd_out[x][y][face].write = false; 1119 signal_dspin_bound_cmd_out[x][y][face].read = true; 1120 1121 signal_dspin_bound_rsp_in [x][y][face].write = false; 1122 signal_dspin_bound_rsp_in [x][y][face].read = true; 1123 signal_dspin_bound_rsp_out[x][y][face].write = false; 1124 signal_dspin_bound_rsp_out[x][y][face].read = true; 1125 } 1126 1127 signal_dspin_bound_m2p_in [x][y][face].write = false; 1128 signal_dspin_bound_m2p_in [x][y][face].read = true; 1129 signal_dspin_bound_m2p_out[x][y][face].write = false; 1130 signal_dspin_bound_m2p_out[x][y][face].read = true; 1131 1132 signal_dspin_bound_p2m_in [x][y][face].write = false; 1133 signal_dspin_bound_p2m_in [x][y][face].read = true; 1134 signal_dspin_bound_p2m_out[x][y][face].write = false; 1135 signal_dspin_bound_p2m_out[x][y][face].read = true; 1136 1137 signal_dspin_bound_cla_in [x][y][face].write = false; 1138 signal_dspin_bound_cla_in [x][y][face].read = true; 1139 signal_dspin_bound_cla_out[x][y][face].write = false; 1140 signal_dspin_bound_cla_out[x][y][face].read = true; 708 1141 } 709 710 for (size_t k = 0; k < 2; k++){ 711 clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); 712 clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); 713 clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); 714 clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); 715 } 716 } 717 } 718 } 719 std::cout << "Vertical connections established" << std::endl; 720 721 // East & West boundary cluster connections 722 for (size_t y = 0; y < Y_SIZE; y++) 723 { 724 for (size_t k = 0; k < 3; k++) 725 { 726 clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]); 727 clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); 728 clusters[X_SIZE-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[X_SIZE-1][y][EAST][k]); 729 clusters[X_SIZE-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[X_SIZE-1][y][EAST][k]); 730 } 731 732 for (size_t k = 0; k < 2; k++) 733 { 734 clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]); 735 clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); 736 clusters[X_SIZE-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[X_SIZE-1][y][EAST][k]); 737 clusters[X_SIZE-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[X_SIZE-1][y][EAST][k]); 738 } 739 } 740 741 // North & South boundary clusters connections 742 for (size_t x = 0; x < X_SIZE; x++) 743 { 744 for (size_t k = 0; k < 3; k++) 745 { 746 clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]); 747 clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); 748 clusters[x][Y_SIZE-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][Y_SIZE-1][NORTH][k]); 749 clusters[x][Y_SIZE-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][Y_SIZE-1][NORTH][k]); 750 } 751 752 for (size_t k = 0; k < 2; k++) 753 { 754 clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]); 755 clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); 756 clusters[x][Y_SIZE-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][Y_SIZE-1][NORTH][k]); 757 clusters[x][Y_SIZE-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][Y_SIZE-1][NORTH][k]); 758 } 759 } 760 std::cout << "North, South, West, East connections established" << std::endl; 761 std::cout << std::endl; 762 763 764 //////////////////////////////////////////////////////// 765 // Simulation 766 /////////////////////////////////////////////////////// 767 768 sc_start(sc_core::sc_time(0, SC_NS)); 769 signal_resetn = false; 770 771 // network boundaries signals 772 for (size_t x = 0; x < X_SIZE ; x++){ 773 for (size_t y = 0; y < Y_SIZE ; y++){ 774 for (size_t a = 0; a < 4; a++){ 775 for (size_t k = 0; k < 3; k++){ 776 signal_dspin_false_cmd_in [x][y][a][k].write = false; 777 signal_dspin_false_cmd_in [x][y][a][k].read = true; 778 signal_dspin_false_cmd_out[x][y][a][k].write = false; 779 signal_dspin_false_cmd_out[x][y][a][k].read = true; 780 } 781 782 for (size_t k = 0; k < 2; k++){ 783 signal_dspin_false_rsp_in [x][y][a][k].write = false; 784 signal_dspin_false_rsp_in [x][y][a][k].read = true; 785 signal_dspin_false_rsp_out[x][y][a][k].write = false; 786 signal_dspin_false_rsp_out[x][y][a][k].read = true; 787 } 788 } 789 } 790 } 791 792 sc_start(sc_core::sc_time(1, SC_NS)); 793 signal_resetn = true; 794 795 if (gettimeofday(&t1, NULL) != 0) 796 { 797 perror("gettimeofday"); 798 return EXIT_FAILURE; 799 } 1142 } 1143 } 1144 1145 sc_start(sc_core::sc_time(1, SC_NS)); 1146 signal_resetn = true; 1147 1148 if (gettimeofday(&t1, NULL) != 0) 1149 { 1150 perror("gettimeofday"); 1151 return EXIT_FAILURE; 1152 } 800 1153 801 1154 for (uint64_t n = 1; n < ncycles && !stop_called; n++) 802 1155 { 803 1156 // Monitor a specific address for L1 & L2 caches 804 // clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL);805 // clusters[1][0]->memc->copies_monitor(0x800002C000ULL);1157 // clusters[0][0]->proc[0]->cache_monitor(0x0000010000ULL); 1158 // clusters[0][0]->memc->cache_monitor(0x0000030000ULL); 806 1159 807 1160 if( (n % 5000000) == 0) … … 838 1191 std::ostringstream proc_signame; 839 1192 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 840 std::ostringstream p2m_signame; 841 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 842 std::ostringstream m2p_signame; 843 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 844 std::ostringstream p_cmd_signame; 845 p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; 846 std::ostringstream p_rsp_signame; 847 p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; 848 849 clusters[x][y]->proc[l]->print_trace(); 850 // clusters[x][y]->wi_proc[l]->print_trace(); 1193 std::ostringstream xicu_signame; 1194 xicu_signame << "[SIG]XICU_" << x << "_" << y ; 1195 1196 clusters[x][y]->proc[l]->print_trace(0x1); 851 1197 clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); 852 clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 853 clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 854 clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); 855 clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); 856 857 // clusters[x][y]->xbar_rsp_d->print_trace(); 858 // clusters[x][y]->xbar_cmd_d->print_trace(); 859 // clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); 860 // clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); 861 // clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); 862 // clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); 863 864 // trace memc[trace_memc_id] 1198 1199 clusters[x][y]->xicu->print_trace(0); 1200 clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str()); 1201 1202 if ( clusters[x][y]->signal_proc_irq[0].read() ) 1203 std::cout << " IRQ_PROC active in cluster " << cluster(x,y) << std::endl; 1204 1205 if ( signal_irq_bdev.read() ) 1206 std::cout << " IRQ_BDEV in cluster_io active" << std::endl; 1207 1208 // trace memc[trace_memc_id] and xram[trace_memc_id] 865 1209 x = trace_memc_id >> Y_WIDTH; 866 1210 y = trace_memc_id & ((1<<Y_WIDTH) - 1); … … 870 1214 std::ostringstream sxram; 871 1215 sxram << "[SIG]XRAM_" << x << "_" << y; 872 std::ostringstream sm2p;873 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ;874 std::ostringstream sp2m;875 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ;876 std::ostringstream m_cmd_signame;877 m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ;878 std::ostringstream m_rsp_signame;879 m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ;880 1216 881 1217 clusters[x][y]->memc->print_trace(); 882 // clusters[x][y]->wt_memc->print_trace();883 1218 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 884 1219 clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 885 clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str());886 clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str());887 clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str());888 clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str());889 1220 890 // trace replicated peripherals 891 // clusters[1][1]->mdma->print_trace(); 892 // clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); 893 // clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); 1221 // trace coherence signals 1222 // clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]"); 1223 // clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]"); 1224 // clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]"); 1225 // clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]"); 1226 1227 // clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]"); 1228 // clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]"); 1229 // clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]"); 1230 // clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]"); 1231 1232 // trace xbar(s) m2p 1233 // clusters[0][0]->xbar_m2p->print_trace(); 1234 // clusters[1][0]->xbar_m2p->print_trace(); 1235 // clusters[0][1]->xbar_m2p->print_trace(); 1236 // clusters[1][1]->xbar_m2p->print_trace(); 894 1237 895 1238 // trace router(s) m2p 1239 // clusters[0][0]->router_m2p->print_trace(); 1240 // clusters[1][0]->router_m2p->print_trace(); 1241 // clusters[0][1]->router_m2p->print_trace(); 1242 // clusters[1][1]->router_m2p->print_trace(); 1243 896 1244 // trace external peripherals 897 898 // clusters[0][0]->bdev->print_trace(); 899 // clusters[0][0]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 900 // clusters[0][0]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 901 902 // clusters[0][0]->mtty->print_trace(); 903 // clusters[0][0]->wt_mtty->print_trace(); 904 // clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); 905 } 1245 bdev->print_trace(); 1246 signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 1247 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1248 1249 iopic->print_trace(); 1250 signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); 1251 signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); 1252 1253 clusters[0][0]->mtty->print_trace(); 1254 clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); 1255 } // end trace 906 1256 907 1257 sc_start(sc_core::sc_time(1, SC_NS)); … … 917 1267 } 918 1268 919 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X_SIZE - 1, Y_SIZE, 3);920 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X_SIZE - 1, Y_SIZE, 3);921 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X_SIZE - 1, Y_SIZE, 2);922 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X_SIZE - 1, Y_SIZE, 2);923 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE - 1, 3);924 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE - 1, 3);925 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE - 1, 2);926 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE - 1, 2);927 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_in, X_SIZE, Y_SIZE, 4, 3);928 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_out, X_SIZE, Y_SIZE, 4, 3);929 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_in, X_SIZE, Y_SIZE, 4, 2);930 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_out, X_SIZE, Y_SIZE, 4, 2);931 932 1269 return EXIT_SUCCESS; 933 1270 } 934 1271 935 1272 936 void handler(int dummy = 0) { 1273 void handler(int dummy = 0) 1274 { 937 1275 stop_called = true; 938 1276 sc_stop();
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