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source: trunk/platforms/tsar_generic_leti/top.cpp @ 948

Last change on this file since 948 was 939, checked in by alain, 10 years ago
Introduce the distributed kernel heap vsegs.
File size: 54.2 KB

Rev	Line
[621]	1	/////////////////////////////////////////////////////////////////////////
[664]	2	// File: top.cpp (for tsar_generic_leti)
[792]	3	// Author: Alain Greiner
[621]	4	// Copyright: UPMC/LIP6
[937]	5	// Date : february 2013 / updated january 2015
[621]	6	// This program is released under the GNU public license
	7	/////////////////////////////////////////////////////////////////////////
[681]	8	// This file define a generic TSAR architecture, fully compatible
	9	// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
	10	// in the framework of the SHARP project.
[792]	11	//
[621]	12	// The processor is a MIPS32 processor wrapped in a GDB server
	13	// (this is defined in the tsar_xbar_cluster).
[792]	14	//
[937]	15	// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
	16	// and the number of processors per cluster (NB_PROCS_MAX).
	17	// The NB_PROCS_MAX parameter cannot be larger than 4.
[621]	18	//
[937]	19	// All external peripherals are located in cluster[X_SIZE-1][Y_SIZE-1],
	20	// and are connected to an IO bus (implemented as a vci_local_crossbar):
	21	// - one disk controller
	22	// - one multi-channel ethernet controller
	23	// - one multi-channel chained buffer dma controller
	24	// - one multi-channel tty controller
	25	// - one frame buffer controller
	26	// - one iopic controller
	27	// This IO bus is directly connected to the north ports of the CMD/RSP
	28	// routers in cluster[X_SIZE-1][y_SIZE-2] through VCI/DSPIN wrappers.
	29	// All other clusters in the upper row are empty: no processors,
	30	// no ram, no routers.
	31	// The X_SIZE parameter must be larger than 0, but no larger than 16.
	32	// The Y_SIZE parameter must be larger than 1, but no larger than 16.
	33	//
	34	// We don't use an external ROM, as the boot code is (pre)loaded
	35	// in RAM in cluster[0][0] at address 0x0.
	36	//
	37	// An optional RAMDISK of 32 Mbytes can be used in RAM of cluster[0][0].
	38	//
[621]	39	// The physical address space is 40 bits.
	40	// The 8 address MSB bits define the cluster index.
	41	//
[937]	42	// Besides the processors, each cluster contains:
	43	// - 5 L1/L2 DSPIN routers implementing 5 separated NOCs
[628]	44	// - 1 vci_mem_cache
	45	// - 1 vci_xicu
[937]	46	// - 1 vci_simple_ram (to emulate the L3 cache).
[621]	47	//
[681]	48	// Each processor receives 4 consecutive IRQ lines from the local XICU.
[664]	49	//
[628]	50	// In all clusters, the MEMC IRQ line (signaling a late write error)
	51	// is connected to XICU HWI[8]
[621]	52	//
[792]	53	// This IOBUS is connected to the north port of the DIR_CMD
[681]	54	// and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1).
[628]	55	// For all external peripherals, the hardware interrupts (HWI) are
[664]	56	// translated to write interrupts (WTI) by the iopic component:
	57	// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
[792]	58	// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
[664]	59	// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
	60	// - IOPIC HWI[8] connected to IRQ_BDEV
	61	// - IOPIC HWI[15:9] unused (grounded)
	62	// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
	63	// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
[937]	64	//
	65	// The cluster internal architecture is defined in file tsar_leti_cluster,
	66	// that must be considered as an extension of this top.cpp file.
[628]	67	////////////////////////////////////////////////////////////////////////////
	68	// The following parameters must be defined in the hard_config.h file :
[621]	69	// - X_WIDTH : number of bits for x coordinate (must be 4)
	70	// - Y_WIDTH : number of bits for y coordinate (must be 4)
[681]	71	// - X_SIZE : number of clusters in a row (1,2,4,8,16)
	72	// - Y_SIZE : number of clusters in a column (1,2,4,8)
[628]	73	// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
[664]	74	// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
	75	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
[628]	76	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
[937]	77	// - FBUF_X_SIZE : number of pixels per line for frame buffer
	78	// - FBUF_Y_SIZE : number of lines for frame buffer
[792]	79	//
[621]	80	// Some other hardware parameters are not used when compiling the OS,
[628]	81	// and are only defined in this top.cpp file:
[792]	82	// - XRAM_LATENCY : external ram latency
[628]	83	// - L1_IWAYS : L1 cache instruction number of ways
	84	// - L1_ISETS : L1 cache instruction number of sets
	85	// - L1_DWAYS : L1 cache data number of ways
	86	// - L1_DSETS : L1 cache data number of sets
[937]	87	// - BDEV_IMAGE_NAME : pathname for block device disk image
[621]	88	/////////////////////////////////////////////////////////////////////////
	89	// General policy for 40 bits physical address decoding:
	90	// All physical segments base addresses are multiple of 1 Mbytes
[792]	91	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
[621]	92	// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
	93	// the cluster index, and the LADR bits define the local index:
	94	// \|X_ID\|Y_ID\| LADR \| OFFSET \|
	95	// \| 4 \| 4 \| 8 \| 24 \|
	96	/////////////////////////////////////////////////////////////////////////
	97	// General policy for 14 bits SRCID decoding:
	98	// Each component is identified by (x_id, y_id, l_id) tuple.
	99	// \|X_ID\|Y_ID\| L_ID \|
	100	// \| 4 \| 4 \| 6 \|
	101	/////////////////////////////////////////////////////////////////////////
	102
	103	#include <systemc>
	104	#include <sys/time.h>
	105	#include <iostream>
	106	#include <sstream>
	107	#include <cstdlib>
	108	#include <cstdarg>
	109	#include <stdint.h>
	110
	111	#include "gdbserver.h"
	112	#include "mapping_table.h"
	113	#include "tsar_leti_cluster.h"
[628]	114	#include "vci_local_crossbar.h"
	115	#include "vci_dspin_initiator_wrapper.h"
	116	#include "vci_dspin_target_wrapper.h"
	117	#include "vci_multi_tty.h"
	118	#include "vci_multi_nic.h"
	119	#include "vci_chbuf_dma.h"
	120	#include "vci_block_device_tsar.h"
	121	#include "vci_framebuffer.h"
	122	#include "vci_iopic.h"
[621]	123	#include "alloc_elems.h"
	124
[792]	125	#include "hard_config.h"
[621]	126
	127	///////////////////////////////////////////////////
	128	// Parallelisation
	129	///////////////////////////////////////////////////
[708]	130	#define USE_OPENMP _OPENMP
[621]	131
	132	#if USE_OPENMP
	133	#include <omp.h>
	134	#endif
	135
	136	///////////////////////////////////////////////////
	137	// cluster index (from x,y coordinates)
	138	///////////////////////////////////////////////////
	139
[692]	140	#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
[621]	141
	142	///////////////////////////////////////////////////////////
[792]	143	// DSPIN parameters
[621]	144	///////////////////////////////////////////////////////////
	145
	146	#define dspin_cmd_width 39
	147	#define dspin_rsp_width 32
	148
	149	///////////////////////////////////////////////////////////
[792]	150	// VCI parameters
[621]	151	///////////////////////////////////////////////////////////
	152
	153	#define vci_cell_width_int 4
	154	#define vci_cell_width_ext 8
	155	#define vci_address_width 40
	156	#define vci_plen_width 8
	157	#define vci_rerror_width 1
	158	#define vci_clen_width 1
	159	#define vci_rflag_width 1
	160	#define vci_srcid_width 14
	161	#define vci_pktid_width 4
	162	#define vci_trdid_width 4
	163	#define vci_wrplen_width 1
	164
	165
[937]	166	///////////////////////////////////////////////////////////////////////////////////////
[792]	167	// Secondary Hardware Parameters
[937]	168	///////////////////////////////////////////////////////////////////////////////////////
[621]	169
[937]	170	#define XMAX X_SIZE // actual number of columns in 2D mesh
	171	#define YMAX (Y_SIZE - 1) // actual number of rows in 2D mesh
[664]	172
[621]	173	#define XRAM_LATENCY 0
	174
	175	#define MEMC_WAYS 16
	176	#define MEMC_SETS 256
	177
	178	#define L1_IWAYS 4
	179	#define L1_ISETS 64
	180
	181	#define L1_DWAYS 4
	182	#define L1_DSETS 64
	183
[937]	184	#define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg"
[621]	185
[937]	186	#define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf"
	187
[621]	188	#define NORTH 0
	189	#define SOUTH 1
	190	#define EAST 2
	191	#define WEST 3
	192
[664]	193	///////////////////////////////////////////////////////////////////////////////////////
[792]	194	// DEBUG Parameters default values
[664]	195	///////////////////////////////////////////////////////////////////////////////////////
[621]	196
[681]	197	#define MAX_FROZEN_CYCLES 500000
[621]	198
[664]	199	///////////////////////////////////////////////////////////////////////////////////////
[792]	200	// LOCAL TGTID & SRCID definition
[621]	201	// For all components: global TGTID = global SRCID = cluster_index
[664]	202	///////////////////////////////////////////////////////////////////////////////////////
[621]	203
[664]	204	#define MEMC_TGTID 0
	205	#define XICU_TGTID 1
	206	#define MTTY_TGTID 2
	207	#define BDEV_TGTID 3
	208	#define FBUF_TGTID 4
	209	#define MNIC_TGTID 5
	210	#define CDMA_TGTID 6
	211	#define IOPI_TGTID 7
[621]	212
[664]	213	#define BDEV_SRCID NB_PROCS_MAX
	214	#define CDMA_SRCID NB_PROCS_MAX + 1
	215	#define IOPI_SRCID NB_PROCS_MAX + 2
[628]	216
[621]	217	bool stop_called = false;
	218
	219	/////////////////////////////////
	220	int _main(int argc, char *argv[])
	221	{
	222	using namespace sc_core;
	223	using namespace soclib::caba;
	224	using namespace soclib::common;
	225
[937]	226	uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
	227	size_t threads = 1; // simulator's threads number
	228	bool trace_ok = false; // trace activated
	229	uint32_t trace_from = 0; // trace start cycle
	230	bool trace_proc_ok = false; // detailed proc trace activated
	231	size_t trace_memc_ok = false; // detailed memc trace activated
	232	size_t trace_memc_id = 0; // index of memc to be traced
	233	size_t trace_proc_id = 0; // index of proc to be traced
	234	char soft_name[256] = ROM_SOFT_NAME; // pathname for ROM binary code
	235	char disk_name[256] = BDEV_IMAGE_NAME; // pathname for DISK image
	236	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // for debug
[621]	237	struct timeval t1,t2;
	238	uint64_t ms1,ms2;
	239
	240	////////////// command line arguments //////////////////////
	241	if (argc > 1)
	242	{
	243	for (int n = 1; n < argc; n = n + 2)
	244	{
	245	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
	246	{
	247	ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
	248	}
	249	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
	250	{
	251	trace_ok = true;
	252	trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
	253	}
	254	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
	255	{
	256	trace_memc_ok = true;
	257	trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
	258	size_t x = trace_memc_id >> Y_WIDTH;
	259	size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
	260
[937]	261	assert( (x < XMAX) and (y < (YMAX)) and
[621]	262	"MEMCID parameter refers a not valid memory cache");
	263	}
	264	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
	265	{
	266	trace_proc_ok = true;
	267	trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
[803]	268	size_t cluster_xy = trace_proc_id >> P_WIDTH ;
[621]	269	size_t x = cluster_xy >> Y_WIDTH;
	270	size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
[803]	271	size_t l = trace_proc_id & ((1<<P_WIDTH)-1) ;
[621]	272
[937]	273	assert( (x < XMAX) and (y < YMAX) and (l < NB_PROCS_MAX) and
[621]	274	"PROCID parameter refers a not valid processor");
	275	}
[937]	276	else if ((strcmp(argv[n], "-ROM") == 0) && ((n + 1) < argc))
[692]	277	{
[792]	278	strcpy(soft_name, argv[n + 1]);
[692]	279	}
	280	else if ((strcmp(argv[n], "-DISK") == 0) && ((n + 1) < argc))
	281	{
	282	strcpy(disk_name, argv[n + 1]);
	283	}
[621]	284	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
	285	{
[628]	286	threads = (size_t) strtol(argv[n + 1], NULL, 0);
	287	threads = (threads < 1) ? 1 : threads;
[621]	288	}
	289	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
	290	{
	291	frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
	292	}
	293	else
	294	{
	295	std::cout << " Arguments are (key,value) couples." << std::endl;
	296	std::cout << " The order is not important." << std::endl;
	297	std::cout << " Accepted arguments are :" << std::endl << std::endl;
[937]	298	std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl;
	299	std::cout << " - DEBUG debug_start_cycle" << std::endl;
	300	std::cout << " - ROM path to ROM image" << std::endl;
	301	std::cout << " - DISK path to disk image" << std::endl;
	302	std::cout << " - THREADS simulator's threads number" << std::endl;
	303	std::cout << " - FROZEN max_number_of_lines" << std::endl;
	304	std::cout << " - PERIOD number_of_cycles between trace" << std::endl;
	305	std::cout << " - MEMCID index_memc_to_be_traced" << std::endl;
	306	std::cout << " - PROCID index_proc_to_be_traced" << std::endl;
[621]	307	exit(0);
	308	}
	309	}
	310	}
	311
	312	// checking hardware parameters
[937]	313	assert( ((X_SIZE <= 16) and (X_SIZE > 0)) and
[681]	314	"Illegal X_SIZE parameter" );
[621]	315
[937]	316	assert( ((Y_SIZE <= 16) and (Y_SIZE > 1)) and
[681]	317	"Illegal Y_SIZE parameter" );
[621]	318
[803]	319	assert( (P_WIDTH <= 2) and
	320	"P_WIDTH parameter cannot be larger than 2" );
	321
[664]	322	assert( (NB_PROCS_MAX <= 4) and
[681]	323	"Illegal NB_PROCS_MAX parameter" );
[621]	324
[937]	325	assert( (NB_CMA_CHANNELS <= 4) and
[628]	326	"The NB_CMA_CHANNELS parameter cannot be larger than 4" );
[621]	327
[937]	328	assert( (NB_TTY_CHANNELS <= 8) and
	329	"The NB_TTY_CHANNELS parameter cannot be larger than 16" );
[621]	330
[937]	331	assert( (NB_NIC_CHANNELS <= 2) and
[628]	332	"The NB_NIC_CHANNELS parameter cannot be larger than 2" );
[621]	333
	334	assert( (vci_address_width == 40) and
	335	"VCI address width with the GIET must be 40 bits" );
	336
	337	assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
[937]	338	"You must have X_WIDTH == Y_WIDTH == 4");
[792]	339
[621]	340	std::cout << std::endl;
	341
[937]	342	std::cout << " - XMAX = " << XMAX << std::endl;
	343	std::cout << " - YMAX = " << YMAX << std::endl;
[621]	344	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
	345	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
	346	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
[937]	347	std::cout << " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl;
[621]	348	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
	349	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
	350	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
	351	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
	352	std::cout << " - MAX_CYCLES = " << ncycles << std::endl;
	353	std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl;
[692]	354	std::cout << " - SOFT_FILENAME = " << soft_name << std::endl;
	355	std::cout << " - DISK_IMAGENAME = " << disk_name << std::endl;
	356	std::cout << " - OPENMP THREADS = " << threads << std::endl;
[621]	357
	358	std::cout << std::endl;
	359
	360	// Internal and External VCI parameters definition
	361	typedef soclib::caba::VciParams<vci_cell_width_int,
	362	vci_plen_width,
	363	vci_address_width,
	364	vci_rerror_width,
	365	vci_clen_width,
	366	vci_rflag_width,
	367	vci_srcid_width,
	368	vci_pktid_width,
	369	vci_trdid_width,
	370	vci_wrplen_width> vci_param_int;
	371
	372	typedef soclib::caba::VciParams<vci_cell_width_ext,
	373	vci_plen_width,
	374	vci_address_width,
	375	vci_rerror_width,
	376	vci_clen_width,
	377	vci_rflag_width,
	378	vci_srcid_width,
	379	vci_pktid_width,
	380	vci_trdid_width,
	381	vci_wrplen_width> vci_param_ext;
	382
	383	#if USE_OPENMP
	384	omp_set_dynamic(false);
[628]	385	omp_set_num_threads(threads);
[621]	386	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
	387	#endif
	388
	389
[628]	390	///////////////////////////////////////
	391	// Direct Network Mapping Table
	392	///////////////////////////////////////
[621]	393
[792]	394	MappingTable maptabd(vci_address_width,
	395	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
	396	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
[628]	397	0x00FF000000ULL);
[621]	398
[628]	399	// replicated segments
[937]	400	for (size_t x = 0; x < XMAX; x++)
[621]	401	{
[937]	402	for (size_t y = 0; y < (YMAX) ; y++)
[621]	403	{
	404	sc_uint<vci_address_width> offset;
[628]	405	offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
[621]	406
	407	std::ostringstream si;
	408	si << "seg_xicu_" << x << "_" << y;
[792]	409	maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
[621]	410	IntTab(cluster(x,y),XICU_TGTID), false));
	411
	412	std::ostringstream sd;
[628]	413	sd << "seg_mcfg_" << x << "_" << y;
[792]	414	maptabd.add(Segment(sd.str(), SEG_MMC_BASE + offset, SEG_MMC_SIZE,
[628]	415	IntTab(cluster(x,y),MEMC_TGTID), false));
[621]	416
	417	std::ostringstream sh;
	418	sh << "seg_memc_" << x << "_" << y;
[792]	419	maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
[621]	420	IntTab(cluster(x,y),MEMC_TGTID), true));
	421	}
	422	}
[628]	423
[664]	424	// segments for peripherals in cluster(0,0)
[792]	425	maptabd.add(Segment("seg_tty0", SEG_TTY_BASE, SEG_TTY_SIZE,
[628]	426	IntTab(cluster(0,0),MTTY_TGTID), false));
	427
[792]	428	maptabd.add(Segment("seg_ioc0", SEG_IOC_BASE, SEG_IOC_SIZE,
[628]	429	IntTab(cluster(0,0),BDEV_TGTID), false));
	430
[937]	431	// segments for peripherals in cluster_io (XMAX-1,YMAX)
[628]	432	sc_uint<vci_address_width> offset;
[937]	433	offset = ((sc_uint<vci_address_width>)cluster(XMAX-1,YMAX)) << 32;
[628]	434
[792]	435	maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
[937]	436	IntTab(cluster(XMAX-1, YMAX),MTTY_TGTID), false));
[628]	437
[792]	438	maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
[937]	439	IntTab(cluster(XMAX-1, YMAX),FBUF_TGTID), false));
[628]	440
[792]	441	maptabd.add(Segment("seg_bdev", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
[937]	442	IntTab(cluster(XMAX-1, YMAX),BDEV_TGTID), false));
[628]	443
[792]	444	maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
[937]	445	IntTab(cluster(XMAX-1, YMAX),MNIC_TGTID), false));
[628]	446
[792]	447	maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
[937]	448	IntTab(cluster(XMAX-1, YMAX),CDMA_TGTID), false));
[628]	449
[792]	450	maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
[937]	451	IntTab(cluster(XMAX-1, YMAX),IOPI_TGTID), false));
[628]	452
[621]	453	std::cout << maptabd << std::endl;
	454
[628]	455	/////////////////////////////////////////////////
	456	// Ram network mapping table
	457	/////////////////////////////////////////////////
[621]	458
[792]	459	MappingTable maptabx(vci_address_width,
	460	IntTab(X_WIDTH+Y_WIDTH),
	461	IntTab(X_WIDTH+Y_WIDTH),
[628]	462	0x00FF000000ULL);
[621]	463
[937]	464	for (size_t x = 0; x < XMAX; x++)
[628]	465	{
[937]	466	for (size_t y = 0; y < (YMAX) ; y++)
[792]	467	{
[628]	468	sc_uint<vci_address_width> offset;
[792]	469	offset = (sc_uint<vci_address_width>)cluster(x,y)
[628]	470	<< (vci_address_width-X_WIDTH-Y_WIDTH);
[621]	471
[628]	472	std::ostringstream sh;
	473	sh << "x_seg_memc_" << x << "_" << y;
[621]	474
[792]	475	maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
	476	SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
[628]	477	}
	478	}
	479	std::cout << maptabx << std::endl;
[621]	480
[628]	481	////////////////////
	482	// Signals
	483	///////////////////
[621]	484
[628]	485	sc_clock signal_clk("clk");
	486	sc_signal<bool> signal_resetn("resetn");
[621]	487
[628]	488	// IRQs from external peripherals
	489	sc_signal<bool> signal_irq_bdev;
	490	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
	491	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
[664]	492	sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
[628]	493	sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
	494	sc_signal<bool> signal_irq_false;
	495
[621]	496	// Horizontal inter-clusters DSPIN signals
[628]	497	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
[937]	498	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX);
[628]	499	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
[937]	500	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX);
[621]	501
[628]	502	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
[937]	503	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX);
[628]	504	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
[937]	505	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX);
[628]	506
	507	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
[937]	508	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", XMAX-1, YMAX);
[628]	509	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
[937]	510	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", XMAX-1, YMAX);
[628]	511
	512	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
[937]	513	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", XMAX-1, YMAX);
[628]	514	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
[937]	515	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", XMAX-1, YMAX);
[628]	516
	517	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
[937]	518	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", XMAX-1, YMAX);
[628]	519	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
[937]	520	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", XMAX-1, YMAX);
[628]	521
[621]	522	// Vertical inter-clusters DSPIN signals
[628]	523	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
[937]	524	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1);
[628]	525	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
[937]	526	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1);
[621]	527
[628]	528	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
[937]	529	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1);
[628]	530	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
[937]	531	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1);
[621]	532
[628]	533	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
[937]	534	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", XMAX, YMAX-1);
[628]	535	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
[937]	536	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", XMAX, YMAX-1);
[621]	537
[628]	538	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
[937]	539	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", XMAX, YMAX-1);
[628]	540	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
[937]	541	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", XMAX, YMAX-1);
[628]	542
	543	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
[937]	544	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", XMAX, YMAX-1);
[628]	545	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
[937]	546	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", XMAX, YMAX-1);
[628]	547
	548	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
	549	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
[937]	550	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , XMAX, YMAX, 4);
[628]	551	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
[937]	552	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", XMAX, YMAX, 4);
[628]	553
	554	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
[937]	555	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , XMAX, YMAX, 4);
[628]	556	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
[937]	557	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", XMAX, YMAX, 4);
[628]	558
	559	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
[937]	560	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , XMAX, YMAX, 4);
[628]	561	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
[937]	562	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", XMAX, YMAX, 4);
[628]	563
	564	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
[937]	565	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , XMAX, YMAX, 4);
[628]	566	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
[937]	567	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", XMAX, YMAX, 4);
[628]	568
	569	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
[937]	570	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , XMAX, YMAX, 4);
[628]	571	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
[937]	572	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", XMAX, YMAX, 4);
[628]	573
	574	// VCI signals for iobus and peripherals
	575	VciSignals<vci_param_int> signal_vci_ini_bdev("signal_vci_ini_bdev");
	576	VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
	577	VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
	578
[792]	579	VciSignals<vci_param_int>* signal_vci_ini_proc =
[628]	580	alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
	581
	582	VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
	583	VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
	584	VciSignals<vci_param_int> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
	585	VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
	586	VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
	587	VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
	588	VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
	589	VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
	590
	591	VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
	592	VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
[792]	593
[621]	594	////////////////////////////
[792]	595	// Loader
[621]	596	////////////////////////////
	597
[796]	598	#if USE_IOC_RDK
[795]	599	std::ostringstream ramdisk_name;
	600	ramdisk_name << disk_name << "@" << std::hex << SEG_RDK_BASE << ":";
	601	soclib::common::Loader loader( soft_name, ramdisk_name.str().c_str() );
[664]	602	#else
[692]	603	soclib::common::Loader loader( soft_name );
[664]	604	#endif
[937]	605
[939]	606	loader.memory_default(0x55);
[621]	607
	608	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
[630]	609	proc_iss::set_loader( loader );
[621]	610
[664]	611	//////////////////////////////////////////////////////////////
[937]	612	// mesh construction: XMAX * YMAX clusters
[664]	613	//////////////////////////////////////////////////////////////
[621]	614
	615	TsarLetiCluster<dspin_cmd_width,
	616	dspin_rsp_width,
	617	vci_param_int,
[937]	618	vci_param_ext>* clusters[XMAX][YMAX];
[621]	619
	620	#if USE_OPENMP
	621	#pragma omp parallel
	622	{
	623	#pragma omp for
	624	#endif
[937]	625	for (size_t i = 0; i < (XMAX * YMAX); i++)
[621]	626	{
[937]	627	size_t x = i / (YMAX);
	628	size_t y = i % (YMAX);
[621]	629
	630	#if USE_OPENMP
	631	#pragma omp critical
	632	{
	633	#endif
	634	std::cout << std::endl;
[792]	635	std::cout << "Cluster_" << std::dec << x << "_" << y
[628]	636	<< " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
[621]	637	std::cout << std::endl;
	638
[664]	639	std::ostringstream cluster_name;
	640	cluster_name << "cluster_" << std::dec << x << "_" << y;
	641
[621]	642	clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
	643	dspin_rsp_width,
	644	vci_param_int,
	645	vci_param_ext>
	646	(
[664]	647	cluster_name.str().c_str(),
[621]	648	NB_PROCS_MAX,
	649	x,
	650	y,
	651	cluster(x,y),
	652	maptabd,
	653	maptabx,
	654	RESET_ADDRESS,
	655	X_WIDTH,
	656	Y_WIDTH,
	657	vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
[803]	658	P_WIDTH,
[621]	659	MEMC_TGTID,
	660	XICU_TGTID,
	661	MTTY_TGTID,
	662	BDEV_TGTID,
[692]	663	disk_name,
[621]	664	MEMC_WAYS,
	665	MEMC_SETS,
	666	L1_IWAYS,
	667	L1_ISETS,
	668	L1_DWAYS,
	669	L1_DSETS,
	670	XRAM_LATENCY,
	671	loader,
	672	frozen_cycles,
	673	trace_from,
[792]	674	trace_proc_ok,
[621]	675	trace_proc_id,
[792]	676	trace_memc_ok,
[621]	677	trace_memc_id
	678	);
	679
	680	#if USE_OPENMP
	681	} // end critical
	682	#endif
	683	} // end for
	684	#if USE_OPENMP
	685	}
	686	#endif
	687
[937]	688	#if USE_PIC
[826]	689
[628]	690	//////////////////////////////////////////////////////////////////
[937]	691	// IO bus and external peripherals in cluster[X_SIZE-1][Y_SIZE-1]
[664]	692	// - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
	693	// - 3 local initiators : IOC, CMA, PIC
	694	// There is no PROC, no MEMC and no XICU in this cluster,
	695	// but the crossbar has (NB_PROCS_MAX + 3) intiators and
	696	// 8 targets, in order to use the same SRCID and TGTID space
[792]	697	// (same mapping table for the internal components,
	698	// and for the external peripherals)
[628]	699	//////////////////////////////////////////////////////////////////
[621]	700
[664]	701	std::cout << std::endl;
	702	std::cout << " Building IO cluster (external peripherals)" << std::endl;
	703	std::cout << std::endl;
[792]	704
[937]	705	size_t cluster_io = cluster(XMAX-1, YMAX);
[621]	706
[792]	707	//////////// vci_local_crossbar
[628]	708	VciLocalCrossbar<vci_param_int>*
	709	iobus = new VciLocalCrossbar<vci_param_int>(
	710	"iobus",
	711	maptabd, // mapping table
	712	cluster_io, // cluster_xy
	713	NB_PROCS_MAX + 3, // number of local initiators
	714	8, // number of local targets
	715	BDEV_TGTID ); // default target index
[621]	716
[792]	717	//////////// vci_framebuffer
[628]	718	VciFrameBuffer<vci_param_int>*
	719	fbuf = new VciFrameBuffer<vci_param_int>(
	720	"fbuf",
	721	IntTab(cluster_io, FBUF_TGTID),
	722	maptabd,
	723	FBUF_X_SIZE, FBUF_Y_SIZE );
[621]	724
[792]	725	//////////// vci_block_device
[628]	726	VciBlockDeviceTsar<vci_param_int>*
	727	bdev = new VciBlockDeviceTsar<vci_param_int>(
	728	"bdev",
	729	maptabd,
	730	IntTab(cluster_io, BDEV_SRCID),
	731	IntTab(cluster_io, BDEV_TGTID),
[692]	732	disk_name,
[628]	733	512, // block size
	734	64 ); // burst size
	735
[792]	736	//////////// vci_multi_nic
[628]	737	VciMultiNic<vci_param_int>*
	738	mnic = new VciMultiNic<vci_param_int>(
[681]	739	"mnic",
[628]	740	IntTab(cluster_io, MNIC_TGTID),
	741	maptabd,
	742	NB_NIC_CHANNELS,
[937]	743	0, // default MAC_4 address
	744	0, // default MAC_2 address
	745	1 ); // NIC_MODE_SYNTHESIS
[628]	746
[792]	747	///////////// vci_chbuf_dma
[628]	748	VciChbufDma<vci_param_int>*
	749	cdma = new VciChbufDma<vci_param_int>(
	750	"cdma",
	751	maptabd,
	752	IntTab(cluster_io, CDMA_SRCID),
	753	IntTab(cluster_io, CDMA_TGTID),
[937]	754	64, // burst size
[792]	755	NB_CMA_CHANNELS );
[628]	756
	757	////////////// vci_multi_tty
	758	std::vector<std::string> vect_names;
	759	for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
	760	{
	761	std::ostringstream term_name;
	762	term_name << "ext_" << id;
	763	vect_names.push_back(term_name.str().c_str());
	764	}
	765
[792]	766	VciMultiTty<vci_param_int>*
[628]	767	mtty = new VciMultiTty<vci_param_int>(
	768	"mtty",
	769	IntTab(cluster_io, MTTY_TGTID),
	770	maptabd,
	771	vect_names );
	772
	773	///////////// vci_iopic
	774	VciIopic<vci_param_int>*
	775	iopic = new VciIopic<vci_param_int>(
	776	"iopic",
	777	maptabd,
	778	IntTab(cluster_io, IOPI_SRCID),
	779	IntTab(cluster_io, IOPI_TGTID),
[792]	780	32 );
[628]	781
[792]	782	////////////// vci_dspin wrappers
[628]	783	VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	784	wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
[937]	785	"wt_iobus",
[628]	786	vci_srcid_width );
	787
	788	VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	789	wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
[937]	790	"wi_iobus",
[628]	791	vci_srcid_width );
	792
	793	///////////////////////////////////////////////////////////////
[937]	794	// IObus Net-list
[628]	795	///////////////////////////////////////////////////////////////
	796
[792]	797	// iobus
	798	iobus->p_clk (signal_clk);
[628]	799	iobus->p_resetn (signal_resetn);
	800
	801	iobus->p_target_to_up (signal_vci_cmd_from_noc);
	802	iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
	803
	804	iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
	805	iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
	806	iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
	807	iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
	808	iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
	809	iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev);
	810	iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
	811	iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
	812
	813	for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
	814	{
	815	iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
	816	}
	817	iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev);
	818	iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
	819	iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
	820
	821	std::cout << " - IOBUS connected" << std::endl;
	822
	823	// block_device
	824	bdev->p_clk (signal_clk);
	825	bdev->p_resetn (signal_resetn);
	826	bdev->p_vci_target (signal_vci_tgt_bdev);
	827	bdev->p_vci_initiator (signal_vci_ini_bdev);
	828	bdev->p_irq (signal_irq_bdev);
	829
	830	std::cout << " - BDEV connected" << std::endl;
	831
	832	// frame_buffer
	833	fbuf->p_clk (signal_clk);
	834	fbuf->p_resetn (signal_resetn);
	835	fbuf->p_vci (signal_vci_tgt_fbuf);
	836
	837	std::cout << " - FBUF connected" << std::endl;
	838
	839	// multi_nic
	840	mnic->p_clk (signal_clk);
	841	mnic->p_resetn (signal_resetn);
	842	mnic->p_vci (signal_vci_tgt_mnic);
	843	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
	844	{
	845	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
	846	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
	847	}
	848
	849	std::cout << " - MNIC connected" << std::endl;
	850
	851	// chbuf_dma
	852	cdma->p_clk (signal_clk);
	853	cdma->p_resetn (signal_resetn);
	854	cdma->p_vci_target (signal_vci_tgt_cdma);
	855	cdma->p_vci_initiator (signal_vci_ini_cdma);
	856	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
	857	{
	858	cdma->p_irq[i] (signal_irq_cdma[i]);
	859	}
	860
	861	std::cout << " - CDMA connected" << std::endl;
	862
	863	// multi_tty
	864	mtty->p_clk (signal_clk);
	865	mtty->p_resetn (signal_resetn);
	866	mtty->p_vci (signal_vci_tgt_mtty);
	867	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
	868	{
[664]	869	mtty->p_irq[i] (signal_irq_mtty_rx[i]);
[628]	870	}
	871
	872	std::cout << " - MTTY connected" << std::endl;
	873
	874	// iopic
[664]	875	// NB_NIC_CHANNELS <= 2
	876	// NB_CMA_CHANNELS <= 4
[937]	877	// NB_TTY_CHANNELS <= 16
[628]	878	iopic->p_clk (signal_clk);
	879	iopic->p_resetn (signal_resetn);
	880	iopic->p_vci_target (signal_vci_tgt_iopi);
	881	iopic->p_vci_initiator (signal_vci_ini_iopi);
[664]	882	for ( size_t i=0 ; i<32 ; i++)
[628]	883	{
	884	if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
	885	else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
	886	else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
	887	else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
	888	else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
[664]	889	else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
	890	else if(i == 8) iopic->p_hwi[i] (signal_irq_bdev);
	891	else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
	892	else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
[628]	893	else iopic->p_hwi[i] (signal_irq_false);
	894	}
	895
[664]	896	std::cout << " - IOPIC connected" << std::endl;
	897
[628]	898	// vci/dspin wrappers
	899	wi_iobus->p_clk (signal_clk);
	900	wi_iobus->p_resetn (signal_resetn);
	901	wi_iobus->p_vci (signal_vci_cmd_to_noc);
[937]	902	wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH]);
	903	wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH]);
[628]	904
	905	// vci/dspin wrappers
	906	wt_iobus->p_clk (signal_clk);
	907	wt_iobus->p_resetn (signal_resetn);
	908	wt_iobus->p_vci (signal_vci_cmd_from_noc);
[937]	909	wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH]);
	910	wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH]);
[628]	911
[937]	912	#endif // USE_PIC
[826]	913
[628]	914	// Clock & RESET for clusters
[937]	915	for (size_t x = 0; x < (XMAX); x++)
[628]	916	{
[937]	917	for (size_t y = 0; y < (YMAX); y++)
[628]	918	{
	919	clusters[x][y]->p_clk (signal_clk);
	920	clusters[x][y]->p_resetn (signal_resetn);
	921	}
	922	}
	923
	924	// Inter Clusters horizontal connections
[937]	925	if (XMAX > 1)
[628]	926	{
[937]	927	for (size_t x = 0; x < (XMAX-1); x++)
[628]	928	{
[937]	929	for (size_t y = 0; y < (YMAX); y++)
[628]	930	{
	931	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
	932	clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
	933	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
	934	clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
	935
	936	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
	937	clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
	938	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
	939	clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
	940
	941	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
	942	clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
	943	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
	944	clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
	945
	946	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
	947	clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
	948	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
	949	clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
	950
	951	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
	952	clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
	953	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
	954	clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
[621]	955	}
[628]	956	}
	957	}
[792]	958	std::cout << std::endl << "Horizontal connections done" << std::endl;
[621]	959
[628]	960	// Inter Clusters vertical connections
[937]	961	if (YMAX > 1)
[628]	962	{
[937]	963	for (size_t y = 0; y < (YMAX-1); y++)
[628]	964	{
[937]	965	for (size_t x = 0; x < XMAX; x++)
[628]	966	{
	967	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
	968	clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
	969	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
	970	clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
	971
	972	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
	973	clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
	974	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
	975	clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
	976
	977	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
	978	clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
	979	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
	980	clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
	981
	982	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
	983	clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
	984	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
	985	clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
	986
	987	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
	988	clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
	989	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
	990	clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
[621]	991	}
[628]	992	}
	993	}
	994	std::cout << std::endl << "Vertical connections done" << std::endl;
[621]	995
[628]	996	// East & West boundary cluster connections
[937]	997	for (size_t y = 0; y < (YMAX); y++)
[628]	998	{
	999	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
	1000	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
[937]	1001	clusters[XMAX-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[XMAX-1][y][EAST]);
	1002	clusters[XMAX-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[XMAX-1][y][EAST]);
[621]	1003
[628]	1004	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
	1005	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
[937]	1006	clusters[XMAX-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[XMAX-1][y][EAST]);
	1007	clusters[XMAX-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[XMAX-1][y][EAST]);
[621]	1008
[628]	1009	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
	1010	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
[937]	1011	clusters[XMAX-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[XMAX-1][y][EAST]);
	1012	clusters[XMAX-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[XMAX-1][y][EAST]);
[621]	1013
[628]	1014	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
	1015	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
[937]	1016	clusters[XMAX-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[XMAX-1][y][EAST]);
	1017	clusters[XMAX-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[XMAX-1][y][EAST]);
[621]	1018
[628]	1019	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
	1020	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
[937]	1021	clusters[XMAX-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[XMAX-1][y][EAST]);
	1022	clusters[XMAX-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[XMAX-1][y][EAST]);
[628]	1023	}
[621]	1024
[664]	1025	std::cout << std::endl << "West & East boundaries connections done" << std::endl;
	1026
[628]	1027	// North & South boundary clusters connections
[937]	1028	for (size_t x = 0; x < XMAX; x++)
[628]	1029	{
	1030	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
	1031	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
[937]	1032	clusters[x][YMAX-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][YMAX-1][NORTH]);
	1033	clusters[x][YMAX-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][YMAX-1][NORTH]);
[621]	1034
[628]	1035	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
	1036	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
[937]	1037	clusters[x][YMAX-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][YMAX-1][NORTH]);
	1038	clusters[x][YMAX-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][YMAX-1][NORTH]);
[621]	1039
[628]	1040	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
	1041	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
[937]	1042	clusters[x][YMAX-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][YMAX-1][NORTH]);
	1043	clusters[x][YMAX-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][YMAX-1][NORTH]);
[621]	1044
[628]	1045	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
	1046	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
[937]	1047	clusters[x][YMAX-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][YMAX-1][NORTH]);
	1048	clusters[x][YMAX-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][YMAX-1][NORTH]);
[628]	1049
	1050	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
	1051	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
[937]	1052	clusters[x][YMAX-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][YMAX-1][NORTH]);
	1053	clusters[x][YMAX-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][YMAX-1][NORTH]);
[628]	1054	}
	1055
[664]	1056	std::cout << std::endl << "North & South boundaries connections done" << std::endl;
	1057
[628]	1058	std::cout << std::endl;
	1059
	1060	////////////////////////////////////////////////////////
	1061	// Simulation
	1062	///////////////////////////////////////////////////////
	1063
	1064	sc_start(sc_core::sc_time(0, SC_NS));
	1065	signal_resetn = false;
	1066	signal_irq_false = false;
	1067
	1068	// set network boundaries signals default values
	1069	// for all boundary clusters but the IO cluster
[937]	1070	for (size_t x = 0; x < XMAX ; x++)
[628]	1071	{
[937]	1072	for (size_t y = 0; y < YMAX ; y++)
[628]	1073	{
	1074	for (size_t face = 0; face < 4; face++)
	1075	{
[937]	1076	if ( (x != XMAX-1) or (y != YMAX-1) or (face != NORTH) )
[628]	1077	{
	1078	signal_dspin_bound_cmd_in [x][y][face].write = false;
	1079	signal_dspin_bound_cmd_in [x][y][face].read = true;
	1080	signal_dspin_bound_cmd_out[x][y][face].write = false;
	1081	signal_dspin_bound_cmd_out[x][y][face].read = true;
	1082
	1083	signal_dspin_bound_rsp_in [x][y][face].write = false;
	1084	signal_dspin_bound_rsp_in [x][y][face].read = true;
	1085	signal_dspin_bound_rsp_out[x][y][face].write = false;
	1086	signal_dspin_bound_rsp_out[x][y][face].read = true;
	1087	}
	1088
	1089	signal_dspin_bound_m2p_in [x][y][face].write = false;
	1090	signal_dspin_bound_m2p_in [x][y][face].read = true;
	1091	signal_dspin_bound_m2p_out[x][y][face].write = false;
	1092	signal_dspin_bound_m2p_out[x][y][face].read = true;
	1093
	1094	signal_dspin_bound_p2m_in [x][y][face].write = false;
	1095	signal_dspin_bound_p2m_in [x][y][face].read = true;
	1096	signal_dspin_bound_p2m_out[x][y][face].write = false;
	1097	signal_dspin_bound_p2m_out[x][y][face].read = true;
	1098
	1099	signal_dspin_bound_cla_in [x][y][face].write = false;
	1100	signal_dspin_bound_cla_in [x][y][face].read = true;
	1101	signal_dspin_bound_cla_out[x][y][face].write = false;
	1102	signal_dspin_bound_cla_out[x][y][face].read = true;
[621]	1103	}
[628]	1104	}
	1105	}
[621]	1106
[826]	1107	#if USE_PIC == 0
[937]	1108	signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH].write = false;
	1109	signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH].read = true;
	1110	signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH].read = true;
	1111	signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH].write = false;
[826]	1112	#endif
	1113
[792]	1114	// set default values for VCI signals connected to unused ports on iobus
[664]	1115	signal_vci_tgt_memc.rspval = false;
	1116	signal_vci_tgt_xicu.rspval = false;
	1117	for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
	1118
[628]	1119	sc_start(sc_core::sc_time(1, SC_NS));
	1120	signal_resetn = true;
[621]	1121
[792]	1122	if (gettimeofday(&t1, NULL) != 0)
[628]	1123	{
	1124	perror("gettimeofday");
	1125	return EXIT_FAILURE;
	1126	}
[621]	1127
[937]	1128	// simulation loop
[664]	1129	for (uint64_t n = 1; n < ncycles && !stop_called; n++)
	1130	{
[937]	1131	// Monitor a specific address for L1 cache
[664]	1132	// clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
[621]	1133
[937]	1134	// Monitor a specific address for L2 cache
[939]	1135	// clusters[0][0]->memc->cache_monitor( 0x0000201E00ULL );
[937]	1136
	1137	// Monitor a specific address for one XRAM
[939]	1138	// clusters[0][0]->xram->start_monitor( 0x0000201E00ULL , 64);
[937]	1139
[664]	1140	// stats display
	1141	if( (n % 5000000) == 0)
	1142	{
[621]	1143
[792]	1144	if (gettimeofday(&t2, NULL) != 0)
[664]	1145	{
	1146	perror("gettimeofday");
	1147	return EXIT_FAILURE;
	1148	}
[621]	1149
[664]	1150	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
	1151	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
[792]	1152	std::cerr << "platform clock frequency "
[664]	1153	<< (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
[621]	1154
[792]	1155	if (gettimeofday(&t1, NULL) != 0)
[664]	1156	{
	1157	perror("gettimeofday");
	1158	return EXIT_FAILURE;
	1159	}
	1160	}
[621]	1161
[664]	1162	// trace display
	1163	if ( trace_ok and (n > trace_from) )
	1164	{
	1165	std::cout << "****************** cycle " << std::dec << n ;
[937]	1166	std::cout << " ********************************************" << std::endl;
[621]	1167
[664]	1168	size_t l = 0;
	1169	size_t x = 0;
	1170	size_t y = 0;
[621]	1171
[664]	1172	if ( trace_proc_ok )
	1173	{
[803]	1174	l = trace_proc_id & ((1<<P_WIDTH)-1) ;
	1175	x = (trace_proc_id >> P_WIDTH) >> Y_WIDTH ;
	1176	y = (trace_proc_id >> P_WIDTH) & ((1<<Y_WIDTH) - 1);
[621]	1177
[664]	1178	std::ostringstream proc_signame;
	1179	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
[681]	1180	clusters[x][y]->proc[l]->print_trace(1);
[664]	1181	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
[628]	1182
[664]	1183	std::ostringstream xicu_signame;
	1184	xicu_signame << "[SIG]XICU_" << x << "_" << y ;
	1185	clusters[x][y]->xicu->print_trace(0);
	1186	clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
[937]	1187
	1188	if ( clusters[x][y]->signal_proc_irq[0] )
	1189	std::cout << "### IRQ_PROC_" << x << "_" << y << "_0" << std::endl;
	1190	if ( clusters[x][y]->signal_proc_irq[4] )
	1191	std::cout << "### IRQ_PROC_" << x << "_" << y << "_1" << std::endl;
	1192	if ( clusters[x][y]->signal_proc_irq[8] )
	1193	std::cout << "### IRQ_PROC_" << x << "_" << y << "_2" << std::endl;
	1194	if ( clusters[x][y]->signal_proc_irq[12] )
	1195	std::cout << "### IRQ_PROC_" << x << "_" << y << "_3" << std::endl;
[664]	1196	}
[628]	1197
[664]	1198	if ( trace_memc_ok )
	1199	{
	1200	x = trace_memc_id >> Y_WIDTH;
	1201	y = trace_memc_id & ((1<<Y_WIDTH) - 1);
	1202
	1203	std::ostringstream smemc;
	1204	smemc << "[SIG]MEMC_" << x << "_" << y;
	1205	std::ostringstream sxram;
	1206	sxram << "[SIG]XRAM_" << x << "_" << y;
	1207
	1208	clusters[x][y]->memc->print_trace();
	1209	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
	1210	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
[792]	1211	}
[664]	1212
	1213	// trace coherence signals
	1214	// clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
	1215	// clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
	1216	// clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
	1217	// clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
	1218
	1219	// clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
	1220	// clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
	1221	// clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
	1222	// clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
	1223
	1224	// trace xbar(s) m2p
	1225	// clusters[0][0]->xbar_m2p->print_trace();
	1226	// clusters[1][0]->xbar_m2p->print_trace();
	1227	// clusters[0][1]->xbar_m2p->print_trace();
	1228	// clusters[1][1]->xbar_m2p->print_trace();
[792]	1229
[664]	1230	// trace router(s) m2p
	1231	// clusters[0][0]->router_m2p->print_trace();
	1232	// clusters[1][0]->router_m2p->print_trace();
	1233	// clusters[0][1]->router_m2p->print_trace();
	1234	// clusters[1][1]->router_m2p->print_trace();
[792]	1235
[826]	1236	#if USE_PIC
[664]	1237	// trace external ioc
	1238	bdev->print_trace();
	1239	signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
	1240	signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
[621]	1241
[664]	1242	// trace external iopic
	1243	iopic->print_trace();
	1244	signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
	1245	signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
[937]	1246
	1247	// trace external interrupts
	1248	if (signal_irq_bdev) std::cout << "### IRQ_BDEV" << std::endl;
[897]	1249	#else
	1250	clusters[0][0]->bdev->print_trace();
	1251	clusters[0][0]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_0_0");
	1252	clusters[0][0]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_0_0");
[826]	1253	#endif
[621]	1254
[664]	1255	} // end trace
[621]	1256
[664]	1257	sc_start(sc_core::sc_time(1, SC_NS));
	1258	}
	1259	// Free memory
[681]	1260	for (size_t i = 0 ; i < (X_SIZE * Y_SIZE) ; i++)
[664]	1261	{
[681]	1262	size_t x = i / (Y_SIZE);
	1263	size_t y = i % (Y_SIZE);
[664]	1264	delete clusters[x][y];
	1265	}
	1266
	1267	return EXIT_SUCCESS;
[621]	1268	}
	1269
[792]	1270	void handler(int dummy = 0)
[628]	1271	{
[621]	1272	stop_called = true;
	1273	sc_stop();
	1274	}
	1275
	1276	void voidhandler(int dummy = 0) {}
	1277
	1278	int sc_main (int argc, char *argv[])
	1279	{
	1280	signal(SIGINT, handler);
	1281	signal(SIGPIPE, voidhandler);
	1282
	1283	try {
	1284	return _main(argc, argv);
	1285	} catch (std::exception &e) {
	1286	std::cout << e.what() << std::endl;
	1287	} catch (...) {
	1288	std::cout << "Unknown exception occured" << std::endl;
	1289	throw;
	1290	}
	1291	return 1;
	1292	}
	1293
	1294
	1295	// Local Variables:
	1296	// tab-width: 3
	1297	// c-basic-offset: 3
	1298	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	1299	// indent-tabs-mode: nil
	1300	// End:
	1301
	1302	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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