[344] | 1 | ///////////////////////////////////////////////////////////////////////// |
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| 2 | // File: top.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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[396] | 5 | // Date : may 2013 |
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[344] | 6 | // This program is released under the GNU public license |
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| 7 | ///////////////////////////////////////////////////////////////////////// |
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[396] | 8 | // This file define a generic TSAR architecture. |
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| 9 | // The physical address space is 40 bits. |
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| 10 | // |
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[344] | 11 | // The number of clusters cannot be larger than 256. |
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| 12 | // The number of processors per cluster cannot be larger than 8. |
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| 13 | // |
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| 14 | // - It uses four dspin_local_crossbar per cluster as local interconnect |
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| 15 | // - It uses two virtual_dspin routers per cluster as global interconnect |
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| 16 | // - It uses the vci_cc_vcache_wrapper |
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| 17 | // - It uses the vci_mem_cache |
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[396] | 18 | // - It contains one vci_xicu per cluster. |
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| 19 | // - It contains one vci_multi_dma per cluster. |
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| 20 | // - It contains one vci_simple_ram per cluster to model the L3 cache. |
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[344] | 21 | // |
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[396] | 22 | // The communication between the MemCache and the Xram is 64 bits. |
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| 23 | // |
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| 24 | // All clusters are identical, but the cluster 0 (called io_cluster), |
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[493] | 25 | // contains 6 extra components: |
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[344] | 26 | // - the boot rom (BROM) |
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| 27 | // - the disk controller (BDEV) |
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| 28 | // - the multi-channel network controller (MNIC) |
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[493] | 29 | // - the multi-channel chained buffer dma controller (CDMA) |
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[344] | 30 | // - the multi-channel tty controller (MTTY) |
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| 31 | // - the frame buffer controller (FBUF) |
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| 32 | // |
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[396] | 33 | // It is build with one single component implementing a cluster, |
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| 34 | // defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) |
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[344] | 35 | // |
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| 36 | // The IRQs are connected to XICUs as follow: |
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| 37 | // - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. |
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| 38 | // - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. |
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| 39 | // - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. |
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| 40 | // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. |
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| 41 | // |
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[396] | 42 | // Some hardware parameters are used when compiling the OS, and are used |
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| 43 | // by this top.cpp file. They must be defined in the hard_config.h file : |
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[344] | 44 | // - CLUSTER_X : number of clusters in a row (power of 2) |
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| 45 | // - CLUSTER_Y : number of clusters in a column (power of 2) |
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| 46 | // - CLUSTER_SIZE : size of the segment allocated to a cluster |
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| 47 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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[438] | 48 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) |
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| 49 | // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) |
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| 50 | // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) |
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[344] | 51 | // |
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[396] | 52 | // Some other hardware parameters are not used when compiling the OS, |
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| 53 | // and can be directly defined in this top.cpp file: |
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[344] | 54 | // - XRAM_LATENCY : external ram latency |
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| 55 | // - MEMC_WAYS : L2 cache number of ways |
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| 56 | // - MEMC_SETS : L2 cache number of sets |
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| 57 | // - L1_IWAYS |
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| 58 | // - L1_ISETS |
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| 59 | // - L1_DWAYS |
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| 60 | // - L1_DSETS |
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| 61 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 62 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 63 | // - BDEV_SECTOR_SIZE : block size for block drvice |
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| 64 | // - BDEV_IMAGE_NAME : file pathname for block device |
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| 65 | // - NIC_RX_NAME : file pathname for NIC received packets |
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| 66 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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| 67 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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[396] | 68 | ///////////////////////////////////////////////////////////////////////// |
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| 69 | // General policy for 40 bits physical address decoding: |
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| 70 | // All physical segments base addresses are multiple of 1 Mbytes |
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| 71 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[344] | 72 | // The (x_width + y_width) MSB bits (left aligned) define |
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[396] | 73 | // the cluster index, and the LADR bits define the local index: |
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[344] | 74 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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[396] | 75 | // |x_width|y_width|---| 8 | 24 | |
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[344] | 76 | ///////////////////////////////////////////////////////////////////////// |
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[396] | 77 | // General policy for 14 bits SRCID decoding: |
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| 78 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 79 | // | X_ID | Y_ID |---| L_ID | |
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| 80 | // |x_width|y_width|---| 6 | |
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| 81 | ///////////////////////////////////////////////////////////////////////// |
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[344] | 82 | |
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| 83 | #include <systemc> |
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| 84 | #include <sys/time.h> |
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| 85 | #include <iostream> |
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| 86 | #include <sstream> |
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| 87 | #include <cstdlib> |
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| 88 | #include <cstdarg> |
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| 89 | #include <stdint.h> |
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| 90 | |
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| 91 | #include "gdbserver.h" |
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| 92 | #include "mapping_table.h" |
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[663] | 93 | #include "alloc_elems.h" |
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[378] | 94 | #include "tsar_xbar_cluster.h" |
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[344] | 95 | |
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[663] | 96 | #define USE_ALMOS 1 |
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| 97 | //#define USE_GIET |
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[344] | 98 | |
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[464] | 99 | #ifdef USE_ALMOS |
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| 100 | #ifdef USE_GIET |
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| 101 | #error "Can't use Two different OS" |
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| 102 | #endif |
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| 103 | #endif |
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| 104 | |
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| 105 | #ifndef USE_ALMOS |
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| 106 | #ifndef USE_GIET |
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| 107 | #error "You need to specify one OS" |
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| 108 | #endif |
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| 109 | #endif |
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| 110 | |
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[663] | 111 | #ifdef USE_ALMOS |
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| 112 | #define PREFIX_OS "almos/" |
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| 113 | #include "almos/hard_config.h" |
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| 114 | #endif |
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| 115 | #ifdef USE_GIET |
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| 116 | #define PREFIX_OS "giet_vm/" |
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| 117 | #endif |
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| 118 | |
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[344] | 119 | /////////////////////////////////////////////////// |
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| 120 | // Parallelisation |
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| 121 | /////////////////////////////////////////////////// |
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[663] | 122 | |
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[344] | 123 | |
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| 124 | #if USE_OPENMP |
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| 125 | #include <omp.h> |
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| 126 | #endif |
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| 127 | |
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[1012] | 128 | // nluster index (computed from x,y coordinates) |
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[619] | 129 | #ifdef USE_ALMOS |
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[663] | 130 | #define cluster(x,y) (y + x * Y_SIZE) |
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[619] | 131 | #else |
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[663] | 132 | #define cluster(x,y) (y + (x << Y_WIDTH)) |
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[619] | 133 | #endif |
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[344] | 134 | |
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[619] | 135 | |
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[547] | 136 | #define min(x, y) (x < y ? x : y) |
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| 137 | |
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[344] | 138 | /////////////////////////////////////////////////////////// |
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| 139 | // DSPIN parameters |
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| 140 | /////////////////////////////////////////////////////////// |
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| 141 | |
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[404] | 142 | #define dspin_cmd_width 39 |
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| 143 | #define dspin_rsp_width 32 |
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[344] | 144 | |
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[396] | 145 | /////////////////////////////////////////////////////////// |
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| 146 | // VCI parameters |
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| 147 | /////////////////////////////////////////////////////////// |
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| 148 | |
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[438] | 149 | #define vci_cell_width_int 4 |
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| 150 | #define vci_cell_width_ext 8 |
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[396] | 151 | |
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[504] | 152 | #ifdef USE_ALMOS |
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| 153 | #define vci_address_width 32 |
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| 154 | #endif |
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| 155 | #ifdef USE_GIET |
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| 156 | #define vci_address_width 40 |
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| 157 | #endif |
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[438] | 158 | #define vci_plen_width 8 |
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| 159 | #define vci_rerror_width 1 |
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| 160 | #define vci_clen_width 1 |
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| 161 | #define vci_rflag_width 1 |
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| 162 | #define vci_srcid_width 14 |
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| 163 | #define vci_pktid_width 4 |
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| 164 | #define vci_trdid_width 4 |
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| 165 | #define vci_wrplen_width 1 |
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[493] | 166 | |
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[344] | 167 | //////////////////////////////////////////////////////////// |
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[396] | 168 | // Secondary Hardware Parameters |
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[344] | 169 | //////////////////////i///////////////////////////////////// |
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| 170 | |
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[438] | 171 | |
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[344] | 172 | #define XRAM_LATENCY 0 |
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| 173 | |
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| 174 | #define MEMC_WAYS 16 |
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| 175 | #define MEMC_SETS 256 |
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| 176 | |
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| 177 | #define L1_IWAYS 4 |
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| 178 | #define L1_ISETS 64 |
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| 179 | |
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| 180 | #define L1_DWAYS 4 |
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| 181 | #define L1_DSETS 64 |
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| 182 | |
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[464] | 183 | #ifdef USE_ALMOS |
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[663] | 184 | #define FBUF_X_SIZE 1024 |
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| 185 | #define FBUF_Y_SIZE 1024 |
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[464] | 186 | #endif |
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| 187 | #ifdef USE_GIET |
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[344] | 188 | #define FBUF_X_SIZE 128 |
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| 189 | #define FBUF_Y_SIZE 128 |
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[464] | 190 | #endif |
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[344] | 191 | |
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[464] | 192 | #ifdef USE_GIET |
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[344] | 193 | #define BDEV_SECTOR_SIZE 512 |
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[468] | 194 | #define BDEV_IMAGE_NAME PREFIX_OS"display/images.raw" |
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[464] | 195 | #endif |
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| 196 | #ifdef USE_ALMOS |
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| 197 | #define BDEV_SECTOR_SIZE 4096 |
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| 198 | #define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin" |
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| 199 | #endif |
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[344] | 200 | |
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[464] | 201 | #define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt" |
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| 202 | #define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt" |
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[344] | 203 | #define NIC_TIMEOUT 10000 |
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| 204 | |
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[438] | 205 | #define NORTH 0 |
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| 206 | #define SOUTH 1 |
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| 207 | #define EAST 2 |
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| 208 | #define WEST 3 |
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| 209 | |
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[344] | 210 | //////////////////////////////////////////////////////////// |
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| 211 | // Software to be loaded in ROM & RAM |
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| 212 | //////////////////////i///////////////////////////////////// |
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| 213 | |
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[464] | 214 | #ifdef USE_ALMOS |
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[1012] | 215 | #define soft_name PREFIX_OS"preloader.elf" |
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[464] | 216 | #endif |
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| 217 | #ifdef USE_GIET |
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[468] | 218 | #define soft_pathname PREFIX_OS"soft.elf" |
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[464] | 219 | #endif |
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[344] | 220 | |
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| 221 | //////////////////////////////////////////////////////////// |
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| 222 | // DEBUG Parameters default values |
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| 223 | //////////////////////i///////////////////////////////////// |
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| 224 | |
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[663] | 225 | #define MAX_FROZEN_CYCLES 100000000 |
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[344] | 226 | |
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[572] | 227 | |
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| 228 | //////////////////////////////////////////////////////////////////// |
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| 229 | // TGTID definition in direct space |
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| 230 | // For all components: global TGTID = global SRCID = cluster_index |
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| 231 | //////////////////////////////////////////////////////////////////// |
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| 232 | |
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| 233 | |
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[344] | 234 | ///////////////////////////////////////////////////////// |
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| 235 | // Physical segments definition |
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| 236 | ///////////////////////////////////////////////////////// |
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| 237 | // There is 3 segments replicated in all clusters |
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| 238 | // and 5 specific segments in the "IO" cluster |
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| 239 | // (containing address 0xBF000000) |
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| 240 | ///////////////////////////////////////////////////////// |
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| 241 | |
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[547] | 242 | #ifdef USE_GIET |
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[1012] | 243 | #error "This platform is no more supported for the GIET" |
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[504] | 244 | #endif |
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[344] | 245 | |
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[504] | 246 | #ifdef USE_ALMOS |
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[572] | 247 | // 2^19 is the offset for the local id (8 bits for global ID : |
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| 248 | // 1 bit for Memcache or Peripheral, 4 for local peripheral id) |
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| 249 | // (Almos supports 32 bits physical addresses) |
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[504] | 250 | #endif |
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[344] | 251 | |
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[504] | 252 | bool stop_called = false; |
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| 253 | |
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[344] | 254 | ///////////////////////////////// |
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| 255 | int _main(int argc, char *argv[]) |
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| 256 | { |
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| 257 | using namespace sc_core; |
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| 258 | using namespace soclib::caba; |
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| 259 | using namespace soclib::common; |
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| 260 | |
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[663] | 261 | const int64_t max_cycles = 5000000; // Maximum number of cycles simulated in one sc_start call |
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| 262 | int64_t ncycles = 0x7FFFFFFFFFFFFFFF; // simulated cycles |
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| 263 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image |
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| 264 | char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file |
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| 265 | char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file |
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| 266 | ssize_t threads_nr = 1; // simulator's threads number |
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| 267 | bool debug_ok = false; // trace activated |
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| 268 | size_t debug_period = 1; // trace period |
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| 269 | size_t debug_memc_id = 0; // index of memc to be traced |
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| 270 | size_t debug_proc_id = 0; // index of proc to be traced |
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| 271 | int64_t debug_from = 0; // trace start cycle |
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| 272 | int64_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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[504] | 273 | size_t cluster_io_id; // index of cluster containing IOs |
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[663] | 274 | int64_t reset_counters = -1; |
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| 275 | int64_t dump_counters = -1; |
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| 276 | bool do_reset_counters = false; |
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| 277 | bool do_dump_counters = false; |
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| 278 | struct timeval t1, t2; |
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| 279 | uint64_t ms1, ms2; |
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[344] | 280 | |
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| 281 | ////////////// command line arguments ////////////////////// |
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| 282 | if (argc > 1) |
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| 283 | { |
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| 284 | for (int n = 1; n < argc; n = n + 2) |
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| 285 | { |
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[504] | 286 | if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) |
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[344] | 287 | { |
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[663] | 288 | ncycles = (int64_t) strtol(argv[n + 1], NULL, 0); |
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[344] | 289 | } |
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[504] | 290 | else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) |
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[344] | 291 | { |
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[464] | 292 | #ifdef USE_ALMOS |
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| 293 | assert( 0 && "Can't define almos soft name" ); |
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| 294 | #endif |
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| 295 | #ifdef USE_GIET |
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[504] | 296 | strcpy(soft_name, argv[n + 1]); |
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[464] | 297 | #endif |
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[344] | 298 | } |
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[504] | 299 | else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc)) |
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[344] | 300 | { |
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[504] | 301 | strcpy(disk_name, argv[n + 1]); |
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[344] | 302 | } |
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[504] | 303 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) |
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[344] | 304 | { |
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| 305 | debug_ok = true; |
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[663] | 306 | debug_from = (int64_t) strtol(argv[n + 1], NULL, 0); |
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[344] | 307 | } |
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[504] | 308 | else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) |
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[344] | 309 | { |
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[619] | 310 | debug_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); |
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| 311 | #ifdef USE_ALMOS |
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[663] | 312 | assert((debug_memc_id < (X_SIZE * Y_SIZE)) && |
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| 313 | "debug_memc_id larger than X_SIZE * Y_SIZE" ); |
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[619] | 314 | #else |
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| 315 | size_t x = debug_memc_id >> Y_WIDTH; |
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[836] | 316 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
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[619] | 317 | |
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[663] | 318 | assert( (x <= X_SIZE) and (y <= Y_SIZE) && |
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[619] | 319 | "MEMCID parameter refers a not valid memory cache"); |
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| 320 | #endif |
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[344] | 321 | } |
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[504] | 322 | else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc)) |
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[344] | 323 | { |
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[619] | 324 | debug_proc_id = (size_t) strtol(argv[n + 1], NULL, 0); |
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| 325 | #ifdef USE_ALMOS |
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[663] | 326 | assert((debug_proc_id < (X_SIZE * Y_SIZE * NB_PROCS_MAX)) && |
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| 327 | "debug_proc_id larger than X_SIZE * Y_SIZE * NB_PROCS"); |
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[619] | 328 | #else |
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| 329 | size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; |
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[836] | 330 | size_t x = cluster_xy >> Y_WIDTH; |
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| 331 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
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[619] | 332 | |
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[663] | 333 | assert( (x <= X_SIZE) and (y <= Y_SIZE) && |
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[619] | 334 | "PROCID parameter refers a not valid processor"); |
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| 335 | #endif |
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[344] | 336 | } |
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[504] | 337 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) |
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[344] | 338 | { |
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[619] | 339 | threads_nr = (ssize_t) strtol(argv[n + 1], NULL, 0); |
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[344] | 340 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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| 341 | } |
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[504] | 342 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) |
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[344] | 343 | { |
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[663] | 344 | frozen_cycles = (int64_t) strtol(argv[n + 1], NULL, 0); |
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[344] | 345 | } |
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[504] | 346 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc)) |
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[344] | 347 | { |
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[619] | 348 | debug_period = (size_t) strtol(argv[n + 1], NULL, 0); |
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[344] | 349 | } |
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[663] | 350 | else if ((strcmp(argv[n], "--reset-counters") == 0) && (n + 1 < argc)) |
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| 351 | { |
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| 352 | reset_counters = (int64_t) strtol(argv[n + 1], NULL, 0); |
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| 353 | do_reset_counters = true; |
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| 354 | } |
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| 355 | else if ((strcmp(argv[n], "--dump-counters") == 0) && (n + 1 < argc)) |
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| 356 | { |
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| 357 | dump_counters = (int64_t) strtol(argv[n + 1], NULL, 0); |
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| 358 | do_dump_counters = true; |
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| 359 | } |
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[344] | 360 | else |
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| 361 | { |
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| 362 | std::cout << " Arguments are (key,value) couples." << std::endl; |
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| 363 | std::cout << " The order is not important." << std::endl; |
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| 364 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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| 365 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
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| 366 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
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| 367 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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| 368 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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| 369 | std::cout << " -THREADS simulator's threads number" << std::endl; |
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| 370 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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| 371 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
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| 372 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
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| 373 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
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| 374 | exit(0); |
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| 375 | } |
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| 376 | } |
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| 377 | } |
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| 378 | |
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[396] | 379 | // checking hardware parameters |
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[663] | 380 | assert( ( (X_SIZE == 1) or (X_SIZE == 2) or (X_SIZE == 4) or |
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| 381 | (X_SIZE == 8) or (X_SIZE == 16) ) and |
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| 382 | "The X_SIZE parameter must be 1, 2, 4, 8 or 16" ); |
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[344] | 383 | |
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[663] | 384 | assert( ( (Y_SIZE == 1) or (Y_SIZE == 2) or (Y_SIZE == 4) or |
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| 385 | (Y_SIZE == 8) or (Y_SIZE == 16) ) and |
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| 386 | "The Y_SIZE parameter must be 1, 2, 4, 8 or 16" ); |
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[344] | 387 | |
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[396] | 388 | assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or |
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| 389 | (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and |
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| 390 | "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); |
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[344] | 391 | |
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[396] | 392 | assert( (NB_DMA_CHANNELS < 9) and |
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| 393 | "The NB_DMA_CHANNELS parameter must be smaller than 9" ); |
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[344] | 394 | |
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[396] | 395 | assert( (NB_TTY_CHANNELS < 15) and |
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| 396 | "The NB_TTY_CHANNELS parameter must be smaller than 15" ); |
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[344] | 397 | |
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[396] | 398 | assert( (NB_NIC_CHANNELS < 9) and |
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| 399 | "The NB_NIC_CHANNELS parameter must be smaller than 9" ); |
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[344] | 400 | |
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[464] | 401 | #ifdef USE_GIET |
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[438] | 402 | assert( (vci_address_width == 40) and |
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[504] | 403 | "VCI address width with the GIET must be 40 bits" ); |
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[464] | 404 | #endif |
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[344] | 405 | |
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[504] | 406 | #ifdef USE_ALMOS |
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| 407 | assert( (vci_address_width == 32) and |
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| 408 | "VCI address width with ALMOS must be 32 bits" ); |
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| 409 | #endif |
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| 410 | |
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| 411 | |
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[396] | 412 | std::cout << std::endl; |
---|
[663] | 413 | std::cout << " - X_SIZE = " << X_SIZE << std::endl; |
---|
| 414 | std::cout << " - Y_SIZE = " << Y_SIZE << std::endl; |
---|
[438] | 415 | std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; |
---|
[396] | 416 | std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; |
---|
[438] | 417 | std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; |
---|
| 418 | std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; |
---|
| 419 | std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; |
---|
| 420 | std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; |
---|
| 421 | std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; |
---|
| 422 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
---|
[396] | 423 | |
---|
| 424 | std::cout << std::endl; |
---|
| 425 | // Internal and External VCI parameters definition |
---|
[438] | 426 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 427 | vci_plen_width, |
---|
| 428 | vci_address_width, |
---|
| 429 | vci_rerror_width, |
---|
| 430 | vci_clen_width, |
---|
| 431 | vci_rflag_width, |
---|
| 432 | vci_srcid_width, |
---|
| 433 | vci_pktid_width, |
---|
| 434 | vci_trdid_width, |
---|
| 435 | vci_wrplen_width> vci_param_int; |
---|
[396] | 436 | |
---|
[438] | 437 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 438 | vci_plen_width, |
---|
| 439 | vci_address_width, |
---|
| 440 | vci_rerror_width, |
---|
| 441 | vci_clen_width, |
---|
| 442 | vci_rflag_width, |
---|
| 443 | vci_srcid_width, |
---|
| 444 | vci_pktid_width, |
---|
| 445 | vci_trdid_width, |
---|
| 446 | vci_wrplen_width> vci_param_ext; |
---|
[396] | 447 | |
---|
[344] | 448 | #if USE_OPENMP |
---|
| 449 | omp_set_dynamic(false); |
---|
| 450 | omp_set_num_threads(threads_nr); |
---|
| 451 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
| 452 | #endif |
---|
| 453 | |
---|
[663] | 454 | // Define parameters depending on mesh size |
---|
| 455 | size_t x_width; |
---|
| 456 | size_t y_width; |
---|
| 457 | |
---|
[619] | 458 | #ifdef USE_ALMOS |
---|
[663] | 459 | if (X_SIZE == 1) x_width = 0; |
---|
| 460 | else if (X_SIZE == 2) x_width = 1; |
---|
| 461 | else if (X_SIZE <= 4) x_width = 2; |
---|
| 462 | else if (X_SIZE <= 8) x_width = 3; |
---|
[504] | 463 | else x_width = 4; |
---|
[344] | 464 | |
---|
[663] | 465 | if (Y_SIZE == 1) y_width = 0; |
---|
| 466 | else if (Y_SIZE == 2) y_width = 1; |
---|
| 467 | else if (Y_SIZE <= 4) y_width = 2; |
---|
| 468 | else if (Y_SIZE <= 8) y_width = 3; |
---|
[504] | 469 | else y_width = 4; |
---|
[344] | 470 | |
---|
[619] | 471 | #else |
---|
| 472 | size_t x_width = X_WIDTH; |
---|
| 473 | size_t y_width = Y_WIDTH; |
---|
| 474 | |
---|
[1012] | 475 | assert((X_WIDTH <= 4) and (Y_WIDTH <= 4) and |
---|
[619] | 476 | "Up to 256 clusters"); |
---|
| 477 | |
---|
[1012] | 478 | assert((X_SIZE <= (1 << X_WIDTH)) and (Y_SIZE <= (1 << Y_WIDTH)) and |
---|
[619] | 479 | "The X_WIDTH and Y_WIDTH parameter are insufficient"); |
---|
| 480 | |
---|
[504] | 481 | #endif |
---|
| 482 | |
---|
[619] | 483 | // index of cluster containing IOs |
---|
| 484 | cluster_io_id = 0x00bfc00000ULL >> (vci_address_width - x_width - y_width); |
---|
| 485 | |
---|
[663] | 486 | |
---|
[344] | 487 | ///////////////////// |
---|
| 488 | // Mapping Tables |
---|
| 489 | ///////////////////// |
---|
| 490 | |
---|
[396] | 491 | // internal network |
---|
[438] | 492 | MappingTable maptabd(vci_address_width, |
---|
[572] | 493 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
[438] | 494 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
[547] | 495 | 0x00FF800000); |
---|
[344] | 496 | |
---|
[663] | 497 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[344] | 498 | { |
---|
[663] | 499 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[344] | 500 | { |
---|
[438] | 501 | sc_uint<vci_address_width> offset; |
---|
[1012] | 502 | offset = (sc_uint<vci_address_width>) cluster(x,y) |
---|
| 503 | << (vci_address_width - x_width - y_width); |
---|
[344] | 504 | |
---|
| 505 | std::ostringstream si; |
---|
[396] | 506 | si << "seg_xicu_" << x << "_" << y; |
---|
[1012] | 507 | maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE, |
---|
| 508 | IntTab(cluster(x,y), XCU_TGTID), false)); |
---|
[344] | 509 | |
---|
| 510 | std::ostringstream sd; |
---|
[396] | 511 | sd << "seg_mdma_" << x << "_" << y; |
---|
[1012] | 512 | maptabd.add(Segment(sd.str(), SEG_DMA_BASE + offset, SEG_DMA_SIZE, |
---|
| 513 | IntTab(cluster(x,y), DMA_TGTID), false)); |
---|
[344] | 514 | |
---|
[547] | 515 | std::ostringstream sh; |
---|
| 516 | sh << "seg_memc_" << x << "_" << y; |
---|
[1012] | 517 | maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE, |
---|
| 518 | IntTab(cluster(x,y), RAM_TGTID), true)); |
---|
[547] | 519 | |
---|
[344] | 520 | if ( cluster(x,y) == cluster_io_id ) |
---|
| 521 | { |
---|
[1012] | 522 | maptabd.add(Segment("seg_mtty", SEG_TTY_BASE, SEG_TTY_SIZE, |
---|
| 523 | IntTab(cluster(x,y),TTY_TGTID), false)); |
---|
| 524 | maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE, SEG_FBF_SIZE, |
---|
| 525 | IntTab(cluster(x,y),FBF_TGTID), false)); |
---|
| 526 | maptabd.add(Segment("seg_bdev", SEG_IOC_BASE, SEG_IOC_SIZE, |
---|
| 527 | IntTab(cluster(x,y),IOC_TGTID), false)); |
---|
| 528 | maptabd.add(Segment("seg_brom", SEG_ROM_BASE, SEG_ROM_SIZE, |
---|
| 529 | IntTab(cluster(x,y),ROM_TGTID), true)); |
---|
| 530 | maptabd.add(Segment("seg_mnic", SEG_NIC_BASE, SEG_NIC_SIZE, |
---|
| 531 | IntTab(cluster(x,y),NIC_TGTID), false)); |
---|
| 532 | maptabd.add(Segment("seg_cdma", SEG_CMA_BASE, SEG_CMA_SIZE, |
---|
| 533 | IntTab(cluster(x,y),CMA_TGTID), false)); |
---|
| 534 | maptabd.add(Segment("seg_simh", SEG_SIM_BASE, SEG_SIM_SIZE, |
---|
| 535 | IntTab(cluster(x,y),SIM_TGTID), false)); |
---|
[344] | 536 | } |
---|
| 537 | } |
---|
| 538 | } |
---|
| 539 | std::cout << maptabd << std::endl; |
---|
| 540 | |
---|
| 541 | // external network |
---|
[438] | 542 | MappingTable maptabx(vci_address_width, |
---|
[1012] | 543 | IntTab(x_width + y_width), |
---|
| 544 | IntTab(x_width + y_width), |
---|
[396] | 545 | 0xFFFF000000ULL); |
---|
[344] | 546 | |
---|
[663] | 547 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[344] | 548 | { |
---|
[663] | 549 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[752] | 550 | { |
---|
[396] | 551 | |
---|
[438] | 552 | sc_uint<vci_address_width> offset; |
---|
[1012] | 553 | offset = (sc_uint<vci_address_width>) cluster(x,y) |
---|
[836] | 554 | << (vci_address_width - x_width - y_width); |
---|
[396] | 555 | |
---|
[344] | 556 | std::ostringstream sh; |
---|
| 557 | sh << "x_seg_memc_" << x << "_" << y; |
---|
[396] | 558 | |
---|
[1012] | 559 | maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset, |
---|
| 560 | SEG_RAM_SIZE, IntTab(cluster(x,y)), false)); |
---|
[344] | 561 | } |
---|
| 562 | } |
---|
| 563 | std::cout << maptabx << std::endl; |
---|
| 564 | |
---|
| 565 | //////////////////// |
---|
| 566 | // Signals |
---|
| 567 | /////////////////// |
---|
| 568 | |
---|
[389] | 569 | sc_clock signal_clk("clk"); |
---|
[344] | 570 | sc_signal<bool> signal_resetn("resetn"); |
---|
| 571 | |
---|
| 572 | // Horizontal inter-clusters DSPIN signals |
---|
[885] | 573 | DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc = |
---|
[1012] | 574 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE - 1, Y_SIZE); |
---|
[885] | 575 | DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec = |
---|
[1012] | 576 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE - 1, Y_SIZE); |
---|
[344] | 577 | |
---|
[885] | 578 | DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc = |
---|
[1012] | 579 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE - 1, Y_SIZE); |
---|
[885] | 580 | DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec = |
---|
[1012] | 581 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE - 1, Y_SIZE); |
---|
[885] | 582 | |
---|
| 583 | DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc = |
---|
[1012] | 584 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE- 1 , Y_SIZE); |
---|
[885] | 585 | DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec = |
---|
[1012] | 586 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE - 1, Y_SIZE); |
---|
[885] | 587 | |
---|
| 588 | DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc = |
---|
[1012] | 589 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE - 1, Y_SIZE); |
---|
[885] | 590 | DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec = |
---|
[1012] | 591 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE - 1, Y_SIZE); |
---|
[885] | 592 | |
---|
| 593 | DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc = |
---|
[1012] | 594 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE - 1, Y_SIZE); |
---|
[885] | 595 | DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec = |
---|
[1012] | 596 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE - 1, Y_SIZE); |
---|
[885] | 597 | |
---|
[344] | 598 | // Vertical inter-clusters DSPIN signals |
---|
[885] | 599 | DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc = |
---|
[1012] | 600 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE - 1); |
---|
[885] | 601 | DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec = |
---|
[1012] | 602 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE - 1); |
---|
[344] | 603 | |
---|
[885] | 604 | DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc = |
---|
[1012] | 605 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE - 1); |
---|
[885] | 606 | DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec = |
---|
[1012] | 607 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE - 1); |
---|
[344] | 608 | |
---|
[885] | 609 | DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc = |
---|
[1012] | 610 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE - 1); |
---|
[885] | 611 | DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec = |
---|
[1012] | 612 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE - 1); |
---|
[885] | 613 | |
---|
| 614 | DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc = |
---|
[1012] | 615 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE - 1); |
---|
[885] | 616 | DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec = |
---|
[1012] | 617 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE - 1); |
---|
[885] | 618 | |
---|
| 619 | DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc = |
---|
[1012] | 620 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE - 1); |
---|
[885] | 621 | DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec = |
---|
[1012] | 622 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE - 1); |
---|
[885] | 623 | |
---|
| 624 | // Mesh boundaries DSPIN signals (Most of those signals are not used...) |
---|
| 625 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in = |
---|
| 626 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4); |
---|
| 627 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out = |
---|
| 628 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4); |
---|
| 629 | |
---|
| 630 | DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in = |
---|
| 631 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4); |
---|
| 632 | DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out = |
---|
| 633 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4); |
---|
| 634 | |
---|
| 635 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in = |
---|
| 636 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4); |
---|
| 637 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out = |
---|
| 638 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4); |
---|
| 639 | |
---|
| 640 | DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in = |
---|
| 641 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4); |
---|
| 642 | DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out = |
---|
| 643 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4); |
---|
| 644 | |
---|
| 645 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in = |
---|
| 646 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4); |
---|
| 647 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out = |
---|
| 648 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4); |
---|
| 649 | |
---|
| 650 | |
---|
[344] | 651 | //////////////////////////// |
---|
| 652 | // Loader |
---|
| 653 | //////////////////////////// |
---|
| 654 | |
---|
| 655 | soclib::common::Loader loader(soft_name); |
---|
| 656 | |
---|
| 657 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 658 | proc_iss::set_loader(loader); |
---|
| 659 | |
---|
| 660 | //////////////////////////// |
---|
| 661 | // Clusters construction |
---|
| 662 | //////////////////////////// |
---|
| 663 | |
---|
[396] | 664 | TsarXbarCluster<dspin_cmd_width, |
---|
| 665 | dspin_rsp_width, |
---|
| 666 | vci_param_int, |
---|
[836] | 667 | vci_param_ext> * clusters[X_SIZE][Y_SIZE]; |
---|
[344] | 668 | |
---|
| 669 | #if USE_OPENMP |
---|
| 670 | #pragma omp parallel |
---|
| 671 | { |
---|
| 672 | #pragma omp for |
---|
| 673 | #endif |
---|
[663] | 674 | for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
[344] | 675 | { |
---|
[663] | 676 | size_t x = i / Y_SIZE; |
---|
| 677 | size_t y = i % Y_SIZE; |
---|
[344] | 678 | |
---|
| 679 | #if USE_OPENMP |
---|
| 680 | #pragma omp critical |
---|
| 681 | { |
---|
| 682 | #endif |
---|
[438] | 683 | std::cout << std::endl; |
---|
| 684 | std::cout << "Cluster_" << x << "_" << y << std::endl; |
---|
| 685 | std::cout << std::endl; |
---|
[389] | 686 | |
---|
[344] | 687 | std::ostringstream sc; |
---|
| 688 | sc << "cluster_" << x << "_" << y; |
---|
[396] | 689 | clusters[x][y] = new TsarXbarCluster<dspin_cmd_width, |
---|
| 690 | dspin_rsp_width, |
---|
| 691 | vci_param_int, |
---|
| 692 | vci_param_ext> |
---|
[344] | 693 | ( |
---|
| 694 | sc.str().c_str(), |
---|
[396] | 695 | NB_PROCS_MAX, |
---|
[752] | 696 | NB_TTY_CHANNELS, |
---|
| 697 | NB_DMA_CHANNELS, |
---|
[396] | 698 | x, |
---|
| 699 | y, |
---|
| 700 | cluster(x,y), |
---|
| 701 | maptabd, |
---|
| 702 | maptabx, |
---|
| 703 | x_width, |
---|
| 704 | y_width, |
---|
[438] | 705 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
[1012] | 706 | RAM_TGTID, |
---|
| 707 | XCU_TGTID, |
---|
| 708 | DMA_TGTID, |
---|
| 709 | FBF_TGTID, |
---|
| 710 | TTY_TGTID, |
---|
| 711 | ROM_TGTID, |
---|
| 712 | NIC_TGTID, |
---|
| 713 | CMA_TGTID, |
---|
| 714 | IOC_TGTID, |
---|
| 715 | SIM_TGTID, |
---|
[396] | 716 | MEMC_WAYS, |
---|
| 717 | MEMC_SETS, |
---|
| 718 | L1_IWAYS, |
---|
| 719 | L1_ISETS, |
---|
| 720 | L1_DWAYS, |
---|
| 721 | L1_DSETS, |
---|
[706] | 722 | IRQ_PER_PROCESSOR, |
---|
[396] | 723 | XRAM_LATENCY, |
---|
| 724 | (cluster(x,y) == cluster_io_id), |
---|
[1012] | 725 | FBF_X_SIZE, |
---|
| 726 | FBF_Y_SIZE, |
---|
[396] | 727 | disk_name, |
---|
| 728 | BDEV_SECTOR_SIZE, |
---|
| 729 | NB_NIC_CHANNELS, |
---|
| 730 | nic_rx_name, |
---|
| 731 | nic_tx_name, |
---|
| 732 | NIC_TIMEOUT, |
---|
[485] | 733 | NB_CMA_CHANNELS, |
---|
[396] | 734 | loader, |
---|
[344] | 735 | frozen_cycles, |
---|
[663] | 736 | debug_from, |
---|
[836] | 737 | debug_ok, |
---|
| 738 | debug_ok |
---|
[344] | 739 | ); |
---|
| 740 | |
---|
| 741 | #if USE_OPENMP |
---|
| 742 | } // end critical |
---|
| 743 | #endif |
---|
| 744 | } // end for |
---|
| 745 | #if USE_OPENMP |
---|
| 746 | } |
---|
| 747 | #endif |
---|
| 748 | |
---|
| 749 | /////////////////////////////////////////////////////////////// |
---|
| 750 | // Net-list |
---|
| 751 | /////////////////////////////////////////////////////////////// |
---|
| 752 | |
---|
| 753 | // Clock & RESET |
---|
[663] | 754 | for (size_t x = 0; x < (X_SIZE); x++){ |
---|
| 755 | for (size_t y = 0; y < Y_SIZE; y++){ |
---|
[389] | 756 | clusters[x][y]->p_clk (signal_clk); |
---|
| 757 | clusters[x][y]->p_resetn (signal_resetn); |
---|
[344] | 758 | } |
---|
| 759 | } |
---|
| 760 | |
---|
| 761 | // Inter Clusters horizontal connections |
---|
[885] | 762 | if (X_SIZE > 1) { |
---|
| 763 | for (size_t x = 0; x < (X_SIZE-1); x++) { |
---|
| 764 | for (size_t y = 0; y < (Y_SIZE); y++) { |
---|
| 765 | clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]); |
---|
| 766 | clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]); |
---|
| 767 | clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]); |
---|
| 768 | clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]); |
---|
[468] | 769 | |
---|
[885] | 770 | clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]); |
---|
| 771 | clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]); |
---|
| 772 | clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]); |
---|
| 773 | clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]); |
---|
| 774 | |
---|
| 775 | clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]); |
---|
| 776 | clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]); |
---|
| 777 | clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]); |
---|
| 778 | clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]); |
---|
| 779 | |
---|
| 780 | clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]); |
---|
| 781 | clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]); |
---|
| 782 | clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]); |
---|
| 783 | clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]); |
---|
| 784 | |
---|
| 785 | clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]); |
---|
| 786 | clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]); |
---|
| 787 | clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]); |
---|
| 788 | clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]); |
---|
| 789 | } |
---|
| 790 | } |
---|
[344] | 791 | } |
---|
[885] | 792 | std::cout << std::endl << "Horizontal connections done" << std::endl; |
---|
[344] | 793 | |
---|
| 794 | // Inter Clusters vertical connections |
---|
[663] | 795 | if (Y_SIZE > 1) { |
---|
[885] | 796 | for (size_t y = 0; y < (Y_SIZE-1); y++) { |
---|
| 797 | for (size_t x = 0; x < X_SIZE; x++) { |
---|
| 798 | clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]); |
---|
| 799 | clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]); |
---|
| 800 | clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]); |
---|
| 801 | clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]); |
---|
[468] | 802 | |
---|
[885] | 803 | clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]); |
---|
| 804 | clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]); |
---|
| 805 | clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]); |
---|
| 806 | clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]); |
---|
| 807 | |
---|
| 808 | clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]); |
---|
| 809 | clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]); |
---|
| 810 | clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]); |
---|
| 811 | clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]); |
---|
| 812 | |
---|
| 813 | clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]); |
---|
| 814 | clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]); |
---|
| 815 | clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]); |
---|
| 816 | clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]); |
---|
| 817 | |
---|
| 818 | clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]); |
---|
| 819 | clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]); |
---|
| 820 | clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]); |
---|
| 821 | clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]); |
---|
| 822 | } |
---|
| 823 | } |
---|
[344] | 824 | } |
---|
[885] | 825 | std::cout << std::endl << "Vertical connections done" << std::endl; |
---|
[344] | 826 | |
---|
| 827 | // East & West boundary cluster connections |
---|
[885] | 828 | for (size_t y = 0; y < (Y_SIZE); y++) { |
---|
| 829 | clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]); |
---|
| 830 | clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]); |
---|
| 831 | clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]); |
---|
| 832 | clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]); |
---|
[468] | 833 | |
---|
[885] | 834 | clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]); |
---|
| 835 | clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]); |
---|
| 836 | clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]); |
---|
| 837 | clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]); |
---|
| 838 | |
---|
| 839 | clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]); |
---|
| 840 | clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]); |
---|
| 841 | clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]); |
---|
| 842 | clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]); |
---|
| 843 | |
---|
| 844 | clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]); |
---|
| 845 | clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]); |
---|
| 846 | clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]); |
---|
| 847 | clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]); |
---|
| 848 | |
---|
| 849 | clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]); |
---|
| 850 | clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]); |
---|
| 851 | clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]); |
---|
| 852 | clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]); |
---|
[344] | 853 | } |
---|
| 854 | |
---|
[885] | 855 | std::cout << std::endl << "West & East boundaries connections done" << std::endl; |
---|
| 856 | |
---|
[344] | 857 | // North & South boundary clusters connections |
---|
[885] | 858 | for (size_t x = 0; x < X_SIZE; x++) { |
---|
| 859 | clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]); |
---|
| 860 | clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]); |
---|
| 861 | clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]); |
---|
| 862 | clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]); |
---|
[468] | 863 | |
---|
[885] | 864 | clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]); |
---|
| 865 | clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]); |
---|
| 866 | clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]); |
---|
| 867 | clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]); |
---|
| 868 | |
---|
| 869 | clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]); |
---|
| 870 | clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]); |
---|
| 871 | clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]); |
---|
| 872 | clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]); |
---|
| 873 | |
---|
| 874 | clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]); |
---|
| 875 | clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]); |
---|
| 876 | clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]); |
---|
| 877 | clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]); |
---|
| 878 | |
---|
| 879 | clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]); |
---|
| 880 | clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]); |
---|
| 881 | clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]); |
---|
| 882 | clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]); |
---|
[344] | 883 | } |
---|
[885] | 884 | |
---|
| 885 | std::cout << std::endl << "North & South boundaries connections done" << std::endl; |
---|
[396] | 886 | std::cout << std::endl; |
---|
[344] | 887 | |
---|
| 888 | |
---|
[836] | 889 | #ifdef WT_IDL |
---|
| 890 | std::list<VciCcVCacheWrapper<vci_param_int, |
---|
| 891 | dspin_cmd_width, |
---|
| 892 | dspin_rsp_width, |
---|
| 893 | GdbServer<Mips32ElIss> > * > l1_caches; |
---|
| 894 | |
---|
| 895 | for (size_t x = 0; x < X_SIZE; x++) { |
---|
| 896 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
| 897 | for (int proc = 0; proc < NB_PROCS_MAX; proc++) { |
---|
| 898 | l1_caches.push_back(clusters[x][y]->proc[proc]); |
---|
| 899 | } |
---|
| 900 | } |
---|
| 901 | } |
---|
| 902 | |
---|
| 903 | for (size_t x = 0; x < X_SIZE; x++) { |
---|
| 904 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
| 905 | clusters[x][y]->memc->set_vcache_list(l1_caches); |
---|
| 906 | } |
---|
| 907 | } |
---|
| 908 | #endif |
---|
| 909 | |
---|
| 910 | |
---|
[779] | 911 | //#define SC_TRACE |
---|
[752] | 912 | #ifdef SC_TRACE |
---|
| 913 | sc_trace_file * tf = sc_create_vcd_trace_file("my_trace_file"); |
---|
| 914 | |
---|
| 915 | if (X_SIZE > 1){ |
---|
| 916 | for (size_t x = 0; x < (X_SIZE-1); x++){ |
---|
| 917 | for (size_t y = 0; y < Y_SIZE; y++){ |
---|
| 918 | for (size_t k = 0; k < 3; k++){ |
---|
| 919 | signal_dspin_h_cmd_inc[x][y][k].trace(tf, "dspin_h_cmd_inc"); |
---|
| 920 | signal_dspin_h_cmd_dec[x][y][k].trace(tf, "dspin_h_cmd_dec"); |
---|
| 921 | } |
---|
| 922 | |
---|
| 923 | for (size_t k = 0; k < 2; k++){ |
---|
| 924 | signal_dspin_h_rsp_inc[x][y][k].trace(tf, "dspin_h_rsp_inc"); |
---|
| 925 | signal_dspin_h_rsp_dec[x][y][k].trace(tf, "dspin_h_rsp_dec"); |
---|
| 926 | } |
---|
| 927 | } |
---|
| 928 | } |
---|
| 929 | } |
---|
| 930 | |
---|
| 931 | if (Y_SIZE > 1) { |
---|
| 932 | for (size_t y = 0; y < (Y_SIZE-1); y++){ |
---|
| 933 | for (size_t x = 0; x < X_SIZE; x++){ |
---|
| 934 | for (size_t k = 0; k < 3; k++){ |
---|
| 935 | signal_dspin_v_cmd_inc[x][y][k].trace(tf, "dspin_v_cmd_inc"); |
---|
| 936 | signal_dspin_v_cmd_dec[x][y][k].trace(tf, "dspin_v_cmd_dec"); |
---|
| 937 | } |
---|
| 938 | |
---|
| 939 | for (size_t k = 0; k < 2; k++){ |
---|
| 940 | signal_dspin_v_rsp_inc[x][y][k].trace(tf, "dspin_v_rsp_inc"); |
---|
| 941 | signal_dspin_v_rsp_dec[x][y][k].trace(tf, "dspin_v_rsp_dec"); |
---|
| 942 | } |
---|
| 943 | } |
---|
| 944 | } |
---|
| 945 | } |
---|
| 946 | |
---|
| 947 | for (size_t x = 0; x < (X_SIZE); x++){ |
---|
| 948 | for (size_t y = 0; y < Y_SIZE; y++){ |
---|
| 949 | std::ostringstream signame; |
---|
| 950 | signame << "cluster" << x << "_" << y; |
---|
| 951 | clusters[x][y]->trace(tf, signame.str()); |
---|
| 952 | } |
---|
| 953 | } |
---|
| 954 | #endif |
---|
| 955 | |
---|
[779] | 956 | |
---|
| 957 | //////////////////////////////////////////////////////// |
---|
| 958 | // Simulation |
---|
| 959 | /////////////////////////////////////////////////////// |
---|
| 960 | |
---|
| 961 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 962 | signal_resetn = false; |
---|
| 963 | |
---|
[885] | 964 | // set network boundaries signals default values |
---|
| 965 | // for all boundary clusters |
---|
| 966 | for (size_t x = 0; x < X_SIZE ; x++) { |
---|
| 967 | for (size_t y = 0; y < Y_SIZE ; y++) { |
---|
| 968 | for (size_t face = 0; face < 4; face++) { |
---|
| 969 | signal_dspin_bound_cmd_in [x][y][face].write = false; |
---|
| 970 | signal_dspin_bound_cmd_in [x][y][face].read = true; |
---|
| 971 | signal_dspin_bound_cmd_out[x][y][face].write = false; |
---|
| 972 | signal_dspin_bound_cmd_out[x][y][face].read = true; |
---|
| 973 | |
---|
| 974 | signal_dspin_bound_rsp_in [x][y][face].write = false; |
---|
| 975 | signal_dspin_bound_rsp_in [x][y][face].read = true; |
---|
| 976 | signal_dspin_bound_rsp_out[x][y][face].write = false; |
---|
| 977 | signal_dspin_bound_rsp_out[x][y][face].read = true; |
---|
| 978 | |
---|
| 979 | signal_dspin_bound_m2p_in [x][y][face].write = false; |
---|
| 980 | signal_dspin_bound_m2p_in [x][y][face].read = true; |
---|
| 981 | signal_dspin_bound_m2p_out[x][y][face].write = false; |
---|
| 982 | signal_dspin_bound_m2p_out[x][y][face].read = true; |
---|
| 983 | |
---|
| 984 | signal_dspin_bound_p2m_in [x][y][face].write = false; |
---|
| 985 | signal_dspin_bound_p2m_in [x][y][face].read = true; |
---|
| 986 | signal_dspin_bound_p2m_out[x][y][face].write = false; |
---|
| 987 | signal_dspin_bound_p2m_out[x][y][face].read = true; |
---|
| 988 | |
---|
| 989 | signal_dspin_bound_cla_in [x][y][face].write = false; |
---|
| 990 | signal_dspin_bound_cla_in [x][y][face].read = true; |
---|
| 991 | signal_dspin_bound_cla_out[x][y][face].write = false; |
---|
| 992 | signal_dspin_bound_cla_out[x][y][face].read = true; |
---|
| 993 | } |
---|
| 994 | } |
---|
[779] | 995 | } |
---|
| 996 | |
---|
| 997 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 998 | signal_resetn = true; |
---|
| 999 | |
---|
[663] | 1000 | if (debug_ok) { |
---|
| 1001 | #if USE_OPENMP |
---|
| 1002 | assert(false && "OPEN MP should not be used with debug because of its traces"); |
---|
| 1003 | #endif |
---|
[464] | 1004 | |
---|
[663] | 1005 | if (gettimeofday(&t1, NULL) != 0) { |
---|
| 1006 | perror("gettimeofday"); |
---|
| 1007 | return EXIT_FAILURE; |
---|
| 1008 | } |
---|
[396] | 1009 | |
---|
[663] | 1010 | for (int64_t n = 1; n < ncycles && !stop_called; n++) |
---|
[464] | 1011 | { |
---|
[663] | 1012 | if ((n % max_cycles) == 0) |
---|
[464] | 1013 | { |
---|
[663] | 1014 | |
---|
[752] | 1015 | if (gettimeofday(&t2, NULL) != 0) |
---|
[663] | 1016 | { |
---|
| 1017 | perror("gettimeofday"); |
---|
| 1018 | return EXIT_FAILURE; |
---|
| 1019 | } |
---|
| 1020 | |
---|
| 1021 | ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; |
---|
| 1022 | ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; |
---|
| 1023 | std::cerr << "platform clock frequency " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; |
---|
| 1024 | |
---|
[752] | 1025 | if (gettimeofday(&t1, NULL) != 0) |
---|
[663] | 1026 | { |
---|
| 1027 | perror("gettimeofday"); |
---|
| 1028 | return EXIT_FAILURE; |
---|
| 1029 | } |
---|
[464] | 1030 | } |
---|
| 1031 | |
---|
| 1032 | |
---|
[663] | 1033 | if (n == reset_counters) { |
---|
| 1034 | for (size_t x = 0; x < (X_SIZE); x++) { |
---|
| 1035 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
| 1036 | clusters[x][y]->memc->reset_counters(); |
---|
| 1037 | } |
---|
| 1038 | } |
---|
[464] | 1039 | } |
---|
| 1040 | |
---|
[663] | 1041 | if (n == dump_counters) { |
---|
| 1042 | for (size_t x = 0; x < (X_SIZE); x++) { |
---|
| 1043 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
| 1044 | clusters[x][y]->memc->print_stats(true, false); |
---|
| 1045 | } |
---|
| 1046 | } |
---|
| 1047 | } |
---|
[344] | 1048 | |
---|
[752] | 1049 | if ((n > debug_from) and (n % debug_period == 0)) |
---|
[663] | 1050 | { |
---|
| 1051 | std::cout << "****************** cycle " << std::dec << n ; |
---|
[836] | 1052 | std::cout << "************************************************" << std::endl; |
---|
[379] | 1053 | |
---|
[836] | 1054 | for (size_t x = 0; x < X_SIZE ; x++){ |
---|
| 1055 | for (size_t y = 0; y < Y_SIZE ; y++){ |
---|
| 1056 | for (int proc = 0; proc < NB_PROCS_MAX; proc++) { |
---|
| 1057 | clusters[x][y]->proc[proc]->print_trace(); |
---|
| 1058 | std::ostringstream proc_signame; |
---|
| 1059 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc ; |
---|
| 1060 | std::ostringstream p2m_signame; |
---|
| 1061 | p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " P2M"; |
---|
| 1062 | std::ostringstream m2p_signame; |
---|
| 1063 | m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " M2P"; |
---|
[404] | 1064 | |
---|
[836] | 1065 | clusters[x][y]->signal_vci_ini_proc[proc].print_trace(proc_signame.str()); |
---|
| 1066 | clusters[x][y]->signal_dspin_p2m_proc[proc].print_trace(p2m_signame.str()); |
---|
| 1067 | clusters[x][y]->signal_dspin_m2p_proc[proc].print_trace(m2p_signame.str()); |
---|
| 1068 | } |
---|
[404] | 1069 | |
---|
[836] | 1070 | clusters[x][y]->memc->print_trace(); |
---|
[344] | 1071 | |
---|
[836] | 1072 | std::ostringstream smemc; |
---|
| 1073 | smemc << "[SIG]MEMC_" << x << "_" << y; |
---|
| 1074 | std::ostringstream sxram; |
---|
| 1075 | sxram << "[SIG]XRAM_" << x << "_" << y; |
---|
| 1076 | std::ostringstream sm2p; |
---|
| 1077 | sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P"; |
---|
| 1078 | std::ostringstream sp2m; |
---|
| 1079 | sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M"; |
---|
[344] | 1080 | |
---|
[836] | 1081 | clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); |
---|
| 1082 | clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); |
---|
| 1083 | clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); |
---|
| 1084 | clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); |
---|
| 1085 | } |
---|
| 1086 | } |
---|
[663] | 1087 | } |
---|
| 1088 | |
---|
| 1089 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
[344] | 1090 | } |
---|
[663] | 1091 | } |
---|
| 1092 | else { |
---|
| 1093 | int64_t n = 0; |
---|
[749] | 1094 | while (!stop_called && n != ncycles) { |
---|
[663] | 1095 | if (gettimeofday(&t1, NULL) != 0) { |
---|
| 1096 | perror("gettimeofday"); |
---|
| 1097 | return EXIT_FAILURE; |
---|
| 1098 | } |
---|
[749] | 1099 | int64_t nb_cycles = min(max_cycles, ncycles - n); |
---|
[663] | 1100 | if (do_reset_counters) { |
---|
| 1101 | nb_cycles = min(nb_cycles, reset_counters - n); |
---|
| 1102 | } |
---|
| 1103 | if (do_dump_counters) { |
---|
| 1104 | nb_cycles = min(nb_cycles, dump_counters - n); |
---|
| 1105 | } |
---|
[344] | 1106 | |
---|
[663] | 1107 | sc_start(sc_core::sc_time(nb_cycles, SC_NS)); |
---|
| 1108 | n += nb_cycles; |
---|
| 1109 | |
---|
| 1110 | if (do_reset_counters && n == reset_counters) { |
---|
| 1111 | // Reseting counters |
---|
| 1112 | for (size_t x = 0; x < (X_SIZE); x++) { |
---|
| 1113 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
| 1114 | clusters[x][y]->memc->reset_counters(); |
---|
| 1115 | } |
---|
| 1116 | } |
---|
| 1117 | do_reset_counters = false; |
---|
| 1118 | } |
---|
| 1119 | |
---|
| 1120 | if (do_dump_counters && n == dump_counters) { |
---|
| 1121 | // Dumping counters |
---|
| 1122 | for (size_t x = 0; x < (X_SIZE); x++) { |
---|
| 1123 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
| 1124 | clusters[x][y]->memc->print_stats(true, false); |
---|
| 1125 | } |
---|
| 1126 | } |
---|
| 1127 | do_dump_counters = false; |
---|
| 1128 | } |
---|
| 1129 | |
---|
| 1130 | |
---|
| 1131 | if (gettimeofday(&t2, NULL) != 0) { |
---|
| 1132 | perror("gettimeofday"); |
---|
| 1133 | return EXIT_FAILURE; |
---|
| 1134 | } |
---|
| 1135 | ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; |
---|
| 1136 | ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; |
---|
[706] | 1137 | std::cerr << std::dec << "cycle " << n << " platform clock frequency " << (double) nb_cycles / (double) (ms2 - ms1) << "Khz" << std::endl; |
---|
[663] | 1138 | } |
---|
[344] | 1139 | } |
---|
[504] | 1140 | |
---|
[885] | 1141 | |
---|
[512] | 1142 | // Free memory |
---|
[663] | 1143 | for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
[504] | 1144 | { |
---|
[663] | 1145 | size_t x = i / Y_SIZE; |
---|
| 1146 | size_t y = i % Y_SIZE; |
---|
[504] | 1147 | delete clusters[x][y]; |
---|
| 1148 | } |
---|
| 1149 | |
---|
[885] | 1150 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X_SIZE-1, Y_SIZE); |
---|
| 1151 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X_SIZE-1, Y_SIZE); |
---|
[512] | 1152 | |
---|
[885] | 1153 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X_SIZE-1, Y_SIZE); |
---|
| 1154 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X_SIZE-1, Y_SIZE); |
---|
| 1155 | |
---|
| 1156 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_m2p_inc, X_SIZE-1, Y_SIZE); |
---|
| 1157 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_m2p_dec, X_SIZE-1, Y_SIZE); |
---|
| 1158 | |
---|
| 1159 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_p2m_inc, X_SIZE-1, Y_SIZE); |
---|
| 1160 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_p2m_dec, X_SIZE-1, Y_SIZE); |
---|
| 1161 | |
---|
| 1162 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cla_inc, X_SIZE-1, Y_SIZE); |
---|
| 1163 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cla_dec, X_SIZE-1, Y_SIZE); |
---|
| 1164 | |
---|
| 1165 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE-1); |
---|
| 1166 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE-1); |
---|
| 1167 | |
---|
| 1168 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE-1); |
---|
| 1169 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE-1); |
---|
| 1170 | |
---|
| 1171 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_m2p_inc, X_SIZE, Y_SIZE-1); |
---|
| 1172 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_m2p_dec, X_SIZE, Y_SIZE-1); |
---|
| 1173 | |
---|
| 1174 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_p2m_inc, X_SIZE, Y_SIZE-1); |
---|
| 1175 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_p2m_dec, X_SIZE, Y_SIZE-1); |
---|
| 1176 | |
---|
| 1177 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cla_inc, X_SIZE, Y_SIZE-1); |
---|
| 1178 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cla_dec, X_SIZE, Y_SIZE-1); |
---|
| 1179 | |
---|
| 1180 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cmd_in, X_SIZE, Y_SIZE, 4); |
---|
| 1181 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cmd_out, X_SIZE, Y_SIZE, 4); |
---|
| 1182 | |
---|
| 1183 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_bound_rsp_in, X_SIZE, Y_SIZE, 4); |
---|
| 1184 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_bound_rsp_out, X_SIZE, Y_SIZE, 4); |
---|
| 1185 | |
---|
| 1186 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_m2p_in, X_SIZE, Y_SIZE, 4); |
---|
| 1187 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_m2p_out, X_SIZE, Y_SIZE, 4); |
---|
| 1188 | |
---|
| 1189 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_bound_p2m_in, X_SIZE, Y_SIZE, 4); |
---|
| 1190 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_bound_p2m_out, X_SIZE, Y_SIZE, 4); |
---|
| 1191 | |
---|
| 1192 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cla_in, X_SIZE, Y_SIZE, 4); |
---|
| 1193 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cla_out, X_SIZE, Y_SIZE, 4); |
---|
| 1194 | |
---|
[344] | 1195 | return EXIT_SUCCESS; |
---|
| 1196 | } |
---|
| 1197 | |
---|
[504] | 1198 | |
---|
| 1199 | void handler(int dummy = 0) { |
---|
| 1200 | stop_called = true; |
---|
| 1201 | sc_stop(); |
---|
| 1202 | } |
---|
| 1203 | |
---|
[547] | 1204 | void voidhandler(int dummy = 0) {} |
---|
[504] | 1205 | |
---|
[344] | 1206 | int sc_main (int argc, char *argv[]) |
---|
| 1207 | { |
---|
[504] | 1208 | signal(SIGINT, handler); |
---|
[547] | 1209 | signal(SIGPIPE, voidhandler); |
---|
[504] | 1210 | |
---|
[344] | 1211 | try { |
---|
| 1212 | return _main(argc, argv); |
---|
| 1213 | } catch (std::exception &e) { |
---|
| 1214 | std::cout << e.what() << std::endl; |
---|
| 1215 | } catch (...) { |
---|
| 1216 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1217 | throw; |
---|
| 1218 | } |
---|
| 1219 | return 1; |
---|
| 1220 | } |
---|
| 1221 | |
---|
| 1222 | |
---|
| 1223 | // Local Variables: |
---|
| 1224 | // tab-width: 3 |
---|
| 1225 | // c-basic-offset: 3 |
---|
| 1226 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1227 | // indent-tabs-mode: nil |
---|
| 1228 | // End: |
---|
| 1229 | |
---|
| 1230 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|