Ignore:
Timestamp:
Jul 24, 2013, 8:47:40 AM (11 years ago)
Author:
cfuguet
Message:


Merging vci_mem_cache from branches/v5 to trunk [441-467]

=-----------------------------------------------------------------------
r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

=-----------------------------------------------------------------------
r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

=-----------------------------------------------------------------------
r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

=-----------------------------------------------------------------------
r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

=-----------------------------------------------------------------------
r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

=-----------------------------------------------------------------------
r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

=-----------------------------------------------------------------------
r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

=-----------------------------------------------------------------------
r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

=-----------------------------------------------------------------------
r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

=-----------------------------------------------------------------------
r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

=-----------------------------------------------------------------------
r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

=-----------------------------------------------------------------------
r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

=-----------------------------------------------------------------------
r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
Location:
trunk/platforms/tsar_generic_xbar
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/platforms/tsar_generic_xbar

  • trunk/platforms/tsar_generic_xbar/top.cpp

    r465 r468  
    151151//////////////////////i/////////////////////////////////////
    152152
    153 
    154153#ifdef USE_ALMOS
    155154#include "almos/hard_config.h"
    … …  
    157156#endif
    158157#ifdef USE_GIET
     158#include "giet_vm/hard_config.h"
    159159#define PREFIX_OS "giet_vm/"
    160 #include "giet_vm/hard_config.h"
    161160#endif
    162161
    … …  
    190189#ifdef USE_GIET
    191190#define BDEV_SECTOR_SIZE      512
    192 #define BDEV_IMAGE_NAME       "giet_vm/display/images.raw"
     191#define BDEV_IMAGE_NAME       PREFIX_OS"display/images.raw"
    193192#endif
    194193#ifdef USE_ALMOS
    … …  
    196195#define BDEV_IMAGE_NAME       PREFIX_OS"hdd-img.bin"
    197196#endif
    198 
    199197
    200198#define NIC_RX_NAME           PREFIX_OS"nic/rx_packets.txt"
    … …  
    212210
    213211#ifdef USE_ALMOS
    214 #define soft_name PREFIX_OS"bootloader.bin",\
    215                   PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\
    216                   PREFIX_OS"arch-info.bib@0xBFC08000:D"
     212#define soft_name       PREFIX_OS"bootloader.bin",\
     213                        PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\
     214                        PREFIX_OS"arch-info.bib@0xBFC08000:D"
    217215#endif
    218216#ifdef USE_GIET
    219 #define soft_pathname        PREFIX_OS"soft.elf"
     217#define soft_pathname   PREFIX_OS"soft.elf"
    220218#endif
    221219
    … …  
    285283
    286284#ifdef USE_GIET
    287    char     soft_name[256]   = soft_pathname;          // pathname to binary code
    288 #endif
    289    size_t   ncycles          = 1000000000;         // simulated cycles
     285   char     soft_name[256]   = soft_pathname;      // pathname to binary code
     286#endif
     287   uint64_t ncycles          = 100000000000;       // simulated cycles
    290288   char     disk_name[256]   = BDEV_IMAGE_NAME;    // pathname to the disk image
    291289   char     nic_rx_name[256] = NIC_RX_NAME;        // pathname to the rx packets file
    … …  
    299297   uint32_t frozen_cycles    = MAX_FROZEN_CYCLES;  // monitoring frozen processor
    300298   size_t   cluster_io_id    = 0;                  // index of cluster containing IOs
    301    struct timeval t1,t2;
     299   struct   timeval t1,t2;
    302300   uint64_t ms1,ms2;
    303301
    … …  
    541539   // Horizontal inter-clusters DSPIN signals
    542540   DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc =
    543       alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 2);
     541      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 3);
    544542   DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec =
    545       alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 2);
     543      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 3);
    546544   DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc =
    547545      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2);
    … …  
    551549   // Vertical inter-clusters DSPIN signals
    552550   DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc =
    553       alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 2);
     551      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 3);
    554552   DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec =
    555       alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 2);
     553      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 3);
    556554   DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc =
    557555      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2);
    … …  
    561559   // Mesh boundaries DSPIN signals
    562560   DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in =
    563       alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in", XMAX, YMAX, 2, 4);
     561      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , XMAX, YMAX, 4, 3);
    564562   DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out =
    565       alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 2, 4);
     563      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 4, 3);
    566564   DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in =
    567       alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in", XMAX, YMAX, 2, 4);
     565      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , XMAX, YMAX, 4, 2);
    568566   DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out =
    569       alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 2, 4);
     567      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 4, 2);
    570568
    571569
    … …  
    680678      for (size_t x = 0; x < (XMAX-1); x++){
    681679         for (size_t y = 0; y < YMAX; y++){
    682             for (size_t k = 0; k < 2; k++){
     680            for (size_t k = 0; k < 3; k++){
    683681               clusters[x][y]->p_cmd_out[EAST][k]      (signal_dspin_h_cmd_inc[x][y][k]);
    684682               clusters[x+1][y]->p_cmd_in[WEST][k]     (signal_dspin_h_cmd_inc[x][y][k]);
    685683               clusters[x][y]->p_cmd_in[EAST][k]       (signal_dspin_h_cmd_dec[x][y][k]);
    686684               clusters[x+1][y]->p_cmd_out[WEST][k]    (signal_dspin_h_cmd_dec[x][y][k]);
     685            }
     686
     687            for (size_t k = 0; k < 2; k++){
    687688               clusters[x][y]->p_rsp_out[EAST][k]      (signal_dspin_h_rsp_inc[x][y][k]);
    688689               clusters[x+1][y]->p_rsp_in[WEST][k]     (signal_dspin_h_rsp_inc[x][y][k]);
    … …  
    699700      for (size_t y = 0; y < (YMAX-1); y++){
    700701         for (size_t x = 0; x < XMAX; x++){
    701             for (size_t k = 0; k < 2; k++){
     702            for (size_t k = 0; k < 3; k++){
    702703               clusters[x][y]->p_cmd_out[NORTH][k]     (signal_dspin_v_cmd_inc[x][y][k]);
    703704               clusters[x][y+1]->p_cmd_in[SOUTH][k]    (signal_dspin_v_cmd_inc[x][y][k]);
    704705               clusters[x][y]->p_cmd_in[NORTH][k]      (signal_dspin_v_cmd_dec[x][y][k]);
    705706               clusters[x][y+1]->p_cmd_out[SOUTH][k]   (signal_dspin_v_cmd_dec[x][y][k]);
     707            }
     708
     709            for (size_t k = 0; k < 2; k++){
    706710               clusters[x][y]->p_rsp_out[NORTH][k]     (signal_dspin_v_rsp_inc[x][y][k]);
    707711               clusters[x][y+1]->p_rsp_in[SOUTH][k]    (signal_dspin_v_rsp_inc[x][y][k]);
    … …  
    717721   for (size_t y = 0; y < YMAX; y++)
    718722   {
     723      for (size_t k = 0; k < 3; k++)
     724      {
     725         clusters[0][y]->p_cmd_in[WEST][k]        (signal_dspin_false_cmd_in[0][y][WEST][k]);
     726         clusters[0][y]->p_cmd_out[WEST][k]       (signal_dspin_false_cmd_out[0][y][WEST][k]);
     727         clusters[XMAX-1][y]->p_cmd_in[EAST][k]   (signal_dspin_false_cmd_in[XMAX-1][y][EAST][k]);
     728         clusters[XMAX-1][y]->p_cmd_out[EAST][k]  (signal_dspin_false_cmd_out[XMAX-1][y][EAST][k]);
     729      }
     730
    719731      for (size_t k = 0; k < 2; k++)
    720732      {
    721          clusters[0][y]->p_cmd_in[WEST][k]             (signal_dspin_false_cmd_in[0][y][k][WEST]);
    722          clusters[0][y]->p_cmd_out[WEST][k]            (signal_dspin_false_cmd_out[0][y][k][WEST]);
    723          clusters[0][y]->p_rsp_in[WEST][k]             (signal_dspin_false_rsp_in[0][y][k][WEST]);
    724          clusters[0][y]->p_rsp_out[WEST][k]            (signal_dspin_false_rsp_out[0][y][k][WEST]);
    725 
    726          clusters[XMAX-1][y]->p_cmd_in[EAST][k]   (signal_dspin_false_cmd_in[XMAX-1][y][k][EAST]);
    727          clusters[XMAX-1][y]->p_cmd_out[EAST][k]  (signal_dspin_false_cmd_out[XMAX-1][y][k][EAST]);
    728          clusters[XMAX-1][y]->p_rsp_in[EAST][k]   (signal_dspin_false_rsp_in[XMAX-1][y][k][EAST]);
    729          clusters[XMAX-1][y]->p_rsp_out[EAST][k]  (signal_dspin_false_rsp_out[XMAX-1][y][k][EAST]);
     733         clusters[0][y]->p_rsp_in[WEST][k]        (signal_dspin_false_rsp_in[0][y][WEST][k]);
     734         clusters[0][y]->p_rsp_out[WEST][k]       (signal_dspin_false_rsp_out[0][y][WEST][k]);
     735         clusters[XMAX-1][y]->p_rsp_in[EAST][k]   (signal_dspin_false_rsp_in[XMAX-1][y][EAST][k]);
     736         clusters[XMAX-1][y]->p_rsp_out[EAST][k]  (signal_dspin_false_rsp_out[XMAX-1][y][EAST][k]);
    730737      }
    731738   }
    … …  
    734741   for (size_t x = 0; x < XMAX; x++)
    735742   {
     743      for (size_t k = 0; k < 3; k++)
     744      {
     745         clusters[x][0]->p_cmd_in[SOUTH][k]       (signal_dspin_false_cmd_in[x][0][SOUTH][k]);
     746         clusters[x][0]->p_cmd_out[SOUTH][k]      (signal_dspin_false_cmd_out[x][0][SOUTH][k]);
     747         clusters[x][YMAX-1]->p_cmd_in[NORTH][k]  (signal_dspin_false_cmd_in[x][YMAX-1][NORTH][k]);
     748         clusters[x][YMAX-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][YMAX-1][NORTH][k]);
     749      }
     750
    736751      for (size_t k = 0; k < 2; k++)
    737752      {
    738          clusters[x][0]->p_cmd_in[SOUTH][k]            (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
    739          clusters[x][0]->p_cmd_out[SOUTH][k]           (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
    740          clusters[x][0]->p_rsp_in[SOUTH][k]            (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
    741          clusters[x][0]->p_rsp_out[SOUTH][k]           (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
    742 
    743          clusters[x][YMAX-1]->p_cmd_in[NORTH][k]  (signal_dspin_false_cmd_in[x][YMAX-1][k][NORTH]);
    744          clusters[x][YMAX-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][YMAX-1][k][NORTH]);
    745          clusters[x][YMAX-1]->p_rsp_in[NORTH][k]  (signal_dspin_false_rsp_in[x][YMAX-1][k][NORTH]);
    746          clusters[x][YMAX-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][YMAX-1][k][NORTH]);
     753         clusters[x][0]->p_rsp_in[SOUTH][k]       (signal_dspin_false_rsp_in[x][0][SOUTH][k]);
     754         clusters[x][0]->p_rsp_out[SOUTH][k]      (signal_dspin_false_rsp_out[x][0][SOUTH][k]);
     755         clusters[x][YMAX-1]->p_rsp_in[NORTH][k]  (signal_dspin_false_rsp_in[x][YMAX-1][NORTH][k]);
     756         clusters[x][YMAX-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][YMAX-1][NORTH][k]);
    747757      }
    748758   }
    … …  
    761771   for (size_t x = 0; x < XMAX ; x++){
    762772      for (size_t y = 0; y < YMAX ; y++){
    763          for (size_t k = 0; k < 2; k++){
    764             for (size_t a = 0; a < 4; a++){
    765                signal_dspin_false_cmd_in [x][y][k][a].write = false;
    766                signal_dspin_false_cmd_in [x][y][k][a].read  = true;
    767                signal_dspin_false_cmd_out[x][y][k][a].write = false;
    768                signal_dspin_false_cmd_out[x][y][k][a].read  = true;
    769 
    770                signal_dspin_false_rsp_in [x][y][k][a].write = false;
    771                signal_dspin_false_rsp_in [x][y][k][a].read  = true;
    772                signal_dspin_false_rsp_out[x][y][k][a].write = false;
    773                signal_dspin_false_rsp_out[x][y][k][a].read  = true;
     773         for (size_t a = 0; a < 4; a++){
     774            for (size_t k = 0; k < 3; k++){
     775               signal_dspin_false_cmd_in [x][y][a][k].write = false;
     776               signal_dspin_false_cmd_in [x][y][a][k].read  = true;
     777               signal_dspin_false_cmd_out[x][y][a][k].write = false;
     778               signal_dspin_false_cmd_out[x][y][a][k].read  = true;
     779            }
     780
     781            for (size_t k = 0; k < 2; k++){
     782               signal_dspin_false_rsp_in [x][y][a][k].write = false;
     783               signal_dspin_false_rsp_in [x][y][a][k].read  = true;
     784               signal_dspin_false_rsp_out[x][y][a][k].write = false;
     785               signal_dspin_false_rsp_out[x][y][a][k].read  = true;
    774786            }
    775787         }
    … …  
    786798   }
    787799
    788    for (size_t n = 1; n < ncycles; n++)
     800   for (uint64_t n = 1; n < ncycles; n++)
    789801   {
    790802      // Monitor a specific address for L1 & L2 caches
    … …  
    811823         }
    812824      }
    813 
    814825
    815826      if (debug_ok and (n > debug_from) and (n % debug_period == 0))
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