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source: trunk/platforms/tsar_generic_xbar/top.cpp @ 484

Last change on this file since 484 was 475, checked in by lambert, 11 years ago

Introducing Vci_Chbuf_Dma in tsar_generic_xbar platform :

The number of channels of the is dma is 2* nic_channels
Adding one argument to the tsar_xbar_cluster for dma TGTID
Chbuf Dma default address is 0x00B6000000

Changing Vci_Multi_Nic default Mac address to BABEBEEF0000

File size: 35.7 KB

Rev	Line
[344]	1	/////////////////////////////////////////////////////////////////////////
	2	// File: top.cpp
	3	// Author: Alain Greiner
	4	// Copyright: UPMC/LIP6
[396]	5	// Date : may 2013
[344]	6	// This program is released under the GNU public license
	7	/////////////////////////////////////////////////////////////////////////
[396]	8	// This file define a generic TSAR architecture.
	9	// The physical address space is 40 bits.
	10	//
[344]	11	// The number of clusters cannot be larger than 256.
	12	// The number of processors per cluster cannot be larger than 8.
	13	//
	14	// - It uses four dspin_local_crossbar per cluster as local interconnect
	15	// - It uses two virtual_dspin routers per cluster as global interconnect
	16	// - It uses the vci_cc_vcache_wrapper
	17	// - It uses the vci_mem_cache
[396]	18	// - It contains one vci_xicu per cluster.
	19	// - It contains one vci_multi_dma per cluster.
	20	// - It contains one vci_simple_ram per cluster to model the L3 cache.
[344]	21	//
[396]	22	// The communication between the MemCache and the Xram is 64 bits.
	23	//
	24	// All clusters are identical, but the cluster 0 (called io_cluster),
	25	// contains 5 extra components:
[344]	26	// - the boot rom (BROM)
	27	// - the disk controller (BDEV)
	28	// - the multi-channel network controller (MNIC)
[475]	29	// - the multi-channel chained buffer dma controller (CHBUF)
[344]	30	// - the multi-channel tty controller (MTTY)
	31	// - the frame buffer controller (FBUF)
	32	//
[396]	33	// It is build with one single component implementing a cluster,
	34	// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd)
[344]	35	//
	36	// The IRQs are connected to XICUs as follow:
	37	// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
	38	// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
	39	// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
	40	// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
	41	//
[396]	42	// Some hardware parameters are used when compiling the OS, and are used
	43	// by this top.cpp file. They must be defined in the hard_config.h file :
[344]	44	// - CLUSTER_X : number of clusters in a row (power of 2)
	45	// - CLUSTER_Y : number of clusters in a column (power of 2)
	46	// - CLUSTER_SIZE : size of the segment allocated to a cluster
	47	// - NB_PROCS_MAX : number of processors per cluster (power of 2)
[438]	48	// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9)
	49	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16)
	50	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9)
[344]	51	//
[396]	52	// Some other hardware parameters are not used when compiling the OS,
	53	// and can be directly defined in this top.cpp file:
[344]	54	// - XRAM_LATENCY : external ram latency
	55	// - MEMC_WAYS : L2 cache number of ways
	56	// - MEMC_SETS : L2 cache number of sets
	57	// - L1_IWAYS
	58	// - L1_ISETS
	59	// - L1_DWAYS
	60	// - L1_DSETS
	61	// - FBUF_X_SIZE : width of frame buffer (pixels)
	62	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
	63	// - BDEV_SECTOR_SIZE : block size for block drvice
	64	// - BDEV_IMAGE_NAME : file pathname for block device
	65	// - NIC_RX_NAME : file pathname for NIC received packets
	66	// - NIC_TX_NAME : file pathname for NIC transmited packets
	67	// - NIC_TIMEOUT : max number of cycles before closing a container
[396]	68	/////////////////////////////////////////////////////////////////////////
	69	// General policy for 40 bits physical address decoding:
	70	// All physical segments base addresses are multiple of 1 Mbytes
	71	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
[344]	72	// The (x_width + y_width) MSB bits (left aligned) define
[396]	73	// the cluster index, and the LADR bits define the local index:
[344]	74	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
[396]	75	// \|x_width\|y_width\|---\| 8 \| 24 \|
[344]	76	/////////////////////////////////////////////////////////////////////////
[396]	77	// General policy for 14 bits SRCID decoding:
	78	// Each component is identified by (x_id, y_id, l_id) tuple.
	79	// \| X_ID \| Y_ID \|---\| L_ID \|
	80	// \|x_width\|y_width\|---\| 6 \|
	81	/////////////////////////////////////////////////////////////////////////
[344]	82
	83	#include <systemc>
	84	#include <sys/time.h>
	85	#include <iostream>
	86	#include <sstream>
	87	#include <cstdlib>
	88	#include <cstdarg>
	89	#include <stdint.h>
	90
	91	#include "gdbserver.h"
	92	#include "mapping_table.h"
[378]	93	#include "tsar_xbar_cluster.h"
[344]	94	#include "alloc_elems.h"
	95
	96	///////////////////////////////////////////////////
	97	// OS
	98	///////////////////////////////////////////////////
	99
[464]	100	//#define USE_ALMOS
	101	#define USE_GIET
[344]	102
[464]	103	#ifdef USE_ALMOS
	104	#ifdef USE_GIET
	105	#error "Can't use Two different OS"
	106	#endif
	107	#endif
	108
	109	#ifndef USE_ALMOS
	110	#ifndef USE_GIET
	111	#error "You need to specify one OS"
	112	#endif
	113	#endif
	114
[344]	115	///////////////////////////////////////////////////
	116	// Parallelisation
	117	///////////////////////////////////////////////////
	118	#define USE_OPENMP 0
	119
	120	#if USE_OPENMP
	121	#include <omp.h>
	122	#endif
	123
	124	// cluster index (computed from x,y coordinates)
[438]	125	#define cluster(x,y) (y + YMAX*x)
[344]	126
	127	///////////////////////////////////////////////////////////
	128	// DSPIN parameters
	129	///////////////////////////////////////////////////////////
	130
[404]	131	#define dspin_cmd_width 39
	132	#define dspin_rsp_width 32
[344]	133
[396]	134	///////////////////////////////////////////////////////////
	135	// VCI parameters
	136	///////////////////////////////////////////////////////////
	137
[438]	138	#define vci_cell_width_int 4
	139	#define vci_cell_width_ext 8
[396]	140
[438]	141	#define vci_plen_width 8
	142	#define vci_address_width 40
	143	#define vci_rerror_width 1
	144	#define vci_clen_width 1
	145	#define vci_rflag_width 1
	146	#define vci_srcid_width 14
	147	#define vci_pktid_width 4
	148	#define vci_trdid_width 4
	149	#define vci_wrplen_width 1
[344]	150	////////////////////////////////////////////////////////////
	151	// Main Hardware Parameters values
	152	//////////////////////i/////////////////////////////////////
	153
[464]	154	#ifdef USE_ALMOS
	155	#include "almos/hard_config.h"
	156	#define PREFIX_OS "almos/"
	157	#endif
	158	#ifdef USE_GIET
[468]	159	#include "giet_vm/hard_config.h"
[464]	160	#define PREFIX_OS "giet_vm/"
	161	#endif
[344]	162
	163	////////////////////////////////////////////////////////////
[396]	164	// Secondary Hardware Parameters
[344]	165	//////////////////////i/////////////////////////////////////
	166
[438]	167	#define XMAX CLUSTER_X
	168	#define YMAX CLUSTER_Y
	169
[344]	170	#define XRAM_LATENCY 0
	171
	172	#define MEMC_WAYS 16
	173	#define MEMC_SETS 256
	174
	175	#define L1_IWAYS 4
	176	#define L1_ISETS 64
	177
	178	#define L1_DWAYS 4
	179	#define L1_DSETS 64
	180
[464]	181	#ifdef USE_ALMOS
	182	#define FBUF_X_SIZE 512
	183	#define FBUF_Y_SIZE 512
	184	#endif
	185	#ifdef USE_GIET
[344]	186	#define FBUF_X_SIZE 128
	187	#define FBUF_Y_SIZE 128
[464]	188	#endif
[344]	189
[464]	190	#ifdef USE_GIET
[344]	191	#define BDEV_SECTOR_SIZE 512
[468]	192	#define BDEV_IMAGE_NAME PREFIX_OS"display/images.raw"
[464]	193	#endif
	194	#ifdef USE_ALMOS
	195	#define BDEV_SECTOR_SIZE 4096
	196	#define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin"
	197	#endif
[344]	198
[464]	199	#define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt"
	200	#define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt"
[344]	201	#define NIC_TIMEOUT 10000
	202
[438]	203	#define NORTH 0
	204	#define SOUTH 1
	205	#define EAST 2
	206	#define WEST 3
	207
[344]	208	////////////////////////////////////////////////////////////
	209	// Software to be loaded in ROM & RAM
	210	//////////////////////i/////////////////////////////////////
	211
[464]	212	#ifdef USE_ALMOS
[468]	213	#define soft_name PREFIX_OS"bootloader.bin",\
	214	PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\
	215	PREFIX_OS"arch-info.bib@0xBFC08000:D"
[464]	216	#endif
	217	#ifdef USE_GIET
[468]	218	#define soft_pathname PREFIX_OS"soft.elf"
[464]	219	#endif
[344]	220
	221	////////////////////////////////////////////////////////////
	222	// DEBUG Parameters default values
	223	//////////////////////i/////////////////////////////////////
	224
	225	#define MAX_FROZEN_CYCLES 10000
	226
	227	/////////////////////////////////////////////////////////
	228	// Physical segments definition
	229	/////////////////////////////////////////////////////////
	230	// There is 3 segments replicated in all clusters
	231	// and 5 specific segments in the "IO" cluster
	232	// (containing address 0xBF000000)
	233	/////////////////////////////////////////////////////////
	234
	235	// specific segments in "IO" cluster : absolute physical address
	236
[396]	237	#define BROM_BASE 0x00BFC00000
	238	#define BROM_SIZE 0x0000100000 // 1 Mbytes
[344]	239
[396]	240	#define FBUF_BASE 0x00B2000000
[464]	241	#define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE * 2
[344]	242
[396]	243	#define BDEV_BASE 0x00B3000000
	244	#define BDEV_SIZE 0x0000001000 // 4 Kbytes
[344]	245
[396]	246	#define MTTY_BASE 0x00B4000000
	247	#define MTTY_SIZE 0x0000001000 // 4 Kbytes
[344]	248
[396]	249	#define MNIC_BASE 0x00B5000000
[402]	250	#define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels)
[344]	251
[475]	252	#define CHBUF_BASE 0x00B6000000
	253	#define CHBUF_SIZE 0x0000004000 // For 16 Channels
	254
[344]	255	// replicated segments : address is incremented by a cluster offset
	256	// offset = cluster(x,y) << (address_width-x_width-y_width);
	257
[396]	258	#define MEMC_BASE 0x0000000000
	259	#define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster
[344]	260
[396]	261	#define XICU_BASE 0x00B0000000
	262	#define XICU_SIZE 0x0000001000 // 4 Kbytes
[344]	263
[396]	264	#define MDMA_BASE 0x00B1000000
	265	#define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel
[344]	266
	267	////////////////////////////////////////////////////////////////////
	268	// TGTID definition in direct space
	269	// For all components: global TGTID = global SRCID = cluster_index
	270	////////////////////////////////////////////////////////////////////
	271
[396]	272	#define MEMC_TGTID 0
	273	#define XICU_TGTID 1
	274	#define MDMA_TGTID 2
	275	#define MTTY_TGTID 3
	276	#define FBUF_TGTID 4
	277	#define BDEV_TGTID 5
[438]	278	#define MNIC_TGTID 6
	279	#define BROM_TGTID 7
[475]	280	#define CHBUF_TGTID 8
[344]	281
	282	/////////////////////////////////
	283	int _main(int argc, char *argv[])
	284	{
	285	using namespace sc_core;
	286	using namespace soclib::caba;
	287	using namespace soclib::common;
	288
[464]	289	#ifdef USE_GIET
[468]	290	char soft_name[256] = soft_pathname; // pathname to binary code
[464]	291	#endif
[468]	292	uint64_t ncycles = 100000000000; // simulated cycles
[344]	293	char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
	294	char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file
	295	char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file
	296	ssize_t threads_nr = 1; // simulator's threads number
	297	bool debug_ok = false; // trace activated
	298	size_t debug_period = 1; // trace period
[438]	299	size_t debug_memc_id = 0; // index of memc to be traced
	300	size_t debug_proc_id = 0; // index of proc to be traced
[344]	301	uint32_t debug_from = 0; // trace start cycle
	302	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
[396]	303	size_t cluster_io_id = 0; // index of cluster containing IOs
[468]	304	struct timeval t1,t2;
[464]	305	uint64_t ms1,ms2;
[344]	306
	307	////////////// command line arguments //////////////////////
	308	if (argc > 1)
	309	{
	310	for (int n = 1; n < argc; n = n + 2)
	311	{
	312	if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
	313	{
	314	ncycles = atoi(argv[n+1]);
	315	}
	316	else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
	317	{
[464]	318	#ifdef USE_ALMOS
	319	assert( 0 && "Can't define almos soft name" );
	320	#endif
	321	#ifdef USE_GIET
[344]	322	strcpy(soft_name, argv[n+1]);
[464]	323	#endif
[344]	324	}
	325	else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
	326	{
	327	strcpy(disk_name, argv[n+1]);
	328	}
	329	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
	330	{
	331	debug_ok = true;
	332	debug_from = atoi(argv[n+1]);
	333	}
	334	else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
	335	{
	336	debug_memc_id = atoi(argv[n+1]);
[438]	337	assert( (debug_memc_id < (XMAX*YMAX) ) &&
[344]	338	"debug_memc_id larger than XMAX * YMAX" );
	339	}
	340	else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
	341	{
	342	debug_proc_id = atoi(argv[n+1]);
[438]	343	assert( (debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX) ) &&
[344]	344	"debug_proc_id larger than XMAX * YMAX * NB_PROCS" );
	345	}
	346	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
	347	{
	348	threads_nr = atoi(argv[n+1]);
	349	threads_nr = (threads_nr < 1) ? 1 : threads_nr;
	350	}
	351	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
	352	{
	353	frozen_cycles = atoi(argv[n+1]);
	354	}
	355	else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
	356	{
	357	debug_period = atoi(argv[n+1]);
	358	}
	359	else
	360	{
	361	std::cout << " Arguments are (key,value) couples." << std::endl;
	362	std::cout << " The order is not important." << std::endl;
	363	std::cout << " Accepted arguments are :" << std::endl << std::endl;
	364	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
	365	std::cout << " -DISK pathname_for_disk_image" << std::endl;
	366	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
	367	std::cout << " -DEBUG debug_start_cycle" << std::endl;
	368	std::cout << " -THREADS simulator's threads number" << std::endl;
	369	std::cout << " -FROZEN max_number_of_lines" << std::endl;
	370	std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
	371	std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
	372	std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
	373	exit(0);
	374	}
	375	}
	376	}
	377
[396]	378	// checking hardware parameters
[438]	379	assert( ( (XMAX == 1) or (XMAX == 2) or (XMAX == 4) or
	380	(XMAX == 8) or (XMAX == 16) ) and
	381	"The XMAX parameter must be 1, 2, 4, 8 or 16" );
[344]	382
[438]	383	assert( ( (YMAX == 1) or (YMAX == 2) or (YMAX == 4) or
	384	(YMAX == 8) or (YMAX == 16) ) and
	385	"The YMAX parameter must be 1, 2, 4, 8 or 16" );
[344]	386
[396]	387	assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
	388	(NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
	389	"The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
[344]	390
[396]	391	assert( (NB_DMA_CHANNELS < 9) and
	392	"The NB_DMA_CHANNELS parameter must be smaller than 9" );
[344]	393
[396]	394	assert( (NB_TTY_CHANNELS < 15) and
	395	"The NB_TTY_CHANNELS parameter must be smaller than 15" );
[344]	396
[396]	397	assert( (NB_NIC_CHANNELS < 9) and
	398	"The NB_NIC_CHANNELS parameter must be smaller than 9" );
[344]	399
[464]	400	#ifdef USE_GIET
[438]	401	assert( (vci_address_width == 40) and
[396]	402	"VCI address width must be 40 bits" );
[464]	403	#endif
[344]	404
[396]	405	std::cout << std::endl;
[438]	406	std::cout << " - XMAX = " << XMAX << std::endl;
	407	std::cout << " - YMAX = " << YMAX << std::endl;
	408	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
[396]	409	std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
[438]	410	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
	411	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
	412	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
	413	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
	414	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
	415	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
[396]	416
	417	std::cout << std::endl;
	418	// Internal and External VCI parameters definition
[438]	419	typedef soclib::caba::VciParams<vci_cell_width_int,
	420	vci_plen_width,
	421	vci_address_width,
	422	vci_rerror_width,
	423	vci_clen_width,
	424	vci_rflag_width,
	425	vci_srcid_width,
	426	vci_pktid_width,
	427	vci_trdid_width,
	428	vci_wrplen_width> vci_param_int;
[396]	429
[438]	430	typedef soclib::caba::VciParams<vci_cell_width_ext,
	431	vci_plen_width,
	432	vci_address_width,
	433	vci_rerror_width,
	434	vci_clen_width,
	435	vci_rflag_width,
	436	vci_srcid_width,
	437	vci_pktid_width,
	438	vci_trdid_width,
	439	vci_wrplen_width> vci_param_ext;
[396]	440
[344]	441	#if USE_OPENMP
	442	omp_set_dynamic(false);
	443	omp_set_num_threads(threads_nr);
	444	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
	445	#endif
	446
	447	// Define parameters depending on mesh size
	448	size_t x_width;
	449	size_t y_width;
	450
[438]	451	if (XMAX == 1) x_width = 0;
	452	else if (XMAX == 2) x_width = 1;
	453	else if (XMAX <= 4) x_width = 2;
	454	else if (XMAX <= 8) x_width = 3;
[389]	455	else x_width = 4;
[344]	456
[438]	457	if (YMAX == 1) y_width = 0;
	458	else if (YMAX == 2) y_width = 1;
	459	else if (YMAX <= 4) y_width = 2;
	460	else if (YMAX <= 8) y_width = 3;
[389]	461	else y_width = 4;
[344]	462
	463	/////////////////////
	464	// Mapping Tables
	465	/////////////////////
	466
[396]	467	// internal network
[438]	468	MappingTable maptabd(vci_address_width,
[396]	469	IntTab(x_width + y_width, 16 - x_width - y_width),
[438]	470	IntTab(x_width + y_width, vci_srcid_width - x_width - y_width),
[396]	471	0x00FF000000);
[344]	472
[438]	473	for (size_t x = 0; x < XMAX; x++)
[344]	474	{
[438]	475	for (size_t y = 0; y < YMAX; y++)
[344]	476	{
[438]	477	sc_uint<vci_address_width> offset;
	478	offset = (sc_uint<vci_address_width>)cluster(x,y)
	479	<< (vci_address_width-x_width-y_width);
[344]	480
	481	std::ostringstream sh;
[396]	482	sh << "seg_memc_" << x << "_" << y;
	483	maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE,
	484	IntTab(cluster(x,y),MEMC_TGTID), true));
[344]	485
	486	std::ostringstream si;
[396]	487	si << "seg_xicu_" << x << "_" << y;
	488	maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE,
	489	IntTab(cluster(x,y),XICU_TGTID), false));
[344]	490
	491	std::ostringstream sd;
[396]	492	sd << "seg_mdma_" << x << "_" << y;
	493	maptabd.add(Segment(sd.str(), MDMA_BASE+offset, MDMA_SIZE,
	494	IntTab(cluster(x,y),MDMA_TGTID), false));
[344]	495
	496	if ( cluster(x,y) == cluster_io_id )
	497	{
[396]	498	maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE,
	499	IntTab(cluster(x,y),MTTY_TGTID), false));
	500	maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE,
	501	IntTab(cluster(x,y),FBUF_TGTID), false));
	502	maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE,
	503	IntTab(cluster(x,y),BDEV_TGTID), false));
	504	maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE,
	505	IntTab(cluster(x,y),MNIC_TGTID), false));
[475]	506	maptabd.add(Segment("seg_chbuf", CHBUF_BASE, CHBUF_SIZE,
	507	IntTab(cluster(x,y),CHBUF_TGTID), false));
[396]	508	maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE,
	509	IntTab(cluster(x,y),BROM_TGTID), true));
[344]	510	}
	511	}
	512	}
	513	std::cout << maptabd << std::endl;
	514
	515	// external network
[438]	516	MappingTable maptabx(vci_address_width,
[396]	517	IntTab(x_width+y_width),
	518	IntTab(x_width+y_width),
	519	0xFFFF000000ULL);
[344]	520
[438]	521	for (size_t x = 0; x < XMAX; x++)
[344]	522	{
[438]	523	for (size_t y = 0; y < YMAX ; y++)
[344]	524	{
[396]	525
[438]	526	sc_uint<vci_address_width> offset;
	527	offset = (sc_uint<vci_address_width>)cluster(x,y)
	528	<< (vci_address_width-x_width-y_width);
[396]	529
[344]	530	std::ostringstream sh;
	531	sh << "x_seg_memc_" << x << "_" << y;
[396]	532
[344]	533	maptabx.add(Segment(sh.str(), MEMC_BASE+offset,
	534	MEMC_SIZE, IntTab(cluster(x,y)), false));
	535	}
	536	}
	537	std::cout << maptabx << std::endl;
	538
	539	////////////////////
	540	// Signals
	541	///////////////////
	542
[389]	543	sc_clock signal_clk("clk");
[344]	544	sc_signal<bool> signal_resetn("resetn");
	545
	546	// Horizontal inter-clusters DSPIN signals
[396]	547	DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc =
[468]	548	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 3);
[396]	549	DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec =
[468]	550	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 3);
[396]	551	DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc =
[438]	552	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2);
[396]	553	DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec =
[438]	554	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX, 2);
[344]	555
	556	// Vertical inter-clusters DSPIN signals
[396]	557	DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc =
[468]	558	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 3);
[396]	559	DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec =
[468]	560	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 3);
[396]	561	DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc =
[438]	562	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2);
[396]	563	DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec =
[438]	564	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1, 2);
[344]	565
	566	// Mesh boundaries DSPIN signals
[396]	567	DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in =
[468]	568	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , XMAX, YMAX, 4, 3);
[396]	569	DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out =
[468]	570	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 4, 3);
[396]	571	DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in =
[468]	572	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , XMAX, YMAX, 4, 2);
[396]	573	DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out =
[468]	574	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 4, 2);
[344]	575
	576
	577	////////////////////////////
	578	// Loader
	579	////////////////////////////
	580
	581	soclib::common::Loader loader(soft_name);
	582
	583	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
	584	proc_iss::set_loader(loader);
	585
	586	////////////////////////////
	587	// Clusters construction
	588	////////////////////////////
	589
[396]	590	TsarXbarCluster<dspin_cmd_width,
	591	dspin_rsp_width,
	592	vci_param_int,
[438]	593	vci_param_ext>* clusters[XMAX][YMAX];
[344]	594
	595	#if USE_OPENMP
	596	#pragma omp parallel
	597	{
	598	#pragma omp for
	599	#endif
[438]	600	for(size_t i = 0; i < (XMAX * YMAX); i++)
[344]	601	{
[438]	602	size_t x = i / YMAX;
	603	size_t y = i % YMAX;
[344]	604
	605	#if USE_OPENMP
	606	#pragma omp critical
	607	{
	608	#endif
[438]	609	std::cout << std::endl;
	610	std::cout << "Cluster_" << x << "_" << y << std::endl;
	611	std::cout << std::endl;
[389]	612
[344]	613	std::ostringstream sc;
	614	sc << "cluster_" << x << "_" << y;
[396]	615	clusters[x][y] = new TsarXbarCluster<dspin_cmd_width,
	616	dspin_rsp_width,
	617	vci_param_int,
	618	vci_param_ext>
[344]	619	(
	620	sc.str().c_str(),
[396]	621	NB_PROCS_MAX,
	622	NB_TTY_CHANNELS,
	623	NB_DMA_CHANNELS,
	624	x,
	625	y,
	626	cluster(x,y),
	627	maptabd,
	628	maptabx,
	629	x_width,
	630	y_width,
[438]	631	vci_srcid_width - x_width - y_width, // l_id width,
[396]	632	MEMC_TGTID,
	633	XICU_TGTID,
	634	MDMA_TGTID,
	635	FBUF_TGTID,
	636	MTTY_TGTID,
	637	BROM_TGTID,
	638	MNIC_TGTID,
[475]	639	CHBUF_TGTID,
[396]	640	BDEV_TGTID,
	641	MEMC_WAYS,
	642	MEMC_SETS,
	643	L1_IWAYS,
	644	L1_ISETS,
	645	L1_DWAYS,
	646	L1_DSETS,
	647	XRAM_LATENCY,
	648	(cluster(x,y) == cluster_io_id),
	649	FBUF_X_SIZE,
	650	FBUF_Y_SIZE,
	651	disk_name,
	652	BDEV_SECTOR_SIZE,
	653	NB_NIC_CHANNELS,
	654	nic_rx_name,
	655	nic_tx_name,
	656	NIC_TIMEOUT,
	657	loader,
[344]	658	frozen_cycles,
[389]	659	debug_from ,
[344]	660	debug_ok and (cluster(x,y) == debug_memc_id),
	661	debug_ok and (cluster(x,y) == debug_proc_id)
	662	);
	663
	664	#if USE_OPENMP
	665	} // end critical
	666	#endif
	667	} // end for
	668	#if USE_OPENMP
	669	}
	670	#endif
	671
	672	///////////////////////////////////////////////////////////////
	673	// Net-list
	674	///////////////////////////////////////////////////////////////
	675
	676	// Clock & RESET
[438]	677	for (size_t x = 0; x < (XMAX); x++){
	678	for (size_t y = 0; y < YMAX; y++){
[389]	679	clusters[x][y]->p_clk (signal_clk);
	680	clusters[x][y]->p_resetn (signal_resetn);
[344]	681	}
	682	}
	683
	684	// Inter Clusters horizontal connections
[438]	685	if (XMAX > 1){
	686	for (size_t x = 0; x < (XMAX-1); x++){
	687	for (size_t y = 0; y < YMAX; y++){
[468]	688	for (size_t k = 0; k < 3; k++){
[465]	689	clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]);
	690	clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]);
	691	clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]);
	692	clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]);
[468]	693	}
	694
	695	for (size_t k = 0; k < 2; k++){
[465]	696	clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]);
	697	clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]);
	698	clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]);
	699	clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]);
[344]	700	}
	701	}
	702	}
	703	}
	704	std::cout << std::endl << "Horizontal connections established" << std::endl;
	705
	706	// Inter Clusters vertical connections
[438]	707	if (YMAX > 1) {
	708	for (size_t y = 0; y < (YMAX-1); y++){
	709	for (size_t x = 0; x < XMAX; x++){
[468]	710	for (size_t k = 0; k < 3; k++){
[465]	711	clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]);
	712	clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]);
	713	clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]);
	714	clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]);
[468]	715	}
	716
	717	for (size_t k = 0; k < 2; k++){
[465]	718	clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]);
	719	clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]);
	720	clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]);
	721	clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]);
[344]	722	}
	723	}
	724	}
	725	}
	726	std::cout << "Vertical connections established" << std::endl;
	727
	728	// East & West boundary cluster connections
[438]	729	for (size_t y = 0; y < YMAX; y++)
[344]	730	{
[468]	731	for (size_t k = 0; k < 3; k++)
	732	{
	733	clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]);
	734	clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]);
	735	clusters[XMAX-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[XMAX-1][y][EAST][k]);
	736	clusters[XMAX-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[XMAX-1][y][EAST][k]);
	737	}
	738
[344]	739	for (size_t k = 0; k < 2; k++)
	740	{
[468]	741	clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]);
	742	clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]);
	743	clusters[XMAX-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[XMAX-1][y][EAST][k]);
	744	clusters[XMAX-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[XMAX-1][y][EAST][k]);
[344]	745	}
	746	}
	747
	748	// North & South boundary clusters connections
[438]	749	for (size_t x = 0; x < XMAX; x++)
[344]	750	{
[468]	751	for (size_t k = 0; k < 3; k++)
	752	{
	753	clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]);
	754	clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]);
	755	clusters[x][YMAX-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][YMAX-1][NORTH][k]);
	756	clusters[x][YMAX-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][YMAX-1][NORTH][k]);
	757	}
	758
[344]	759	for (size_t k = 0; k < 2; k++)
	760	{
[468]	761	clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]);
	762	clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]);
	763	clusters[x][YMAX-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][YMAX-1][NORTH][k]);
	764	clusters[x][YMAX-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][YMAX-1][NORTH][k]);
[344]	765	}
	766	}
[396]	767	std::cout << "North, South, West, East connections established" << std::endl;
	768	std::cout << std::endl;
[344]	769
	770
	771	////////////////////////////////////////////////////////
	772	// Simulation
	773	///////////////////////////////////////////////////////
	774
	775	sc_start(sc_core::sc_time(0, SC_NS));
	776	signal_resetn = false;
	777
	778	// network boundaries signals
[438]	779	for (size_t x = 0; x < XMAX ; x++){
	780	for (size_t y = 0; y < YMAX ; y++){
[468]	781	for (size_t a = 0; a < 4; a++){
	782	for (size_t k = 0; k < 3; k++){
	783	signal_dspin_false_cmd_in [x][y][a][k].write = false;
	784	signal_dspin_false_cmd_in [x][y][a][k].read = true;
	785	signal_dspin_false_cmd_out[x][y][a][k].write = false;
	786	signal_dspin_false_cmd_out[x][y][a][k].read = true;
	787	}
[344]	788
[468]	789	for (size_t k = 0; k < 2; k++){
	790	signal_dspin_false_rsp_in [x][y][a][k].write = false;
	791	signal_dspin_false_rsp_in [x][y][a][k].read = true;
	792	signal_dspin_false_rsp_out[x][y][a][k].write = false;
	793	signal_dspin_false_rsp_out[x][y][a][k].read = true;
[344]	794	}
	795	}
	796	}
	797	}
	798
	799	sc_start(sc_core::sc_time(1, SC_NS));
	800	signal_resetn = true;
	801
[464]	802	if (gettimeofday(&t1, NULL) != 0)
	803	{
	804	perror("gettimeofday");
	805	return EXIT_FAILURE;
	806	}
	807
[468]	808	for (uint64_t n = 1; n < ncycles; n++)
[344]	809	{
[396]	810	// Monitor a specific address for L1 & L2 caches
	811	//clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL);
	812	//clusters[1][0]->memc->copies_monitor(0x800002C000ULL);
	813
[464]	814	if( (n % 5000000) == 0)
	815	{
	816
	817	if (gettimeofday(&t2, NULL) != 0)
	818	{
	819	perror("gettimeofday");
	820	return EXIT_FAILURE;
	821	}
	822
	823	ms1 = (uint64_t)t1.tv_sec * 1000ULL + (uint64_t)t1.tv_usec / 1000;
	824	ms2 = (uint64_t)t2.tv_sec * 1000ULL + (uint64_t)t2.tv_usec / 1000;
	825	std::cerr << "platform clock frequency " << (double)5000000 / (double)(ms2 - ms1) << "Khz" << std::endl;
	826
	827	if (gettimeofday(&t1, NULL) != 0)
	828	{
	829	perror("gettimeofday");
	830	return EXIT_FAILURE;
	831	}
	832	}
	833
[344]	834	if (debug_ok and (n > debug_from) and (n % debug_period == 0))
	835	{
	836	std::cout << "****************** cycle " << std::dec << n ;
	837	std::cout << " ************************************************" << std::endl;
	838
[379]	839	// trace proc[debug_proc_id]
[438]	840	size_t l = debug_proc_id % NB_PROCS_MAX ;
	841	size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ;
	842	size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ;
[379]	843
[438]	844	std::ostringstream proc_signame;
	845	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
	846	std::ostringstream p2m_signame;
	847	p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ;
	848	std::ostringstream m2p_signame;
	849	m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ;
	850	std::ostringstream p_cmd_signame;
	851	p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ;
	852	std::ostringstream p_rsp_signame;
	853	p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ;
[379]	854
[438]	855	clusters[x][y]->proc[l]->print_trace();
	856	clusters[x][y]->wi_proc[l]->print_trace();
	857	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
	858	clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str());
	859	clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str());
	860	clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str());
	861	clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str());
[404]	862
[438]	863	clusters[x][y]->xbar_rsp_d->print_trace();
	864	clusters[x][y]->xbar_cmd_d->print_trace();
	865	clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD");
	866	clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD");
	867	clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP");
	868	clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP");
[404]	869
[379]	870	// trace memc[debug_memc_id]
[438]	871	x = debug_memc_id / YMAX;
	872	y = debug_memc_id % YMAX;
[344]	873
[438]	874	std::ostringstream smemc;
	875	smemc << "[SIG]MEMC_" << x << "_" << y;
	876	std::ostringstream sxram;
	877	sxram << "[SIG]XRAM_" << x << "_" << y;
	878	std::ostringstream sm2p;
	879	sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ;
	880	std::ostringstream sp2m;
	881	sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ;
	882	std::ostringstream m_cmd_signame;
	883	m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ;
	884	std::ostringstream m_rsp_signame;
	885	m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ;
[344]	886
[438]	887	clusters[x][y]->memc->print_trace();
	888	clusters[x][y]->wt_memc->print_trace();
	889	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
	890	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
	891	clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str());
	892	clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str());
	893	clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str());
	894	clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str());
[396]	895
	896	// trace replicated peripherals
[404]	897	// clusters[1][1]->mdma->print_trace();
	898	// clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1");
	899	// clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1");
[396]	900
	901
[379]	902	// trace external peripherals
[438]	903	size_t io_x = cluster_io_id / YMAX;
	904	size_t io_y = cluster_io_id % YMAX;
[379]	905
[404]	906	clusters[io_x][io_y]->brom->print_trace();
	907	clusters[io_x][io_y]->wt_brom->print_trace();
	908	clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM");
	909	clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD");
	910	clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP");
[396]	911
[404]	912	// clusters[io_x][io_y]->bdev->print_trace();
	913	// clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
	914	// clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
[344]	915	}
	916
	917	sc_start(sc_core::sc_time(1, SC_NS));
	918	}
	919	return EXIT_SUCCESS;
	920	}
	921
	922	int sc_main (int argc, char *argv[])
	923	{
	924	try {
	925	return _main(argc, argv);
	926	} catch (std::exception &e) {
	927	std::cout << e.what() << std::endl;
	928	} catch (...) {
	929	std::cout << "Unknown exception occured" << std::endl;
	930	throw;
	931	}
	932	return 1;
	933	}
	934
	935
	936	// Local Variables:
	937	// tab-width: 3
	938	// c-basic-offset: 3
	939	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	940	// indent-tabs-mode: nil
	941	// End:
	942
	943	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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