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source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 475

Last change on this file since 475 was 475, checked in by lambert, 11 years ago

Introducing Vci_Chbuf_Dma in tsar_generic_xbar platform :

The number of channels of the is dma is 2* nic_channels
Adding one argument to the tsar_xbar_cluster for dma TGTID
Chbuf Dma default address is 0x00B6000000

Changing Vci_Multi_Nic default Mac address to BABEBEEF0000

File size: 36.0 KB

Rev	Line
[345]	1	//////////////////////////////////////////////////////////////////////////////
[378]	2	// File: tsar_xbar_cluster.cpp
[428]	3	// Author: Alain Greiner
[345]	4	// Copyright: UPMC/LIP6
	5	// Date : march 2011
	6	// This program is released under the GNU public license
	7	//////////////////////////////////////////////////////////////////////////////
	8	// This file define a TSAR cluster architecture with virtual memory:
[428]	9	// - It uses two virtual_dspin_router as distributed global interconnect
	10	// - It uses four dspin_local_crossbar as local interconnect
[345]	11	// - It uses the vci_cc_vcache_wrapper
	12	// - It uses the vci_mem_cache
	13	// - It contains a private RAM with a variable latency to emulate the L3 cache
	14	// - It can contains 1, 2 or 4 processors
	15	// - Each processor has a private dma channel (vci_multi_dma)
	16	// - It uses the vci_xicu interrupt controller
[396]	17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
[428]	18	// - The Multi-TTY component controls up to 15 terminals.
[345]	19	// - Each Multi-DMA component controls up to 8 DMA channels.
	20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
	21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
	22	// - The BDEV IRQ is connected to IRQ_IN[31]
[428]	23	//////////////////////////////////////////////////////////////////////////////////
[345]	24
[378]	25	#include "../include/tsar_xbar_cluster.h"
[345]	26
[389]	27
[345]	28	namespace soclib {
	29	namespace caba {
	30
[396]	31	////////////////////////////////////////////////////////////////////////////////////
[428]	32	template<size_t dspin_cmd_width,
[396]	33	size_t dspin_rsp_width,
	34	typename vci_param_int,
	35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
	36	dspin_rsp_width,
	37	vci_param_int,
	38	vci_param_ext>::TsarXbarCluster(
	39	////////////////////////////////////////////////////////////////////////////////////
[345]	40	sc_module_name insname,
	41	size_t nb_procs,
	42	size_t nb_ttys,
	43	size_t nb_dmas,
	44	size_t x_id,
	45	size_t y_id,
	46	size_t cluster_id,
	47	const soclib::common::MappingTable &mtd,
[428]	48	const soclib::common::MappingTable &mtx,
[345]	49	size_t x_width,
	50	size_t y_width,
	51	size_t l_width,
	52	size_t tgtid_memc,
	53	size_t tgtid_xicu,
	54	size_t tgtid_mdma,
	55	size_t tgtid_fbuf,
	56	size_t tgtid_mtty,
	57	size_t tgtid_brom,
	58	size_t tgtid_mnic,
[475]	59	size_t tgtid_chbuf,
[345]	60	size_t tgtid_bdev,
	61	size_t memc_ways,
	62	size_t memc_sets,
	63	size_t l1_i_ways,
	64	size_t l1_i_sets,
	65	size_t l1_d_ways,
	66	size_t l1_d_sets,
	67	size_t xram_latency,
	68	bool io,
	69	size_t xfb,
	70	size_t yfb,
	71	char* disk_name,
	72	size_t block_size,
	73	size_t nic_channels,
	74	char* nic_rx_name,
	75	char* nic_tx_name,
	76	uint32_t nic_timeout,
	77	const Loader &loader,
	78	uint32_t frozen_cycles,
	79	uint32_t debug_start_cycle,
	80	bool memc_debug_ok,
	81	bool proc_debug_ok)
	82	: soclib::caba::BaseModule(insname),
	83	p_clk("clk"),
	84	p_resetn("resetn")
	85
	86	{
	87	// Vectors of ports definition
[468]	88	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 4, 3);
	89	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 4, 3);
[465]	90	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 4, 2);
	91	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 4, 2);
[345]	92
[396]	93	/////////////////////////////////////////////////////////////////////////////
[428]	94	// Components definition
[345]	95	/////////////////////////////////////////////////////////////////////////////
	96
	97	for (size_t p = 0; p < nb_procs; p++)
[428]	98	{
[345]	99	std::ostringstream sproc;
[396]	100	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
	101	proc[p] = new VciCcVCacheWrapper<vci_param_int,
	102	dspin_cmd_width,
[428]	103	dspin_rsp_width,
[396]	104	GdbServer<Mips32ElIss> >(
[345]	105	sproc.str().c_str(),
	106	cluster_id*nb_procs + p, // GLOBAL PROC_ID
[428]	107	mtd, // Mapping Table
[345]	108	IntTab(cluster_id,p), // SRCID
	109	(cluster_id << l_width) + p, // CC_GLOBAL_ID
	110	8, // ITLB ways
	111	8, // ITLB sets
	112	8, // DTLB ways
	113	8, // DTLB sets
	114	l1_i_ways,l1_i_sets,16, // ICACHE size
	115	l1_d_ways,l1_d_sets,16, // DCACHE size
	116	4, // WBUF nlines
	117	4, // WBUF nwords
	118	x_width,
	119	y_width,
	120	frozen_cycles, // max frozen cycles
	121	debug_start_cycle,
	122	proc_debug_ok);
	123
	124	std::ostringstream swip;
[435]	125	swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
[396]	126	wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
	127	dspin_cmd_width,
	128	dspin_rsp_width>(
[351]	129	swip.str().c_str(),
[363]	130	x_width + y_width + l_width);
[345]	131	}
	132
	133	/////////////////////////////////////////////////////////////////////////////
[396]	134	std::ostringstream smemc;
	135	smemc << "memc_" << x_id << "_" << y_id;
	136	memc = new VciMemCache<vci_param_int,
	137	vci_param_ext,
	138	dspin_rsp_width,
	139	dspin_cmd_width>(
	140	smemc.str().c_str(),
[345]	141	mtd, // Mapping Table direct space
	142	mtx, // Mapping Table external space
	143	IntTab(cluster_id), // SRCID external space
	144	IntTab(cluster_id, tgtid_memc), // TGTID direct space
	145	(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
	146	memc_ways, memc_sets, 16, // CACHE SIZE
	147	3, // MAX NUMBER OF COPIES
	148	4096, // HEAP SIZE
	149	8, // TRANSACTION TABLE DEPTH
	150	8, // UPDATE TABLE DEPTH
[468]	151	8, // INVALIDATE TABLE DEPTH
[345]	152	debug_start_cycle,
	153	memc_debug_ok );
	154
[396]	155	wt_memc = new VciDspinTargetWrapper<vci_param_int,
	156	dspin_cmd_width,
	157	dspin_rsp_width>(
[379]	158	"wt_memc",
[363]	159	x_width + y_width + l_width);
[345]	160
	161	/////////////////////////////////////////////////////////////////////////////
[396]	162	std::ostringstream sxram;
	163	sxram << "xram_" << x_id << "_" << y_id;
	164	xram = new VciSimpleRam<vci_param_ext>(
	165	sxram.str().c_str(),
[345]	166	IntTab(cluster_id),
	167	mtx,
	168	loader,
	169	xram_latency);
[379]	170
[345]	171	/////////////////////////////////////////////////////////////////////////////
[396]	172	std::ostringstream sxicu;
	173	sxicu << "xicu_" << x_id << "_" << y_id;
	174	xicu = new VciXicu<vci_param_int>(
	175	sxicu.str().c_str(),
[345]	176	mtd, // mapping table
	177	IntTab(cluster_id, tgtid_xicu), // TGTID_D
	178	nb_procs, // number of timer IRQs
	179	32, // number of hard IRQs
[389]	180	32, // number of soft IRQs
[345]	181	nb_procs); // number of output IRQs
	182
[396]	183	wt_xicu = new VciDspinTargetWrapper<vci_param_int,
	184	dspin_cmd_width,
	185	dspin_rsp_width>(
[379]	186	"wt_xicu",
[363]	187	x_width + y_width + l_width);
[345]	188
	189	/////////////////////////////////////////////////////////////////////////////
[396]	190	std::ostringstream smdma;
	191	smdma << "mdma_" << x_id << "_" << y_id;
	192	mdma = new VciMultiDma<vci_param_int>(
	193	smdma.str().c_str(),
[345]	194	mtd,
	195	IntTab(cluster_id, nb_procs), // SRCID
	196	IntTab(cluster_id, tgtid_mdma), // TGTID
	197	64, // burst size
[379]	198	nb_dmas); // number of IRQs
[345]	199
[396]	200	wt_mdma = new VciDspinTargetWrapper<vci_param_int,
	201	dspin_cmd_width,
	202	dspin_rsp_width>(
[379]	203	"wt_mdma",
[363]	204	x_width + y_width + l_width);
[345]	205
[396]	206	wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
	207	dspin_cmd_width,
	208	dspin_rsp_width>(
[379]	209	"wi_mdma",
[363]	210	x_width + y_width + l_width);
[345]	211
	212	/////////////////////////////////////////////////////////////////////////////
	213	size_t nb_direct_initiators = nb_procs + 1;
	214	size_t nb_direct_targets = 3;
	215	if ( io )
	216	{
[475]	217	nb_direct_initiators = nb_procs + 3;
	218	nb_direct_targets = 9;
[345]	219	}
	220
[396]	221	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
[379]	222	"xbar_cmd_d",
[345]	223	mtd, // mapping table
	224	x_id, y_id, // cluster coordinates
	225	x_width, y_width, l_width,
	226	nb_direct_initiators, // number of local of sources
[435]	227	nb_direct_targets, // number of local dests
	228	2, 2, // fifo depths
	229	true, // CMD
	230	true, // use local routing table
	231	false ); // no broadcast
[345]	232
	233	/////////////////////////////////////////////////////////////////////////////
[396]	234	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
[379]	235	"xbar_rsp_d",
[345]	236	mtd, // mapping table
	237	x_id, y_id, // cluster coordinates
	238	x_width, y_width, l_width,
[428]	239	nb_direct_targets, // number of local sources
[345]	240	nb_direct_initiators, // number of local dests
[435]	241	2, 2, // fifo depths
	242	false, // RSP
	243	false, // don't use local routing table
	244	false ); // no broadcast
[345]	245
	246	/////////////////////////////////////////////////////////////////////////////
[396]	247	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
[379]	248	"xbar_m2p_c",
[345]	249	mtd, // mapping table
	250	x_id, y_id, // cluster coordinates
	251	x_width, y_width, l_width,
	252	1, // number of local sources
[435]	253	nb_procs, // number of local targets
[428]	254	2, 2, // fifo depths
[435]	255	true, // CMD
[345]	256	false, // don't use local routing table
[435]	257	true ); // broadcast
[345]	258
	259	/////////////////////////////////////////////////////////////////////////////
[396]	260	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
[379]	261	"xbar_p2m_c",
[345]	262	mtd, // mapping table
	263	x_id, y_id, // cluster coordinates
[379]	264	x_width, y_width, 0, // l_width unused on p2m network
[345]	265	nb_procs, // number of local sources
	266	1, // number of local dests
[428]	267	2, 2, // fifo depths
[435]	268	false, // RSP
[345]	269	false, // don't use local routing table
[435]	270	false ); // no broadcast
[345]	271
	272	/////////////////////////////////////////////////////////////////////////////
[468]	273	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
	274	"xbar_clack_c",
	275	mtd, // mapping table
	276	x_id, y_id, // cluster coordinates
	277	x_width, y_width, l_width,
	278	1, // number of local sources
	279	nb_procs, // number of local targets
	280	1, 1, // fifo depths
	281	true, // CMD
	282	false, // don't use local routing table
	283	false); // broadcast
	284
	285	/////////////////////////////////////////////////////////////////////////////
[396]	286	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
[379]	287	"router_cmd",
[345]	288	x_id,y_id, // coordinate in the mesh
	289	x_width, y_width, // x & y fields width
[468]	290	3, // nb virtual channels
[345]	291	4,4); // input & output fifo depths
	292
	293	/////////////////////////////////////////////////////////////////////////////
[396]	294	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
[379]	295	"router_rsp",
[345]	296	x_id,y_id, // coordinates in mesh
	297	x_width, y_width, // x & y fields width
[465]	298	2, // nb virtual channels
[345]	299	4,4); // input & output fifo depths
	300
	301	// IO cluster components
	302	if ( io )
	303	{
	304	/////////////////////////////////////////////
[435]	305	brom = new VciSimpleRom<vci_param_int>(
[396]	306	"brom",
	307	IntTab(cluster_id, tgtid_brom),
	308	mtd,
	309	loader);
[345]	310
[396]	311	wt_brom = new VciDspinTargetWrapper<vci_param_int,
	312	dspin_cmd_width,
	313	dspin_rsp_width>(
	314	"wt_brom",
[363]	315	x_width + y_width + l_width);
[345]	316
	317	/////////////////////////////////////////////
[396]	318	fbuf = new VciFrameBuffer<vci_param_int>(
	319	"fbuf",
	320	IntTab(cluster_id, tgtid_fbuf),
	321	mtd,
[428]	322	xfb, yfb);
[345]	323
[396]	324	wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
	325	dspin_cmd_width,
	326	dspin_rsp_width>(
	327	"wt_fbuf",
[363]	328	x_width + y_width + l_width);
[345]	329
	330	/////////////////////////////////////////////
[396]	331	bdev = new VciBlockDeviceTsar<vci_param_int>(
	332	"bdev",
	333	mtd,
	334	IntTab(cluster_id, nb_procs+1),
	335	IntTab(cluster_id, tgtid_bdev),
	336	disk_name,
	337	block_size,
	338	64); // burst size
[345]	339
[396]	340	wt_bdev = new VciDspinTargetWrapper<vci_param_int,
	341	dspin_cmd_width,
	342	dspin_rsp_width>(
	343	"wt_bdev",
[363]	344	x_width + y_width + l_width);
[396]	345
	346	wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
	347	dspin_cmd_width,
	348	dspin_rsp_width>(
	349	"wi_bdev",
[363]	350	x_width + y_width + l_width);
[345]	351
	352	/////////////////////////////////////////////
[475]	353	int mac = 0xBEEF0000;
[396]	354	mnic = new VciMultiNic<vci_param_int>(
	355	"mnic",
	356	IntTab(cluster_id, tgtid_mnic),
	357	mtd,
	358	nic_channels,
	359	nic_rx_name,
	360	nic_tx_name,
[475]	361	mac, // mac_4 address
	362	0xBABE ); // mac_2 address
[345]	363
[396]	364	wt_mnic = new VciDspinTargetWrapper<vci_param_int,
	365	dspin_cmd_width,
	366	dspin_rsp_width>(
	367	"wt_mnic",
[363]	368	x_width + y_width + l_width);
[345]	369
	370	/////////////////////////////////////////////
[475]	371	chbuf = new VciChbufDma<vci_param_int>(
	372	"chbuf_dma",
	373	mtd,
	374	IntTab(cluster_id, nb_procs + 2),
	375	IntTab(cluster_id, tgtid_chbuf),
	376	64,
	377	2 * nic_channels ); // Two chbuf dma channel by nic channel
	378
	379	wt_chbuf = new VciDspinTargetWrapper<vci_param_int,
	380	dspin_cmd_width,
	381	dspin_rsp_width>(
	382	"wt_chbuf",
	383	x_width + y_width + l_width);
	384
	385	wi_chbuf = new VciDspinInitiatorWrapper<vci_param_int,
	386	dspin_cmd_width,
	387	dspin_rsp_width>(
	388	"wi_chbuf",
	389	x_width + y_width + l_width);
	390
	391	/////////////////////////////////////////////
[345]	392	std::vector<std::string> vect_names;
	393	for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
	394	{
	395	std::ostringstream term_name;
	396	term_name << "term" << tid;
	397	vect_names.push_back(term_name.str().c_str());
	398	}
[396]	399	mtty = new VciMultiTty<vci_param_int>(
	400	"mtty",
	401	IntTab(cluster_id, tgtid_mtty),
[428]	402	mtd,
[396]	403	vect_names);
[345]	404
[396]	405	wt_mtty = new VciDspinTargetWrapper<vci_param_int,
	406	dspin_cmd_width,
	407	dspin_rsp_width>(
	408	"wt_mtty",
[363]	409	x_width + y_width + l_width);
[345]	410	}
	411
	412	////////////////////////////////////
	413	// Connections are defined here
	414	////////////////////////////////////
	415
	416	//////////////////////// CMD ROUTER and RSP ROUTER
	417	router_cmd->p_clk (this->p_clk);
	418	router_cmd->p_resetn (this->p_resetn);
	419	router_rsp->p_clk (this->p_clk);
	420	router_rsp->p_resetn (this->p_resetn);
[465]	421
	422	for(int i = 0; i < 4; i++)
[345]	423	{
[468]	424	for (int k = 0; k < 3; k++)
[345]	425	{
[465]	426	router_cmd->p_out[i][k] (this->p_cmd_out[i][k]);
	427	router_cmd->p_in[i][k] (this->p_cmd_in[i][k]);
[468]	428	}
	429
	430	for (int k = 0; k < 2; k++)
	431	{
[465]	432	router_rsp->p_out[i][k] (this->p_rsp_out[i][k]);
	433	router_rsp->p_in[i][k] (this->p_rsp_in[i][k]);
[345]	434	}
	435	}
	436
[465]	437	router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d);
	438	router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c);
[468]	439	router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c);
[465]	440	router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d);
	441	router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c);
[468]	442	router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c);
[345]	443
[465]	444	router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d);
	445	router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c);
	446	router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d);
	447	router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c);
[345]	448
[468]	449
[345]	450	std::cout << " - CMD & RSP routers connected" << std::endl;
	451
	452	///////////////////// CMD DSPIN local crossbar direct
	453	xbar_cmd_d->p_clk (this->p_clk);
	454	xbar_cmd_d->p_resetn (this->p_resetn);
	455	xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d);
	456	xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d);
	457
	458	xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t);
	459	xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t);
	460	xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t);
	461
	462	xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i);
	463
	464	for (size_t p = 0; p < nb_procs; p++)
	465	xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]);
	466
	467	if ( io )
	468	{
	469	xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t);
	470	xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t);
	471	xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t);
	472	xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t);
	473	xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t);
[475]	474	xbar_cmd_d->p_local_out[tgtid_chbuf] (signal_dspin_cmd_chbuf_t);
[345]	475
	476	xbar_cmd_d->p_local_in[nb_procs+1] (signal_dspin_cmd_bdev_i);
[475]	477	xbar_cmd_d->p_local_in[nb_procs+2] (signal_dspin_cmd_chbuf_i);
[345]	478	}
	479
	480	std::cout << " - Command Direct crossbar connected" << std::endl;
	481
	482	//////////////////////// RSP DSPIN local crossbar direct
	483	xbar_rsp_d->p_clk (this->p_clk);
	484	xbar_rsp_d->p_resetn (this->p_resetn);
	485	xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d);
	486	xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d);
	487
	488	xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t);
	489	xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t);
	490	xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t);
	491
	492	xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i);
	493
	494	for (size_t p = 0; p < nb_procs; p++)
	495	xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]);
	496
	497	if ( io )
	498	{
	499	xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t);
	500	xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t);
	501	xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t);
	502	xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t);
	503	xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t);
[475]	504	xbar_rsp_d->p_local_in[tgtid_chbuf] (signal_dspin_rsp_chbuf_t);
[345]	505
	506	xbar_rsp_d->p_local_out[nb_procs+1] (signal_dspin_rsp_bdev_i);
[475]	507	xbar_rsp_d->p_local_out[nb_procs+2] (signal_dspin_rsp_chbuf_i);
[345]	508	}
	509
	510	std::cout << " - Response Direct crossbar connected" << std::endl;
	511
	512	////////////////////// M2P DSPIN local crossbar coherence
	513	xbar_m2p_c->p_clk (this->p_clk);
	514	xbar_m2p_c->p_resetn (this->p_resetn);
	515	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
	516	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
[360]	517	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
[428]	518	for (size_t p = 0; p < nb_procs; p++)
[345]	519	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
	520
	521	std::cout << " - M2P Coherence crossbar connected" << std::endl;
	522
[468]	523	////////////////////// CLACK DSPIN local crossbar coherence
	524	xbar_clack_c->p_clk (this->p_clk);
	525	xbar_clack_c->p_resetn (this->p_resetn);
	526	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
	527	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
	528	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
	529	for (size_t p = 0; p < nb_procs; p++)
	530	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
	531
	532	std::cout << " - Clack Coherence crossbar connected" << std::endl;
	533
[345]	534	////////////////////////// P2M DSPIN local crossbar coherence
	535	xbar_p2m_c->p_clk (this->p_clk);
	536	xbar_p2m_c->p_resetn (this->p_resetn);
	537	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
	538	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
[360]	539	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
[428]	540	for (size_t p = 0; p < nb_procs; p++)
[345]	541	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
	542
	543	std::cout << " - P2M Coherence crossbar connected" << std::endl;
	544
	545
	546	//////////////////////////////////// Processors
	547	for (size_t p = 0; p < nb_procs; p++)
	548	{
	549	proc[p]->p_clk (this->p_clk);
	550	proc[p]->p_resetn (this->p_resetn);
	551	proc[p]->p_vci (signal_vci_ini_proc[p]);
[468]	552	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
	553	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
	554	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
[345]	555	proc[p]->p_irq[0] (signal_proc_it[p]);
	556	for ( size_t j = 1 ; j < 6 ; j++)
	557	{
	558	proc[p]->p_irq[j] (signal_false);
	559	}
	560
	561	wi_proc[p]->p_clk (this->p_clk);
	562	wi_proc[p]->p_resetn (this->p_resetn);
	563	wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]);
	564	wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]);
	565	wi_proc[p]->p_vci (signal_vci_ini_proc[p]);
	566	}
	567
	568	std::cout << " - Processors connected" << std::endl;
	569
	570	///////////////////////////////////// XICU
[428]	571	xicu->p_clk (this->p_clk);
	572	xicu->p_resetn (this->p_resetn);
	573	xicu->p_vci (signal_vci_tgt_xicu);
[345]	574	for ( size_t p=0 ; p<nb_procs ; p++)
	575	{
[428]	576	xicu->p_irq[p] (signal_proc_it[p]);
[345]	577	}
	578	for ( size_t i=0 ; i<32 ; i++)
	579	{
	580	if ( io ) // I/O cluster
	581	{
	582	if (i < 8) xicu->p_hwi[i] (signal_false);
[428]	583	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
[345]	584	else if (i < 16) xicu->p_hwi[i] (signal_false);
	585	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]);
[428]	586	else if (i < 31) xicu->p_hwi[i] (signal_false);
[345]	587	else xicu->p_hwi[i] (signal_irq_bdev);
	588	}
	589	else // other clusters
	590	{
	591	if (i < 8) xicu->p_hwi[i] (signal_false);
[428]	592	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
	593	else xicu->p_hwi[i] (signal_false);
[345]	594	}
	595	}
	596
	597	// wrapper XICU
[360]	598	wt_xicu->p_clk (this->p_clk);
	599	wt_xicu->p_resetn (this->p_resetn);
	600	wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t);
	601	wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t);
	602	wt_xicu->p_vci (signal_vci_tgt_xicu);
[345]	603
	604	std::cout << " - XICU connected" << std::endl;
	605
	606	//////////////////////////////////////////////// MEMC
[428]	607	memc->p_clk (this->p_clk);
	608	memc->p_resetn (this->p_resetn);
	609	memc->p_vci_ixr (signal_vci_xram);
	610	memc->p_vci_tgt (signal_vci_tgt_memc);
[468]	611	memc->p_dspin_p2m (signal_dspin_p2m_memc);
	612	memc->p_dspin_m2p (signal_dspin_m2p_memc);
	613	memc->p_dspin_clack (signal_dspin_clack_memc);
[345]	614
	615	// wrapper MEMC
[360]	616	wt_memc->p_clk (this->p_clk);
	617	wt_memc->p_resetn (this->p_resetn);
	618	wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t);
	619	wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t);
	620	wt_memc->p_vci (signal_vci_tgt_memc);
[345]	621
	622	std::cout << " - MEMC connected" << std::endl;
	623
	624	/////////////////////////////////////////////// XRAM
[428]	625	xram->p_clk (this->p_clk);
	626	xram->p_resetn (this->p_resetn);
	627	xram->p_vci (signal_vci_xram);
[345]	628
	629	std::cout << " - XRAM connected" << std::endl;
	630
[360]	631	////////////////////////////////////////////// MDMA
[428]	632	mdma->p_clk (this->p_clk);
	633	mdma->p_resetn (this->p_resetn);
	634	mdma->p_vci_target (signal_vci_tgt_mdma);
	635	mdma->p_vci_initiator (signal_vci_ini_mdma);
[345]	636	for (size_t i=0 ; i<nb_dmas ; i++)
	637	mdma->p_irq[i] (signal_irq_mdma[i]);
	638
[360]	639	// wrapper tgt MDMA
	640	wt_mdma->p_clk (this->p_clk);
	641	wt_mdma->p_resetn (this->p_resetn);
	642	wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t);
	643	wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t);
	644	wt_mdma->p_vci (signal_vci_tgt_mdma);
	645
	646	// wrapper ini MDMA
	647	wi_mdma->p_clk (this->p_clk);
	648	wi_mdma->p_resetn (this->p_resetn);
	649	wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i);
	650	wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i);
	651	wi_mdma->p_vci (signal_vci_ini_mdma);
	652
[345]	653	std::cout << " - MDMA connected" << std::endl;
	654
[428]	655	/////////////////////////////// Components in I/O cluster
[345]	656
[428]	657	if ( io )
	658	{
	659	// BDEV
	660	bdev->p_clk (this->p_clk);
[345]	661	bdev->p_resetn (this->p_resetn);
	662	bdev->p_irq (signal_irq_bdev);
	663	bdev->p_vci_target (signal_vci_tgt_bdev);
	664	bdev->p_vci_initiator (signal_vci_ini_bdev);
	665
[360]	666	// wrapper tgt BDEV
	667	wt_bdev->p_clk (this->p_clk);
	668	wt_bdev->p_resetn (this->p_resetn);
	669	wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t);
	670	wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t);
	671	wt_bdev->p_vci (signal_vci_tgt_bdev);
	672
	673	// wrapper ini BDEV
	674	wi_bdev->p_clk (this->p_clk);
	675	wi_bdev->p_resetn (this->p_resetn);
	676	wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i);
	677	wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i);
	678	wi_bdev->p_vci (signal_vci_ini_bdev);
	679
[345]	680	std::cout << " - BDEV connected" << std::endl;
	681
	682	// FBUF
	683	fbuf->p_clk (this->p_clk);
	684	fbuf->p_resetn (this->p_resetn);
	685	fbuf->p_vci (signal_vci_tgt_fbuf);
	686
[360]	687	// wrapper tgt FBUF
	688	wt_fbuf->p_clk (this->p_clk);
	689	wt_fbuf->p_resetn (this->p_resetn);
	690	wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t);
	691	wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t);
	692	wt_fbuf->p_vci (signal_vci_tgt_fbuf);
	693
[345]	694	std::cout << " - FBUF connected" << std::endl;
	695
	696	// MNIC
	697	mnic->p_clk (this->p_clk);
	698	mnic->p_resetn (this->p_resetn);
	699	mnic->p_vci (signal_vci_tgt_mnic);
	700	for ( size_t i=0 ; i<nic_channels ; i++ )
	701	{
	702	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
	703	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
	704	}
	705
[360]	706	// wrapper tgt MNIC
	707	wt_mnic->p_clk (this->p_clk);
	708	wt_mnic->p_resetn (this->p_resetn);
	709	wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t);
	710	wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t);
	711	wt_mnic->p_vci (signal_vci_tgt_mnic);
	712
[345]	713	std::cout << " - MNIC connected" << std::endl;
	714
[475]	715	// CHBUF
	716	chbuf->p_clk (this->p_clk);
	717	chbuf->p_resetn (this->p_resetn);
	718	chbuf->p_vci_target (signal_vci_tgt_chbuf);
	719	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
	720	for ( size_t i=0 ; i < nic_channels * 2 ; i++ )
	721	{
	722	chbuf->p_irq[i] (signal_irq_chbuf[i]);
	723	}
	724
	725	// wrapper tgt CHBUF
	726	wt_chbuf->p_clk (this->p_clk);
	727	wt_chbuf->p_resetn (this->p_resetn);
	728	wt_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_t);
	729	wt_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_t);
	730	wt_chbuf->p_vci (signal_vci_tgt_chbuf);
	731
	732	// wrapper ini CHBUF
	733	wi_chbuf->p_clk (this->p_clk);
	734	wi_chbuf->p_resetn (this->p_resetn);
	735	wi_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_i);
	736	wi_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_i);
	737	wi_chbuf->p_vci (signal_vci_ini_chbuf);
	738
	739	std::cout << " - CHBUF connected" << std::endl;
	740
[345]	741	// BROM
	742	brom->p_clk (this->p_clk);
	743	brom->p_resetn (this->p_resetn);
	744	brom->p_vci (signal_vci_tgt_brom);
	745
[360]	746	// wrapper tgt BROM
	747	wt_brom->p_clk (this->p_clk);
	748	wt_brom->p_resetn (this->p_resetn);
	749	wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t);
	750	wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t);
	751	wt_brom->p_vci (signal_vci_tgt_brom);
	752
[345]	753	std::cout << " - BROM connected" << std::endl;
	754
	755	// MTTY
	756	mtty->p_clk (this->p_clk);
	757	mtty->p_resetn (this->p_resetn);
	758	mtty->p_vci (signal_vci_tgt_mtty);
	759	for ( size_t i=0 ; i<nb_ttys ; i++ )
	760	{
[428]	761	mtty->p_irq[i] (signal_irq_mtty[i]);
[345]	762	}
	763
[360]	764	// wrapper tgt MTTY
	765	wt_mtty->p_clk (this->p_clk);
	766	wt_mtty->p_resetn (this->p_resetn);
	767	wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t);
	768	wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t);
	769	wt_mtty->p_vci (signal_vci_tgt_mtty);
	770
[345]	771	std::cout << " - MTTY connected" << std::endl;
	772	}
	773	} // end constructor
	774
[396]	775	}}
[345]	776
	777	// Local Variables:
	778	// tab-width: 3
	779	// c-basic-offset: 3
	780	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	781	// indent-tabs-mode: nil
	782	// End:
	783
	784	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
	785
	786
	787

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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