1 | ///////////////////////////////////////////////////////////////////////// |
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2 | // File: top.cpp |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : august 2012 |
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6 | // This program is released under the GNU public license |
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7 | ///////////////////////////////////////////////////////////////////////// |
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8 | // This file define a generic TSAR architecture with virtual memory. |
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9 | // - It uses vci_local_crossbar as local interconnect |
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10 | // - It uses virtual_dspin as global interconnect |
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11 | // - It uses the vci_cc_vcache_wrapper_v4 |
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12 | // - It uses the vci_mem_cache_v4 |
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13 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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14 | // The peripherals BDEV, FBUF, MTTY, and the boot BROM |
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15 | // are in the cluster containing address 0xBFC00000. |
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16 | // |
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17 | // It is build with one single component implementing a cluster: |
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18 | // The Tsarv4ClusterMmu component is defined in files |
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19 | // tsarv4_cluster_mmu.* (with * = cpp, h, sd) |
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20 | // |
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21 | // The IRQs are connected to XICUs as follow: |
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22 | // - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. |
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23 | // - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. |
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24 | // - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. |
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25 | // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. |
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26 | // |
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27 | // The physical address space is 32 bits. |
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28 | // The number of clusters cannot be larger than 256. |
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29 | // The number of processors per cluster cannot be larger than 8. |
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30 | // |
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31 | // The hardware parameters are : |
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32 | // - xmax : number of clusters in a row (power of 2) |
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33 | // - ymax : number of clusters in a column (power of 2) |
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34 | // - nb_procs : number of processors per cluster (power of 2) |
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35 | // - nb_dmas : number of DMA channels per cluster (< 9) |
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36 | // - nb_ttys : number of TTYs in I/O cluster (< 16) |
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37 | // |
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38 | // General policy for 32 bits physical address decoding: |
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39 | // All segments base addresses are multiple of 64 Kbytes |
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40 | // Therefore the 16 address MSB bits completely define the target: |
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41 | // The (x_width + y_width) MSB bits (left aligned) define |
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42 | // the cluster index, and the 8 LSB bits define the local index: |
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43 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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44 | // |x_width|y_width|---| 8 | 16 | |
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45 | ///////////////////////////////////////////////////////////////////////// |
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46 | |
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47 | #include <systemc> |
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48 | #include <sys/time.h> |
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49 | #include <iostream> |
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50 | #include <sstream> |
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51 | #include <cstdlib> |
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52 | #include <cstdarg> |
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53 | #include <stdint.h> |
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54 | |
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55 | #include "gdbserver.h" |
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56 | #include "mapping_table.h" |
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57 | #include "tsarv4_cluster_mmu.h" |
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58 | #include "alloc_elems.h" |
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59 | |
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60 | /////////////////////////////////////////////////// |
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61 | // OS |
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62 | /////////////////////////////////////////////////// |
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63 | |
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64 | #define USE_ALMOS 0 |
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65 | #define almos_bootloader_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/bootloader/bin/bootloader-soclib-mipsel.bin" |
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66 | #define almos_kernel_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/kernel/bin/kernel-soclib-mipsel.bin@0xbfc10000:D" |
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67 | #define almos_archinfo_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/arch_bins/arch-info_4_4.bin@0xBFC08000:D" |
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68 | |
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69 | /////////////////////////////////////////////////// |
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70 | // Parallelisation |
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71 | /////////////////////////////////////////////////// |
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72 | |
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73 | #define USE_OPENMP 0 |
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74 | #define OPENMP_THREADS_NR 8 |
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75 | |
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76 | #if USE_OPENMP |
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77 | #include <omp.h> |
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78 | #endif |
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79 | |
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80 | // cluster index (computed from x,y coordinates) |
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81 | #define cluster(x,y) (y + ymax*x) |
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82 | |
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83 | // flit widths for the DSPIN network |
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84 | #define cmd_width 40 |
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85 | #define rsp_width 33 |
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86 | |
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87 | // VCI format |
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88 | #define cell_width 4 |
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89 | #define address_width 32 |
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90 | #define plen_width 8 |
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91 | #define error_width 2 |
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92 | #define clen_width 1 |
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93 | #define rflag_width 1 |
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94 | #define srcid_width 14 |
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95 | #define pktid_width 4 |
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96 | #define trdid_width 4 |
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97 | #define wrplen_width 1 |
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98 | |
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99 | /////////////////////////////////////////////////// |
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100 | // Parameters default values |
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101 | /////////////////////////////////////////////////// |
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102 | |
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103 | #define MESH_XMAX 2 |
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104 | #define MESH_YMAX 2 |
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105 | |
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106 | #define NB_PROCS 1 |
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107 | #define NB_TTYS 8 |
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108 | #define NB_DMAS 1 |
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109 | |
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110 | #define XRAM_LATENCY 0 |
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111 | |
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112 | #define MEMC_WAYS 16 |
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113 | #define MEMC_SETS 256 |
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114 | |
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115 | #define L1_IWAYS 4 |
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116 | #define L1_ISETS 64 |
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117 | |
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118 | #define L1_DWAYS 4 |
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119 | #define L1_DSETS 64 |
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120 | |
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121 | #define FBUF_X_SIZE 128 |
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122 | #define FBUF_Y_SIZE 128 |
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123 | |
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124 | #define BDEV_SECTOR_SIZE 512 |
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125 | #define BDEV_IMAGE_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/display/images.raw" |
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126 | |
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127 | #define BOOT_SOFT_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/soft.elf" |
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128 | |
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129 | #define MAX_FROZEN_CYCLES 10000 |
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130 | |
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131 | #define TRACE_MEMC_ID 1000000 |
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132 | #define TRACE_PROC_ID 1000000 |
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133 | |
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134 | ///////////////////////////////////////////////////////// |
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135 | // Physical segments definition |
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136 | ///////////////////////////////////////////////////////// |
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137 | // There is 3 segments replicated in all clusters: |
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138 | // - seg_memc -> MEMC / BASE = 0x**000000 (12 M bytes) |
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139 | // - seg_icu -> ICU / BASE = 0x**F00000 |
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140 | // - seg_dma -> CDMA / BASE = 0x**F30000 |
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141 | // |
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142 | // There is 4 specific segments in the "IO" cluster |
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143 | // (containing address 0xBF000000) |
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144 | // - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) |
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145 | // - seg_fbuf -> FBUF / BASE = 0xBFD00000 (2 M bytes) |
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146 | // - seg_bdev -> BDEV / BASE = 0xBFF10000 |
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147 | // - seg_tty -> MTTY / BASE = 0x**F20000 |
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148 | // |
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149 | // There is one special segment corresponding to |
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150 | // the processors in the coherence address space |
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151 | // - seg_proc -> PROC / BASE = 0x**B0 to 0xBF |
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152 | /////////////////////////////////////////////////// |
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153 | |
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154 | // specific segments in "IO" cluster : absolute physical address |
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155 | |
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156 | #define BROM_BASE 0xBFC00000 |
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157 | #define BROM_SIZE 0x00100000 |
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158 | |
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159 | #define FBUF_BASE 0x80D00000 |
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160 | #define FBUF_SIZE 0x00200000 |
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161 | |
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162 | #define BDEV_BASE 0x80F10000 |
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163 | #define BDEV_SIZE 0x00001000 |
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164 | |
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165 | #define MTTY_BASE 0x80F20000 |
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166 | #define MTTY_SIZE 0x00001000 |
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167 | |
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168 | // replicated segments : physical address is incremented by an offset |
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169 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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170 | |
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171 | #define MEMC_BASE 0x00000000 |
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172 | #define MEMC_SIZE 0x00C00000 |
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173 | |
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174 | #define XICU_BASE 0x00F00000 |
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175 | #define XICU_SIZE 0x00001000 |
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176 | |
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177 | #define CDMA_BASE 0x00F30000 |
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178 | #define CDMA_SIZE 0x00008000 |
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179 | |
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180 | //////////////////////////////////////////////////////////////////// |
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181 | // TGTID definition in direct space |
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182 | // For all components: global TGTID = global SRCID = cluster_index |
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183 | //////////////////////////////////////////////////////////////////// |
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184 | |
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185 | #define MEMC_TGTID 0 |
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186 | #define XICU_TGTID 1 |
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187 | #define CDMA_TGTID 2 |
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188 | #define MTTY_TGTID 3 |
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189 | #define FBUF_TGTID 4 |
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190 | #define BROM_TGTID 5 |
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191 | #define BDEV_TGTID 6 |
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192 | |
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193 | ///////////////////////////////// |
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194 | int _main(int argc, char *argv[]) |
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195 | { |
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196 | using namespace sc_core; |
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197 | using namespace soclib::caba; |
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198 | using namespace soclib::common; |
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199 | |
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200 | |
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201 | char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code |
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202 | size_t ncycles = 1000000000; // simulated cycles |
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203 | size_t xmax = MESH_XMAX; // number of clusters in a row |
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204 | size_t ymax = MESH_YMAX; // number of clusters in a column |
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205 | size_t nb_procs = NB_PROCS; // number of processors per cluster |
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206 | size_t nb_dmas = NB_DMAS; // number of RDMA channels per cluster |
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207 | size_t nb_ttys = NB_TTYS; // number of TTY terminals in I/O cluster |
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208 | size_t xfb = FBUF_X_SIZE; // frameBuffer column number |
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209 | size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number |
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210 | size_t memc_ways = MEMC_WAYS; |
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211 | size_t memc_sets = MEMC_SETS; |
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212 | size_t l1_d_ways = L1_DWAYS; |
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213 | size_t l1_d_sets = L1_DSETS; |
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214 | size_t l1_i_ways = L1_IWAYS; |
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215 | size_t l1_i_sets = L1_ISETS; |
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216 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image |
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217 | size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) |
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218 | size_t xram_latency = XRAM_LATENCY; // external RAM latency |
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219 | bool debug_ok = false; // trace activated |
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220 | size_t debug_period = 1; // trace period |
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221 | size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) |
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222 | size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced |
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223 | uint32_t debug_from = 0; // trace start cycle |
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224 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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225 | |
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226 | ////////////// command line arguments ////////////////////// |
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227 | if (argc > 1) |
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228 | { |
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229 | for (int n = 1; n < argc; n = n + 2) |
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230 | { |
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231 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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232 | { |
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233 | ncycles = atoi(argv[n+1]); |
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234 | } |
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235 | else if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc)) |
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236 | { |
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237 | nb_procs = atoi(argv[n+1]); |
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238 | assert( ((nb_procs == 1) || (nb_procs == 2) || |
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239 | (nb_procs == 4) || (nb_procs == 8)) && |
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240 | "NPROCS must be equal to 1, 2, 4, or 8"); |
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241 | } |
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242 | else if ((strcmp(argv[n],"-NTTYS") == 0) && (n+1<argc)) |
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243 | { |
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244 | nb_ttys = atoi(argv[n+1]); |
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245 | assert( (nb_ttys < 16) && |
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246 | "The number of TTY terminals cannot be larger than 15"); |
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247 | } |
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248 | else if ((strcmp(argv[n],"-NDMAS") == 0) && (n+1<argc)) |
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249 | { |
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250 | nb_dmas = atoi(argv[n+1]); |
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251 | assert( (nb_dmas < 9) && |
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252 | "The number of DMA channels per cluster cannot be larger than 8"); |
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253 | } |
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254 | else if ((strcmp(argv[n],"-XMAX") == 0) && (n+1<argc)) |
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255 | { |
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256 | xmax = atoi(argv[n+1]); |
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257 | assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) |
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258 | && "The XMAX parameter must be 2, 4, 8, or 16" ); |
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259 | } |
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260 | |
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261 | else if ((strcmp(argv[n],"-YMAX") == 0) && (n+1<argc)) |
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262 | { |
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263 | ymax = atoi(argv[n+1]); |
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264 | assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) |
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265 | && "The YMAX parameter must be 2, 4, 8, or 16" ); |
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266 | } |
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267 | else if ((strcmp(argv[n],"-XFB") == 0) && (n+1<argc)) |
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268 | { |
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269 | xfb = atoi(argv[n+1]); |
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270 | } |
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271 | else if ((strcmp(argv[n],"-YFB") == 0) && (n+1<argc) ) |
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272 | { |
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273 | yfb = atoi(argv[n+1]); |
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274 | } |
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275 | else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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276 | { |
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277 | strcpy(soft_name, argv[n+1]); |
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278 | } |
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279 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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280 | { |
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281 | strcpy(disk_name, argv[n+1]); |
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282 | } |
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283 | else if ((strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) ) |
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284 | { |
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285 | debug_ok = true; |
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286 | debug_from = atoi(argv[n+1]); |
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287 | } |
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288 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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289 | { |
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290 | debug_memc_id = atoi(argv[n+1]); |
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291 | assert( (debug_memc_id < (xmax*ymax) ) && |
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292 | "debug_memc_id larger than XMAX * YMAX" ); |
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293 | } |
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294 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
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295 | { |
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296 | debug_proc_id = atoi(argv[n+1]); |
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297 | assert( (debug_proc_id < (xmax*ymax*nb_procs) ) && |
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298 | "debug_proc_id larger than XMAX * YMAX * BN_PROCS" ); |
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299 | } |
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300 | else if ((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc)) |
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301 | { |
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302 | memc_ways = atoi(argv[n+1]); |
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303 | } |
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304 | else if ((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc)) |
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305 | { |
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306 | memc_sets = atoi(argv[n+1]); |
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307 | } |
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308 | else if ((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc)) |
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309 | { |
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310 | xram_latency = atoi(argv[n+1]); |
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311 | } |
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312 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
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313 | { |
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314 | frozen_cycles = atoi(argv[n+1]); |
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315 | } |
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316 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
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317 | { |
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318 | debug_period = atoi(argv[n+1]); |
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319 | } |
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320 | else |
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321 | { |
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322 | std::cout << " Arguments on the command line are (key,value) couples." << std::endl; |
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323 | std::cout << " The order is not important." << std::endl; |
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324 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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325 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
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326 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
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327 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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328 | std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; |
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329 | std::cout << " -NTTYS total_number_of_TTY_terminals" << std::endl; |
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330 | std::cout << " -NDMAS number_of_DMA_channels_per_cluster" << std::endl; |
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331 | std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl; |
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332 | std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl; |
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333 | std::cout << " -TRACE debug_start_cycle" << std::endl; |
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334 | std::cout << " -MCWAYS memory_cache_number_of_ways" << std::endl; |
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335 | std::cout << " -MCSETS memory_cache_number_of_sets" << std::endl; |
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336 | std::cout << " -XLATENCY external_ram_latency_value" << std::endl; |
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337 | std::cout << " -XFB fram_buffer_number_of_pixels" << std::endl; |
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338 | std::cout << " -YFB fram_buffer_number_of_lines" << std::endl; |
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339 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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340 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
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341 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
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342 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
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343 | exit(0); |
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344 | } |
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345 | } |
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346 | } |
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347 | |
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348 | std::cout << std::endl; |
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349 | std::cout << " - NB_CLUSTERS = " << xmax*ymax << std::endl; |
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350 | std::cout << " - NB_PROCS = " << nb_procs << std::endl; |
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351 | std::cout << " - NB_TTYS = " << nb_ttys << std::endl; |
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352 | std::cout << " - NB_DMAS = " << nb_dmas << std::endl; |
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353 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
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354 | std::cout << " - MEMC_WAYS = " << memc_ways << std::endl; |
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355 | std::cout << " - MEMC_SETS = " << memc_sets << std::endl; |
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356 | std::cout << " - RAM_LATENCY = " << xram_latency << std::endl; |
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357 | |
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358 | std::cout << std::endl; |
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359 | |
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360 | #if USE_OPENMP |
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361 | omp_set_dynamic(false); |
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362 | omp_set_num_threads(threads_nr); |
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363 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
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364 | #endif |
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365 | |
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366 | // Define VCI parameters |
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367 | typedef soclib::caba::VciParams<cell_width, |
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368 | plen_width, |
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369 | address_width, |
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370 | error_width, |
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371 | clen_width, |
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372 | rflag_width, |
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373 | srcid_width, |
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374 | pktid_width, |
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375 | trdid_width, |
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376 | wrplen_width> vci_param; |
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377 | |
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378 | // Define parameters depending on mesh size |
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379 | size_t cluster_io_id; |
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380 | size_t x_width; |
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381 | size_t y_width; |
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382 | |
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383 | if (xmax == 1) x_width = 0; |
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384 | else if (xmax == 2) x_width = 1; |
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385 | else if (xmax <= 4) x_width = 2; |
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386 | else if (xmax <= 8) x_width = 3; |
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387 | else x_width = 4; |
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388 | |
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389 | if (ymax == 1) y_width = 0; |
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390 | else if (ymax == 2) y_width = 1; |
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391 | else if (ymax <= 4) y_width = 2; |
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392 | else if (ymax <= 8) y_width = 3; |
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393 | else y_width = 4; |
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394 | |
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395 | cluster_io_id = 0xBF >> (8 - x_width - y_width); |
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396 | |
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397 | ///////////////////// |
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398 | // Mapping Tables |
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399 | ///////////////////// |
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400 | |
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401 | // direct network |
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402 | MappingTable maptabd(address_width, |
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403 | IntTab(x_width + y_width, 16 - x_width - y_width), |
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404 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
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405 | 0x00FF0000); |
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406 | |
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407 | for (size_t x = 0; x < xmax; x++) |
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408 | { |
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409 | for (size_t y = 0; y < ymax; y++) |
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410 | { |
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411 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
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412 | |
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413 | std::ostringstream sh; |
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414 | sh << "d_seg_memc_" << x << "_" << y; |
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415 | maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); |
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416 | |
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417 | std::ostringstream si; |
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418 | si << "d_seg_xicu_" << x << "_" << y; |
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419 | maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); |
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420 | |
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421 | std::ostringstream sd; |
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422 | sd << "d_seg_mdma_" << x << "_" << y; |
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423 | maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); |
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424 | |
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425 | if ( cluster(x,y) == cluster_io_id ) |
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426 | { |
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427 | maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); |
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428 | maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); |
---|
429 | maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); |
---|
430 | maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); |
---|
431 | } |
---|
432 | } |
---|
433 | } |
---|
434 | std::cout << maptabd << std::endl; |
---|
435 | |
---|
436 | // coherence network |
---|
437 | // - tgtid_c_proc = srcid_c_proc = local procid |
---|
438 | // - tgtid_c_memc = srcid_c_memc = nb_procs |
---|
439 | MappingTable maptabc(address_width, |
---|
440 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
---|
441 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
---|
442 | 0x00FF0000); |
---|
443 | |
---|
444 | for (size_t x = 0; x < xmax; x++) |
---|
445 | { |
---|
446 | for (size_t y = 0; y < ymax; y++) |
---|
447 | { |
---|
448 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
---|
449 | |
---|
450 | // cleanup requests must be routed to the memory cache |
---|
451 | std::ostringstream sh; |
---|
452 | sh << "c_seg_memc_" << x << "_" << y; |
---|
453 | maptabc.add(Segment(sh.str(), (nb_procs << (address_width - srcid_width)) + offset, |
---|
454 | 0x10, IntTab(cluster(x,y), nb_procs), false)); |
---|
455 | |
---|
456 | // update & invalidate requests must be routed to the proper processor |
---|
457 | for ( size_t p = 0 ; p < nb_procs ; p++) |
---|
458 | { |
---|
459 | std::ostringstream sp; |
---|
460 | sp << "c_seg_proc_" << x << "_" << y << "_" << p; |
---|
461 | maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , |
---|
462 | 0x10 , IntTab(cluster(x,y), p) , false)); |
---|
463 | } |
---|
464 | } |
---|
465 | } |
---|
466 | std::cout << maptabc << std::endl; |
---|
467 | |
---|
468 | // external network |
---|
469 | MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); |
---|
470 | |
---|
471 | for (size_t x = 0; x < xmax; x++) |
---|
472 | { |
---|
473 | for (size_t y = 0; y < ymax ; y++) |
---|
474 | { |
---|
475 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
---|
476 | std::ostringstream sh; |
---|
477 | sh << "x_seg_memc_" << x << "_" << y; |
---|
478 | maptabx.add(Segment(sh.str(), MEMC_BASE+offset, |
---|
479 | MEMC_SIZE, IntTab(cluster(x,y)), false)); |
---|
480 | } |
---|
481 | } |
---|
482 | std::cout << maptabx << std::endl; |
---|
483 | |
---|
484 | //////////////////// |
---|
485 | // Signals |
---|
486 | /////////////////// |
---|
487 | |
---|
488 | sc_clock signal_clk("clk"); |
---|
489 | sc_signal<bool> signal_resetn("resetn"); |
---|
490 | |
---|
491 | // Horizontal inter-clusters DSPIN signals |
---|
492 | DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc = |
---|
493 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2); |
---|
494 | DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec = |
---|
495 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2); |
---|
496 | DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc = |
---|
497 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2); |
---|
498 | DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec = |
---|
499 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2); |
---|
500 | |
---|
501 | // Vertical inter-clusters DSPIN signals |
---|
502 | DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc = |
---|
503 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2); |
---|
504 | DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec = |
---|
505 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2); |
---|
506 | DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc = |
---|
507 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2); |
---|
508 | DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec = |
---|
509 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2); |
---|
510 | |
---|
511 | // Mesh boundaries DSPIN signals |
---|
512 | DspinSignals<cmd_width>**** signal_dspin_false_cmd_in = |
---|
513 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4); |
---|
514 | DspinSignals<cmd_width>**** signal_dspin_false_cmd_out = |
---|
515 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4); |
---|
516 | DspinSignals<rsp_width>**** signal_dspin_false_rsp_in = |
---|
517 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4); |
---|
518 | DspinSignals<rsp_width>**** signal_dspin_false_rsp_out = |
---|
519 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4); |
---|
520 | |
---|
521 | |
---|
522 | //////////////////////////// |
---|
523 | // Components |
---|
524 | //////////////////////////// |
---|
525 | |
---|
526 | #if USE_ALMOS |
---|
527 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
528 | almos_archinfo_pathname, |
---|
529 | almos_kernel_pathname); |
---|
530 | #else |
---|
531 | soclib::common::Loader loader(soft_name); |
---|
532 | #endif |
---|
533 | |
---|
534 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
535 | proc_iss::set_loader(loader); |
---|
536 | |
---|
537 | TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax]; |
---|
538 | |
---|
539 | #if USE_OPENMP |
---|
540 | |
---|
541 | #pragma omp parallel |
---|
542 | { |
---|
543 | #pragma omp for |
---|
544 | for(size_t i = 0; i < (xmax * ymax); i++) |
---|
545 | { |
---|
546 | size_t x = i / ymax; |
---|
547 | size_t y = i % ymax; |
---|
548 | #pragma omp critical |
---|
549 | |
---|
550 | std::cout << "building cluster_" << x << "_" << y << std::endl; |
---|
551 | |
---|
552 | std::ostringstream sc; |
---|
553 | sc << "cluster_" << x << "_" << y; |
---|
554 | clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> |
---|
555 | (sc.str().c_str(), |
---|
556 | nb_procs, |
---|
557 | nb_ttys, |
---|
558 | nb_dmas, |
---|
559 | x, |
---|
560 | y, |
---|
561 | cluster(x,y), |
---|
562 | maptabd, |
---|
563 | maptabc, |
---|
564 | maptabx, |
---|
565 | x_width, |
---|
566 | y_width, |
---|
567 | MEMC_TGTID, |
---|
568 | XICU_TGTID, |
---|
569 | FBUF_TGTID, |
---|
570 | MTTY_TGTID, |
---|
571 | BROM_TGTID, |
---|
572 | BDEV_TGTID, |
---|
573 | CDMA_TGTID, |
---|
574 | memc_ways, |
---|
575 | memc_sets, |
---|
576 | l1_i_ways, |
---|
577 | l1_i_sets, |
---|
578 | l1_d_ways, |
---|
579 | l1_d_sets, |
---|
580 | xram_latency, |
---|
581 | (cluster(x,y) == cluster_io_id), |
---|
582 | xfb, |
---|
583 | yfb, |
---|
584 | disk_name, |
---|
585 | blk_size, |
---|
586 | loader, |
---|
587 | frozen_cycles, |
---|
588 | debug_from, |
---|
589 | debug_ok and (cluster(x,y) == debug_memc_id), |
---|
590 | debug_ok and (cluster(x,y) == debug_proc_id) ); |
---|
591 | |
---|
592 | std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; |
---|
593 | |
---|
594 | } |
---|
595 | } |
---|
596 | |
---|
597 | #else // NO OPENMP |
---|
598 | |
---|
599 | for (size_t x = 0; x < xmax; x++) |
---|
600 | { |
---|
601 | for (size_t y = 0; y < ymax; y++) |
---|
602 | { |
---|
603 | |
---|
604 | std::cout << "building cluster_" << x << "_" << y << std::endl; |
---|
605 | |
---|
606 | std::ostringstream sc; |
---|
607 | sc << "cluster_" << x << "_" << y; |
---|
608 | clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> |
---|
609 | (sc.str().c_str(), |
---|
610 | nb_procs, |
---|
611 | nb_ttys, |
---|
612 | nb_dmas, |
---|
613 | x, |
---|
614 | y, |
---|
615 | cluster(x,y), |
---|
616 | maptabd, |
---|
617 | maptabc, |
---|
618 | maptabx, |
---|
619 | x_width, |
---|
620 | y_width, |
---|
621 | MEMC_TGTID, |
---|
622 | XICU_TGTID, |
---|
623 | FBUF_TGTID, |
---|
624 | MTTY_TGTID, |
---|
625 | BROM_TGTID, |
---|
626 | BDEV_TGTID, |
---|
627 | CDMA_TGTID, |
---|
628 | memc_ways, |
---|
629 | memc_sets, |
---|
630 | l1_i_ways, |
---|
631 | l1_i_sets, |
---|
632 | l1_d_ways, |
---|
633 | l1_d_sets, |
---|
634 | xram_latency, |
---|
635 | (cluster(x,y) == cluster_io_id), |
---|
636 | xfb, |
---|
637 | yfb, |
---|
638 | disk_name, |
---|
639 | blk_size, |
---|
640 | loader, |
---|
641 | frozen_cycles, |
---|
642 | debug_from, |
---|
643 | debug_ok and ( cluster(x,y) == debug_memc_id ), |
---|
644 | debug_ok and ( cluster(x,y) == debug_proc_id ) ); |
---|
645 | |
---|
646 | std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; |
---|
647 | |
---|
648 | } |
---|
649 | } |
---|
650 | |
---|
651 | #endif // USE_OPENMP |
---|
652 | |
---|
653 | /////////////////////////////////////////////////////////////// |
---|
654 | // Net-list |
---|
655 | /////////////////////////////////////////////////////////////// |
---|
656 | |
---|
657 | // Clock & RESET |
---|
658 | for (size_t x = 0; x < (xmax); x++){ |
---|
659 | for (size_t y = 0; y < ymax; y++){ |
---|
660 | clusters[x][y]->p_clk (signal_clk); |
---|
661 | clusters[x][y]->p_resetn (signal_resetn); |
---|
662 | } |
---|
663 | } |
---|
664 | |
---|
665 | // Inter Clusters horizontal connections |
---|
666 | if (xmax > 1){ |
---|
667 | for (size_t x = 0; x < (xmax-1); x++){ |
---|
668 | for (size_t y = 0; y < ymax; y++){ |
---|
669 | for (size_t k = 0; k < 2; k++){ |
---|
670 | clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
671 | clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
672 | clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
673 | clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
674 | clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
675 | clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
676 | clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
677 | clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
678 | } |
---|
679 | } |
---|
680 | } |
---|
681 | } |
---|
682 | std::cout << "Horizontal connections established" << std::endl; |
---|
683 | |
---|
684 | // Inter Clusters vertical connections |
---|
685 | if (ymax > 1) { |
---|
686 | for (size_t y = 0; y < (ymax-1); y++){ |
---|
687 | for (size_t x = 0; x < xmax; x++){ |
---|
688 | for (size_t k = 0; k < 2; k++){ |
---|
689 | clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
690 | clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
691 | clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
692 | clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
693 | clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
694 | clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
695 | clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
696 | clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
697 | } |
---|
698 | } |
---|
699 | } |
---|
700 | } |
---|
701 | std::cout << "Vertical connections established" << std::endl; |
---|
702 | |
---|
703 | // East & West boundary cluster connections |
---|
704 | for (size_t y = 0; y < ymax; y++) |
---|
705 | { |
---|
706 | for (size_t k = 0; k < 2; k++) |
---|
707 | { |
---|
708 | clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); |
---|
709 | clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); |
---|
710 | clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); |
---|
711 | clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); |
---|
712 | |
---|
713 | clusters[xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]); |
---|
714 | clusters[xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]); |
---|
715 | clusters[xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]); |
---|
716 | clusters[xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]); |
---|
717 | } |
---|
718 | } |
---|
719 | |
---|
720 | // North & South boundary clusters connections |
---|
721 | for (size_t x = 0; x < xmax; x++) |
---|
722 | { |
---|
723 | for (size_t k = 0; k < 2; k++) |
---|
724 | { |
---|
725 | clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); |
---|
726 | clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); |
---|
727 | clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); |
---|
728 | clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); |
---|
729 | |
---|
730 | clusters[x][ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]); |
---|
731 | clusters[x][ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]); |
---|
732 | clusters[x][ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]); |
---|
733 | clusters[x][ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]); |
---|
734 | } |
---|
735 | } |
---|
736 | |
---|
737 | |
---|
738 | //////////////////////////////////////////////////////// |
---|
739 | // Simulation |
---|
740 | /////////////////////////////////////////////////////// |
---|
741 | |
---|
742 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
743 | signal_resetn = false; |
---|
744 | |
---|
745 | // network boundaries signals |
---|
746 | for (size_t x = 0; x < xmax ; x++){ |
---|
747 | for (size_t y = 0; y < ymax ; y++){ |
---|
748 | for (size_t k = 0; k < 2; k++){ |
---|
749 | for (size_t a = 0; a < 4; a++){ |
---|
750 | signal_dspin_false_cmd_in[x][y][k][a].write = false; |
---|
751 | signal_dspin_false_cmd_in[x][y][k][a].read = true; |
---|
752 | signal_dspin_false_cmd_out[x][y][k][a].write = false; |
---|
753 | signal_dspin_false_cmd_out[x][y][k][a].read = true; |
---|
754 | |
---|
755 | signal_dspin_false_rsp_in[x][y][k][a].write = false; |
---|
756 | signal_dspin_false_rsp_in[x][y][k][a].read = true; |
---|
757 | signal_dspin_false_rsp_out[x][y][k][a].write = false; |
---|
758 | signal_dspin_false_rsp_out[x][y][k][a].read = true; |
---|
759 | } |
---|
760 | } |
---|
761 | } |
---|
762 | } |
---|
763 | |
---|
764 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
765 | signal_resetn = true; |
---|
766 | |
---|
767 | for (size_t n = 1; n < ncycles; n++) |
---|
768 | { |
---|
769 | |
---|
770 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
771 | { |
---|
772 | std::cout << "****************** cycle " << std::dec << n ; |
---|
773 | std::cout << " ************************************************" << std::endl; |
---|
774 | |
---|
775 | // trace proc[debug_proc_id] |
---|
776 | if ( debug_proc_id < (xmax * ymax * nb_procs) ) |
---|
777 | { |
---|
778 | size_t proc_x = debug_proc_id / ymax; |
---|
779 | size_t proc_y = debug_proc_id % ymax; |
---|
780 | |
---|
781 | clusters[proc_x][proc_y]->proc[0]->print_trace(); |
---|
782 | |
---|
783 | clusters[proc_x][proc_y]->signal_vci_ini_d_proc[0].print_trace("proc_ini_d"); |
---|
784 | clusters[proc_x][proc_y]->signal_vci_ini_c_proc[0].print_trace("proc_ini_c"); |
---|
785 | clusters[proc_x][proc_y]->signal_vci_tgt_c_proc[0].print_trace("proc_tgt_c"); |
---|
786 | } |
---|
787 | |
---|
788 | // trace memc[debug_memc_id] |
---|
789 | if ( debug_memc_id < (xmax * ymax) ) |
---|
790 | { |
---|
791 | size_t memc_x = debug_memc_id / ymax; |
---|
792 | size_t memc_y = debug_memc_id % ymax; |
---|
793 | |
---|
794 | clusters[memc_x][memc_y]->memc->print_trace(); |
---|
795 | |
---|
796 | clusters[memc_x][memc_y]->signal_vci_tgt_d_memc.print_trace("memc_tgt_d"); |
---|
797 | clusters[memc_x][memc_y]->signal_vci_ini_c_memc.print_trace("memc_ini_c"); |
---|
798 | clusters[memc_x][memc_y]->signal_vci_tgt_c_memc.print_trace("memc_tgt_c"); |
---|
799 | } |
---|
800 | |
---|
801 | // clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0"); |
---|
802 | // clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1"); |
---|
803 | // clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0"); |
---|
804 | // clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1"); |
---|
805 | |
---|
806 | clusters[1][1]->mdma->print_trace(); |
---|
807 | clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("dma_tgt_1_1"); |
---|
808 | clusters[1][1]->signal_vci_ini_d_mdma.print_trace("dma_ini_1_1"); |
---|
809 | if ( clusters[1][1]->signal_irq_mdma[0].read() ) |
---|
810 | std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; |
---|
811 | if ( clusters[1][1]->signal_proc_it[0].read() ) |
---|
812 | std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; |
---|
813 | |
---|
814 | // trace peripherals components |
---|
815 | if ( false ) |
---|
816 | { |
---|
817 | size_t io_x = cluster_io_id / ymax; |
---|
818 | size_t io_y = cluster_io_id % ymax; |
---|
819 | |
---|
820 | clusters[io_x][io_y]->bdev->print_trace(); |
---|
821 | clusters[io_x][io_y]->mdma->print_trace(); |
---|
822 | |
---|
823 | clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); |
---|
824 | clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); |
---|
825 | clusters[io_x][io_y]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); |
---|
826 | clusters[io_x][io_y]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); |
---|
827 | } |
---|
828 | } |
---|
829 | |
---|
830 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
831 | } |
---|
832 | return EXIT_SUCCESS; |
---|
833 | } |
---|
834 | |
---|
835 | int sc_main (int argc, char *argv[]) |
---|
836 | { |
---|
837 | try { |
---|
838 | return _main(argc, argv); |
---|
839 | } catch (std::exception &e) { |
---|
840 | std::cout << e.what() << std::endl; |
---|
841 | } catch (...) { |
---|
842 | std::cout << "Unknown exception occured" << std::endl; |
---|
843 | throw; |
---|
844 | } |
---|
845 | return 1; |
---|
846 | } |
---|
847 | |
---|
848 | |
---|
849 | // Local Variables: |
---|
850 | // tab-width: 3 |
---|
851 | // c-basic-offset: 3 |
---|
852 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
853 | // indent-tabs-mode: nil |
---|
854 | // End: |
---|
855 | |
---|
856 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
857 | |
---|
858 | |
---|
859 | |
---|
860 | |
---|