source: trunk/softs/tsar_boot/drivers/reset_inval.c @ 962

Last change on this file since 962 was 962, checked in by alain, 10 years ago

Introducing a new IOC driver supporting the VciMultiAhci? disk controller (in polling mode only).
Extending the MMC driver to support the SYNC command requested by the AHCI protocol on the tsar_generic_iob platform.

File size: 1.9 KB
RevLine 
[758]1/**
2 * \file   reset_inval.c
3 * \date   December 14, 2014
[962]4 * \author Cesar Fuguet / Alain Greiner
[758]5 */
6
7#include <reset_inval.h>
8#include <io.h>
9#include <defs.h>
10
11#ifndef SEG_MMC_BASE
12#   error "SEG_MMC_BASE constant must be defined in the hard_config.h file"
13#endif
14
[962]15static int* const mmc_address = (int* const)SEG_MMC_BASE;
[758]16
17enum memc_registers
18{
[911]19    MCC_ADDR_LO   = 0,
20    MCC_ADDR_HI   = 1,
21    MCC_LENGTH    = 2,
22    MCC_CMD       = 3
[758]23};
24
25enum memc_operations
26{
27    MCC_CMD_NOP   = 0,
28    MCC_CMD_INVAL = 1,
29    MCC_CMD_SYNC  = 2
30};
31
32/**
[962]33 * \brief Invalidate all L1 cache lines corresponding to a memory buffer
34 *        (identified by an address and a size).
[758]35 */
[962]36void reset_L1_inval( void* const buffer, size_t size )
[758]37{
38    unsigned int i;
39
[911]40    // iterate on L1 cache lines containing target buffer
[758]41    for (i = 0; i <= size; i += CACHE_LINE_SIZE)
42    {
43        asm volatile(
44            " cache %0, %1"
45            : /* no outputs */
46            : "i" (0x11), "R" (*((char*)buffer + i))
[962]47            : "memory" );
[758]48    }
[962]49}
[758]50
[962]51/**
52 * \brief Invalidate all L2 cache lines corresponding to a memory buffer
53 *        (identified by an address and a size).
54 */
55void reset_L2_inval( void* const buffer, size_t size )
56{
57    iowrite32( &mmc_address[MCC_ADDR_LO], (unsigned int)buffer );
58    iowrite32( &mmc_address[MCC_ADDR_HI], 0 );
59    iowrite32( &mmc_address[MCC_LENGTH] , size );
60    iowrite32( &mmc_address[MCC_CMD]    , MCC_CMD_INVAL);
[758]61}
62
[962]63/**
64 * \brief Update external RAM for all L2 cache lines corresponding to
65 *        a memory buffer (identified by an address and a size).
66 */
67void reset_L2_sync ( void* const buffer, size_t size )
68{
69    iowrite32( &mmc_address[MCC_ADDR_LO], (unsigned int)buffer );
70    iowrite32( &mmc_address[MCC_ADDR_HI], 0 );
71    iowrite32( &mmc_address[MCC_LENGTH] , size );
72    iowrite32( &mmc_address[MCC_CMD]    , MCC_CMD_SYNC );
73}
74
[758]75/*
76 * vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab
77 */
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