Changeset 962 for trunk/softs/tsar_boot/drivers/reset_inval.c

Timestamp:

Apr 1, 2015, 3:42:03 PM (10 years ago)

Author:

alain

Message:

Introducing a new IOC driver supporting the VciMultiAhci? disk controller (in polling mode only).
Extending the MMC driver to support the SYNC command requested by the AHCI protocol on the tsar_generic_iob platform.

File:

• trunk/softs/tsar_boot/drivers/reset_inval.c (modified) (4 diffs)

trunk/softs/tsar_boot/drivers/reset_inval.c

@@ -2 +2 @@
  * \file   reset_inval.c
  * \date   December 14, 2014
- * \author Cesar Fuguet
+ * \author Cesar Fuguet / Alain Greiner
  */
 
@@ -13 +13 @@
 #endif
 
-static int* const mcc_address = (int* const)SEG_MMC_BASE;
+static int* const mmc_address = (int* const)SEG_MMC_BASE;
 
 enum memc_registers
@@ -31 +31 @@
 
 /**
- * \brief Invalidate all data cache lines corresponding to a memory buffer
- *        (identified by an address and a size) in L1 cache and L2 cache.
+ * \brief Invalidate all L1 cache lines corresponding to a memory buffer
+ *        (identified by an address and a size).
  */
-void reset_buf_invalidate (void* const buffer, size_t size, int inval_memc)
+void reset_L1_inval( void* const buffer, size_t size )
 {
     unsigned int i;
@@ -45 +45 @@
             : /* no outputs */
             : "i" (0x11), "R" (*((char*)buffer + i))
-            : "memory"
-            );
+            : "memory" );
     }
+}
 
-    if (inval_memc)
-    {
-        // this preloader uses only the cluster 0
-        // It does not use the ADDR_HI bits, and does not take
-        // any lock for exclusive access to MCC 
-        iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer);
-        iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0);
-        iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size);
-        iowrite32(&mcc_address[MCC_CMD]    , (unsigned int) MCC_CMD_INVAL);
-    }
+/**
+ * \brief Invalidate all L2 cache lines corresponding to a memory buffer
+ *        (identified by an address and a size).
+ */
+void reset_L2_inval( void* const buffer, size_t size )
+{
+    iowrite32( &mmc_address[MCC_ADDR_LO], (unsigned int)buffer );
+    iowrite32( &mmc_address[MCC_ADDR_HI], 0 );
+    iowrite32( &mmc_address[MCC_LENGTH] , size );
+    iowrite32( &mmc_address[MCC_CMD]    , MCC_CMD_INVAL);
+}
+
+/**
+ * \brief Update external RAM for all L2 cache lines corresponding to 
+ *        a memory buffer (identified by an address and a size).
+ */
+void reset_L2_sync ( void* const buffer, size_t size )
+{
+    iowrite32( &mmc_address[MCC_ADDR_LO], (unsigned int)buffer );
+    iowrite32( &mmc_address[MCC_ADDR_HI], 0 );
+    iowrite32( &mmc_address[MCC_LENGTH] , size );
+    iowrite32( &mmc_address[MCC_CMD]    , MCC_CMD_SYNC );
 }