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Last change
on this file since 613 was
567,
checked in by alain, 11 years ago
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Introducing CP2 registers mnemonics in mips32_registers.h
Supporting 40 bits physical addresses, multi-clusters TSAR
architectures: XICUs are accessed using the physical address
extension mechanism.
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File size:
2.4 KB
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| Rev | Line | |
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| [292] | 1 | /********************************************************************************/ |
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| 2 | /* File : mips32_registers.h */ |
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| 3 | /* Author : Alain Greiner */ |
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| 4 | /* Date : 26/03/2012 */ |
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| 5 | /* Modified by : Cesar Fuguet 10/02/2013 */ |
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| 6 | /********************************************************************************/ |
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| 7 | /* We define mnemonics for MIPS32 registers */ |
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| 8 | /********************************************************************************/ |
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| 9 | |
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| 10 | #ifndef _MIPS32_REGISTERS_H |
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| 11 | #define _MIPS32_REGISTERS_H |
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| 12 | |
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| 13 | /* processor registers */ |
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| 14 | |
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| 15 | #define zero $0 |
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| 16 | #define at $at |
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| 17 | #define v0 $2 |
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| 18 | #define v1 $3 |
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| 19 | #define a0 $4 |
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| 20 | #define a1 $5 |
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| 21 | #define a2 $6 |
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| 22 | #define a3 $7 |
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| 23 | #define t0 $8 |
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| 24 | #define t1 $9 |
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| 25 | #define t2 $10 |
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| 26 | #define t3 $11 |
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| 27 | #define t4 $12 |
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| 28 | #define t5 $13 |
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| 29 | #define t6 $14 |
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| 30 | #define t7 $15 |
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| 31 | #define s0 $16 |
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| 32 | #define s1 $17 |
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| 33 | #define s2 $18 |
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| 34 | #define s3 $19 |
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| 35 | #define s4 $20 |
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| 36 | #define s5 $21 |
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| 37 | #define s6 $22 |
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| 38 | #define s7 $23 |
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| 39 | #define t8 $24 |
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| 40 | #define t9 $25 |
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| 41 | #define k0 $26 |
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| 42 | #define k1 $27 |
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| 43 | #define gp $28 |
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| 44 | #define sp $29 |
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| 45 | #define fp $30 |
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| 46 | #define ra $31 |
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| 47 | |
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| 48 | /* CP0 registers */ |
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| 49 | |
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| 50 | #define CP0_COUNT $9 |
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| 51 | #define CP0_STATUS $12,0 |
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| 52 | #define CP0_CAUSE $13,0 |
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| 53 | #define CP0_EPC $14,0 |
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| 54 | #define CP0_EBASE $15,1 |
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| 55 | |
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| [567] | 56 | /* CP2 registers */ |
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| 57 | |
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| 58 | #define CP2_PTPR $0 |
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| 59 | #define CP2_MODE $1 |
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| 60 | #define CP2_ICACHE_FLUSH $2 |
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| 61 | #define CP2_DCACHE_FLUSH $3 |
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| 62 | #define CP2_ITLB_INVAL $4 |
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| 63 | #define CP2_DTLB_INVAL $5 |
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| 64 | #define CP2_ICACHE_INVAL $6 |
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| 65 | #define CP2_DCACHE_INVAL $7 |
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| 66 | #define CP2_ICACHE_PREFETCH $8 |
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| 67 | #define CP2_DCACHE_PREFETCH $9 |
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| 68 | #define CP2_SYNC $10 |
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| 69 | #define CP2_IETR $11 |
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| 70 | #define CP2_DETR $12 |
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| 71 | #define CP2_IBVAR $13 |
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| 72 | #define CP2_DBVAR $14 |
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| 73 | #define CP2_PARAMS $15 |
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| 74 | #define CP2_RELEASE $16 |
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| 75 | #define CP2_DATA_LO $17 |
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| 76 | #define CP2_DATA_HI $18 |
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| 77 | #define CP2_ICACHE_INVAL_PA $19 |
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| 78 | #define CP2_DCACHE_INVAL_PA $20 |
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| 79 | #define CP2_PADDR_EXT $24 |
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| 80 | |
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| [292] | 81 | #endif |
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