- Timestamp:
- Sep 14, 2015, 9:42:15 AM (9 years ago)
- Location:
- branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source
- Files:
-
- 2 edited
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branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r1001 r1015 242 242 243 243 bool distboot, 244 bool disable_procs, 244 245 245 246 const Loader &loader, // loader for XRAM … … 255 256 protected: 256 257 258 const size_t m_nb_procs; 259 const bool m_disable_procs; 260 257 261 SC_HAS_PROCESS(TsarIobCluster); 258 259 262 void init(); 260 261 262 263 }; 263 264 … … 267 268 268 269 // Local Variables: 269 // tab-width: 3270 // c-basic-offset: 3270 // tab-width: 4 271 // c-basic-offset: 4 271 272 // c-file-offsets:((innamespace . 0)(inline-open . 0)) 272 273 // indent-tabs-mode: nil 273 274 // End: 274 275 275 // vim: filetype=cpp:expandtab:shiftwidth= 3:tabstop=3:softtabstop=3276 // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 276 277 // -
branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r1001 r1015 80 80 81 81 bool distboot, 82 bool disable_procs, 82 83 83 84 const Loader &loader, … … 94 95 p_clk("clk"), 95 96 p_resetn("resetn"), 96 p_false("false") 97 p_false("false"), 98 m_nb_procs(nb_procs), 99 m_disable_procs(disable_procs) 97 100 { 98 101 … … 124 127 125 128 //////////// PROCS 126 for (size_t p = 0; p < nb_procs ; p++)129 for (size_t p = 0; p < nb_procs && !m_disable_procs; p++) 127 130 { 128 131 std::ostringstream s_proc; … … 539 542 540 543 //////////////////////////////////// Processors 541 for (size_t p = 0; p < nb_procs ; p++)544 for (size_t p = 0; p < nb_procs && !m_disable_procs; p++) 542 545 { 543 546 proc[p]->p_clk (this->p_clk); … … 692 695 tmpl(void)::init() 693 696 { 694 signal_ram_dspin_cmd_false.write = false; 695 signal_ram_dspin_rsp_false.read = true; 697 for (size_t p = 0; p < m_nb_procs && m_disable_procs; p++) 698 { 699 signal_int_vci_ini_proc[p].cmdval = false; 700 signal_int_vci_ini_proc[p].rspack = true; 701 signal_int_dspin_m2p_proc[p].read = true; 702 signal_int_dspin_p2m_proc[p].write = false; 703 signal_int_dspin_clack_proc[p].write = false; 704 } 705 706 signal_ram_dspin_cmd_false.write = false; 707 signal_ram_dspin_rsp_false.read = true; 696 708 } // end init 697 709
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