Changeset 1023 for trunk/platforms
- Timestamp:
- Oct 21, 2015, 11:48:40 AM (9 years ago)
- Location:
- trunk/platforms/tsar_generic_xbar
- Files:
-
- 1 added
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_xbar/scripts/gen_arch_info.py
r1012 r1023 1 1 #-------------------------------------------------------------------- 2 # File : gen_arch_info _large.sh2 # File : gen_arch_info.py 3 3 #-------------------------------------------------------------------- 4 4 … … 8 8 import sys 9 9 10 X_MAX = 011 Y_MAX = 012 CPU_PER_CLUSTER = 013 BSCPU = 014 BSTTY = 015 BSDMA = 016 MEMC_SIZE = 017 P_WDITH = 418 NB_TTY = 419 TTY_CHANNEL_SIZE = 0X0000001020 TTY_SIZE = 0X0000100021 OUTPUT_IRQ_PER_PROC = 422 DMA_SIZE = 0X0000100023 XCU_SIZE = 0X0000100024 BDV_SIZE = 0X0000100025 FBF_SIZE = 0X0020000026 10 27 MEMC_TGTID = 0 28 XICU_TGTID = 1 29 MDMA_TGTID = 2 30 MTTY_TGTID = 3 31 BDEV_TGTID = 4 32 MNIC_TGTID = 5 33 BROM_TGTID = 6 34 CDMA_TGTID = 7 35 SIMH_TGTID = 8 36 FBUF_TGTID = 9 11 exec(file("hard_params.py")) 12 13 def print_comments(cmd, x, y, cpu_per_cluster, bscpu): 14 print "# TSAR hardware description in BIB (Boot Information Block) format" 15 print "# This file is autogenerated by the command: " + cmd + " %d %d %d %d" % (x, y, cpu_per_cluster, bscpu) 16 print "# It is ready to be passed to info2bib utility so the binary format can be generated" 17 print " " 18 print "# " + getpass.getuser() + " on " + socket.gethostname() + " " + time.strftime("%H:%M:%S") 19 print " " 20 print " " 21 22 def print_header(x, y, bscpu, bstty, bsdma): 23 print "[HEADER]" 24 print " REVISION=1" 25 print " ARCH=SOCLIB-TSAR" 26 print " XMAX=%d" % x 27 print " YMAX=%d" % y 28 print " BSCPU=%d" % bscpu 29 print " BSTTY=0x%x" % bstty 30 print " BSDMA=0x%x" % bsdma 31 print " " 32 print " " 37 33 38 34 39 # PHYSICAL ADDRESS WIDTH 40 ADDR_WIDTH = 32 35 def print_cluster(x, y, x_width, y_width, cpu_per_cluster): 36 mem_addr = ram_addr(x, y, x_width, y_width) 37 mem_size = ram_size(x_width, y_width) 38 xcu_base = replicated_periph_base_addr(x_width, y_width, XCU_TGTID) 39 dma_base = replicated_periph_base_addr(x_width, y_width, DMA_TGTID) 40 xcu_addr = replicated_periph_addr(x, y, x_width, y_width, xcu_base) 41 dma_addr = replicated_periph_addr(x, y, x_width, y_width, dma_base) 42 print "[CLUSTER]" 41 43 42 # DEFAULT VALUES 43 DEFAULT_X_MAX = 8 44 DEFAULT_Y_MAX = 8 45 DEFAULT_CPU_PER_CLUSTER = 4 46 CLUSTER_INC = 0 44 cid = x * (1 << y_width) + y 45 cpu_num = 0; 46 while (cpu_num != cpu_per_cluster): 47 gid = (cid << P_WIDTH) + cpu_num 48 print " [CPU] ID=%d OUTIRQ=%d" % (gid, (cpu_num * OUTPUT_IRQ_PER_PROC)) 49 cpu_num += 1 50 51 print " [DEV] ID=RAM BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (mem_addr, mem_size) 52 print " [DEV] ID=XICU BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (xcu_addr, DMA_SIZE) 53 print " [DEV] ID=DMA BASE=%#.8x SIZE=%#.8x IRQ=8 IRQTYPE=HWI" % (dma_addr, XCU_SIZE) 54 print " " 55 print " " 47 56 48 def print_comments(cmd):49 print "# TSAR hardware description in BIB (Boot Information Block) format"50 print "# This file is autogenerated by the command: " + cmd + " %d %d %d %d" % (X_MAX, Y_MAX, CPU_PER_CLUSTER, BSCPU)51 print "# It is ready to be passed to info2bib utility so the binary format can be generated"52 print " "53 print "# " + getpass.getuser() + " on " + socket.gethostname() + " " + time.strftime("%H:%M:%S")54 print " "55 print " "56 57 def print_header():58 print "[HEADER]"59 print " REVISION=1"60 print " ARCH=SOCLIB-TSAR"61 print " XMAX=%d" % X_MAX62 print " YMAX=%d" % Y_MAX63 print " BSCPU=%d" % BSCPU64 print " BSTTY=0x%x" % BSTTY65 print " BSDMA=0x%x" % BSDMA66 print " "67 print " "68 57 69 def print_cluster(offset, cid): 70 mem_base = offset 71 mem_size = MEMC_SIZE 72 xcu_base = (offset + (CLUSTER_INC / 2) + (XICU_TGTID << 19)) 73 dma_base = (offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19)) 74 print "[CLUSTER]" 75 cpu_num=0; 76 while (cpu_num != CPU_PER_CLUSTER): 77 gid = (cid << CPU_PER_CLUSTER) + cpu_num 78 print " [CPU] ID=%d OUTIRQ=%d" % (gid, (cpu_num * OUTPUT_IRQ_PER_PROC)) 79 cpu_num = cpu_num + 1 80 81 print " [DEV] ID=RAM BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (mem_base, mem_size) 82 print " [DEV] ID=XICU BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (xcu_base, DMA_SIZE) 83 print " [DEV] ID=DMA BASE=%#.8x SIZE=%#.8x IRQ=8 IRQTYPE=HWI" % (dma_base, XCU_SIZE) 84 print " " 85 print " " 58 def print_io_cluster(x, y, x_width, y_width, cpu_per_cluster): 59 mem_addr = ram_addr(x, y, x_width, y_width) 60 mem_size = ram_size(x_width, y_width) 86 61 87 def print_io_cluster(offset, cid): 88 mem_base = offset 89 mem_size = MEMC_SIZE 90 xcu_base = (offset + (CLUSTER_INC / 2) + (XICU_TGTID << 19)) 91 dma_base = (offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19)) 92 bdv_base = (offset + (CLUSTER_INC / 2) + (BDEV_TGTID << 19)) 93 tty_base = (offset + (CLUSTER_INC / 2) + (MTTY_TGTID << 19)) 94 fbf_base = (offset + (CLUSTER_INC / 2) + (FBUF_TGTID << 19)) 95 96 print "[CLUSTER]" 97 cpu_num = 0 98 while (cpu_num != CPU_PER_CLUSTER): 99 gid = (cid << CPU_PER_CLUSTER) + cpu_num 100 print " [CPU] ID=%d OUTIRQ=%d" % (gid, (cpu_num * OUTPUT_IRQ_PER_PROC)) 101 cpu_num = cpu_num + 1 102 103 print " [DEV] ID=RAM BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (mem_base, mem_size) 104 print " [DEV] ID=XICU BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (xcu_base, XCU_SIZE) 105 print " [DEV] ID=DMA BASE=%#.8x SIZE=%#.8x IRQ=8 IRQTYPE=HWI" % (dma_base, DMA_SIZE) 106 print " [DEV] ID=BLKDEV BASE=%#.8x SIZE=%#.8x IRQ=31 IRQTYPE=HWI" % (bdv_base, BDV_SIZE) 107 ntty = 0 108 irq = 16 109 while (ntty < NB_TTY): 110 tty_base_i = tty_base + ntty * TTY_CHANNEL_SIZE 111 print " [DEV] ID=TTY BASE=%#.8x SIZE=%#.8x IRQ=%d IRQTYPE=HWI" % (tty_base_i, TTY_CHANNEL_SIZE, irq) 112 irq = irq + 1 113 ntty = ntty + 1 114 print " [DEV] ID=FB BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (fbf_base, FBF_SIZE) 115 print " " 116 print " " 62 xcu_addr = periph_addr(x_width, y_width, XCU_TGTID) 63 dma_addr = periph_addr(x_width, y_width, DMA_TGTID) 64 ioc_addr = periph_addr(x_width, y_width, IOC_TGTID) 65 tty_base = periph_addr(x_width, y_width, TTY_TGTID) 66 fbf_addr = periph_addr(x_width, y_width, FBF_TGTID) 67 68 print "[CLUSTER]" 69 cpu_num = 0 70 cid = x * (1 << y_width) + y 71 while (cpu_num != cpu_per_cluster): 72 gid = (cid << P_WIDTH) + cpu_num 73 print " [CPU] ID=%d OUTIRQ=%d" % (gid, (cpu_num * OUTPUT_IRQ_PER_PROC)) 74 cpu_num = cpu_num + 1 75 76 print " [DEV] ID=RAM BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (mem_addr, mem_size) 77 print " [DEV] ID=XICU BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (xcu_addr, XCU_SIZE) 78 print " [DEV] ID=DMA BASE=%#.8x SIZE=%#.8x IRQ=8 IRQTYPE=HWI" % (dma_addr, DMA_SIZE) 79 print " [DEV] ID=BLKDEV BASE=%#.8x SIZE=%#.8x IRQ=31 IRQTYPE=HWI" % (ioc_addr, IOC_SIZE) 80 ntty = 0 81 irq = 16 82 while (ntty < NB_TTY_CHANNELS): 83 tty_base_i = tty_base + ntty * TTY_CHANNEL_SIZE 84 print " [DEV] ID=TTY BASE=%#.8x SIZE=%#.8x IRQ=%d IRQTYPE=HWI" % (tty_base_i, TTY_CHANNEL_SIZE, irq) 85 irq += 1 86 ntty += 1 87 print " [DEV] ID=FB BASE=%#.8x SIZE=%#.8x IRQ=-1 IRQTYPE=NONE" % (fbf_addr, FBF_SIZE) 88 print " " 89 print " " 117 90 118 def gen_arch_info(x, y, x_width, y_width, bscpu, arch_info_name): 119 fp = open(arch_info_name, 'w') 120 stdout = sys.stdout 121 sys.stdout = fp 122 global X_MAX 123 global Y_MAX 124 global CPU_PER_CLUSTER 125 global CLUSTER_INC 126 global MEMC_SIZE 127 global BSCPU 128 global BSDMA 129 global BSTTY 130 131 #------------------------ 132 133 X_MAX = x 134 Y_MAX = y 135 cpu_per_cluster = DEFAULT_CPU_PER_CLUSTER 136 CPU_PER_CLUSTER = cpu_per_cluster 137 138 #------------------------ 139 CLUSTER_INC = (0x80000000 >> (x_width + y_width)) * 2 140 max_memc_size = 0x40000000 / (X_MAX * Y_MAX) 141 size = min(max_memc_size, 0x10000000) 142 MEMC_SIZE = size 91 def gen_arch_info(x, y, x_width, y_width, cpu_per_cluster, bscpu, arch_info_name): 92 fp = open(arch_info_name, 'w') 93 stdout = sys.stdout 94 sys.stdout = fp 143 95 144 ########################################################################################## 145 #we force io_cid to 0 because this is the only cluster we know which will be present 146 #in all platform where the number of clusters is independant of x_width and y_width values 147 io_cid = 0 148 ########################################################################################## 96 x_io = get_x_io(x_width, y_width) 97 y_io = get_y_io(x_width, y_width) 149 98 150 BSCPU = bscpu 151 152 break_loop = 0 153 xi = 0 99 ########################################################################################### 100 # we force io_cid to 0 because this is the only cluster we know which will be present 101 # in all platform where the number of clusters is independant of x_width and y_width values 102 # io_cid = 0 103 # @QM No. 104 ########################################################################################### 105 106 break_loop = 0 107 xi = 0 108 yi = 0 109 while (xi < x): 110 while (yi < y): 111 if xi == x_io and yi == y_io: 112 bsdma = periph_addr(x_width, y_width, DMA_TGTID) 113 bstty = periph_addr(x_width, y_width, TTY_TGTID) 114 break_loop = 1 115 break 116 else: 117 bsdma = "error" 118 yi = yi + 1 119 120 if break_loop == 1: 121 break 154 122 yi = 0 155 while (xi < X_MAX): 156 while (yi < Y_MAX): 157 cid = xi * (1 << y_width) + yi 158 offset = cid << (ADDR_WIDTH - x_width - y_width) 159 if cid == io_cid: 160 BSDMA = offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19) 161 BSTTY = offset + (CLUSTER_INC / 2) + (MTTY_TGTID << 19) 162 break_loop = 1 163 break 164 else: 165 bsdma="error" 166 yi = yi + 1 123 xi = xi + 1 124 125 # Generate the description 126 print_comments(sys.argv[0], x, y, cpu_per_cluster, bscpu) 127 print_header(x, y, bscpu, bstty, bsdma) 128 129 xi = 0 130 yi = 0 131 while (xi < x): 132 while (yi < y): 133 if xi == x_io and yi == y_io: 134 print_io_cluster(xi, yi, x_width, y_width, cpu_per_cluster) 135 else: 136 print_cluster(xi, yi, x_width, y_width, cpu_per_cluster) 137 yi = yi + 1 138 yi = 0 139 xi = xi + 1 140 sys.stdout = stdout 141 fp.close() 167 142 168 if break_loop == 1:169 break170 yi = 0171 xi = xi + 1172 173 # Generate the description174 print_comments(sys.argv[0])175 print_header()176 177 xi = 0178 yi = 0179 while (xi < X_MAX):180 while (yi < Y_MAX):181 cid = xi * (1 << y_width) + yi182 offset = cid << (ADDR_WIDTH - (x_width + y_width))183 if cid == io_cid:184 print_io_cluster(offset, cid)185 else:186 print_cluster(offset, cid)187 yi = yi + 1188 yi = 0189 xi = xi + 1190 sys.stdout = stdout191 fp.close()192 -
trunk/platforms/tsar_generic_xbar/scripts/gen_hard_config.py
r1012 r1023 1 1 2 3 exec(file("hard_params.py")) 2 4 3 5 4 6 def hard_config(x, y, x_width, y_width, p, hard_config, protocol): 7 8 x_io = get_x_io(x_width, y_width) 9 y_io = get_y_io(x_width, y_width) 5 10 6 ram_tgtid = 0 7 xcu_tgtid = 1 8 dma_tgtid = 2 9 tty_tgtid = 3 10 ioc_tgtid = 4 11 nic_tgtid = 5 12 rom_tgtid = 6 13 cma_tgtid = 7 14 sim_tgtid = 8 15 fbf_tgtid = 9 16 17 nb_dma_channels = 1 18 nb_cma_channels = 0 19 nb_tty_channels = 4 20 nb_ioc_channels = 1 21 22 fbf_x_size = 1024 23 fbf_y_size = 1024 24 25 seg_rom_base = 0xbfc00000 26 seg_rom_size = 0x00100000 27 28 cluster_inc = 0x80000000 / (x * y) * 2 29 cluster_io_id = seg_rom_base >> (32 - x_width - y_width) 30 cluster_io_inc = cluster_io_id * cluster_inc 31 ram_max_size = 0x40000000 / (x * y) # 1 Go Max 32 33 seg_ram_base = 0x00000000 34 seg_ram_size = min(0x10000000, ram_max_size) 35 36 seg_xcu_base = (cluster_inc >> 1) + (xcu_tgtid << 19) 37 seg_xcu_size = 0x00001000 # 4Ko 38 39 seg_dma_base = (cluster_inc >> 1) + (dma_tgtid << 19) 40 seg_dma_size = 0x00001000 * nb_dma_channels 41 42 def periph_address(tgtid): 43 return (cluster_inc >> 1) + cluster_io_inc + (tgtid << 19) 44 45 seg_ioc_base = periph_address(ioc_tgtid); 46 seg_ioc_size = 0x00001000 47 48 seg_tty_base = periph_address(tty_tgtid) 49 seg_tty_size = 0x00001000 50 51 seg_fbf_base = periph_address(fbf_tgtid) 52 seg_fbf_size = fbf_x_size * fbf_y_size * 2 53 54 seg_nic_base = periph_address(nic_tgtid) 55 seg_nic_size = 0x00080000 56 57 seg_cma_base = periph_address(cma_tgtid) 58 seg_cma_size = 0x00004000 * nb_cma_channels 59 60 seg_sim_base = periph_address(sim_tgtid) 61 seg_sim_size = 0x00001000 11 seg_rom_base = BOOT_ADDR 12 seg_rom_size = ROM_SIZE 13 14 seg_ram_base = RAM_BASE 15 seg_ram_size = ram_size(x_width, y_width) 16 17 seg_xcu_base = replicated_periph_base_addr(x_width, y_width, XCU_TGTID) 18 seg_xcu_size = XCU_SIZE 19 20 seg_dma_base = replicated_periph_base_addr(x_width, y_width, DMA_TGTID) 21 seg_dma_size = DMA_SIZE * NB_DMA_CHANNELS 22 23 seg_ioc_base = periph_addr(x_width, y_width, IOC_TGTID); 24 seg_ioc_size = IOC_SIZE 25 26 seg_tty_base = periph_addr(x_width, y_width, TTY_TGTID) 27 seg_tty_size = TTY_SIZE 28 29 seg_fbf_base = periph_addr(x_width, y_width, FBF_TGTID) 30 seg_fbf_size = FBF_X_SIZE * FBF_Y_SIZE * 2 31 32 seg_nic_base = periph_addr(x_width, y_width, NIC_TGTID) 33 seg_nic_size = NIC_SIZE 34 35 seg_cma_base = periph_addr(x_width, y_width, CMA_TGTID) 36 seg_cma_size = CMA_SIZE * NB_CMA_CHANNELS 37 38 seg_sim_base = periph_addr(x_width, y_width, SIM_TGTID) 39 seg_sim_size = SIM_SIZE 62 40 63 41 header = ''' … … 65 43 #define _HARD_CONFIG_H_ 66 44 67 /* Generated from run_simus.py */45 /* Generated from gen_hard_config.py */ 68 46 69 47 /* General platform parameters */ … … 74 52 #define Y_WIDTH %(y_width)d 75 53 #define P_WIDTH 4 76 #define X_IO 077 #define Y_IO 054 #define X_IO %(x_io)d 55 #define Y_IO %(y_io)d 78 56 #define NB_PROCS_MAX %(proc_per_clus)d 79 57 #define IRQ_PER_PROCESSOR 4 … … 169 147 170 148 ''' % dict(x_size = x, y_size = y, x_width = x_width, y_width = y_width, 149 x_io = x_io, 150 y_io = y_io, 171 151 proc_per_clus = p, 172 nb_tty_channels = nb_tty_channels,173 nb_ioc_channels = nb_ioc_channels,174 nb_cma_channels = nb_cma_channels,175 nb_dma_channels = nb_dma_channels,176 fbf_x_size = fbf_x_size, fbf_y_size = fbf_y_size,177 ram_tgtid = ram_tgtid,178 xcu_tgtid = xcu_tgtid,179 dma_tgtid = dma_tgtid,180 tty_tgtid = tty_tgtid,181 ioc_tgtid = ioc_tgtid,182 nic_tgtid = nic_tgtid,183 rom_tgtid = rom_tgtid,184 cma_tgtid = cma_tgtid,185 sim_tgtid = sim_tgtid,186 fbf_tgtid = fbf_tgtid,152 nb_tty_channels = NB_TTY_CHANNELS, 153 nb_ioc_channels = NB_IOC_CHANNELS, 154 nb_cma_channels = NB_CMA_CHANNELS, 155 nb_dma_channels = NB_DMA_CHANNELS, 156 fbf_x_size = FBF_X_SIZE, fbf_y_size = FBF_Y_SIZE, 157 ram_tgtid = RAM_TGTID, 158 xcu_tgtid = XCU_TGTID, 159 dma_tgtid = DMA_TGTID, 160 tty_tgtid = TTY_TGTID, 161 ioc_tgtid = IOC_TGTID, 162 nic_tgtid = NIC_TGTID, 163 rom_tgtid = ROM_TGTID, 164 cma_tgtid = CMA_TGTID, 165 sim_tgtid = SIM_TGTID, 166 fbf_tgtid = FBF_TGTID, 187 167 seg_ram_base = seg_ram_base, 188 168 seg_ram_size = seg_ram_size, -
trunk/platforms/tsar_generic_xbar/scripts/gen_hdd.py
r1012 r1023 9 9 10 10 def hdd_img(partition_root, target, fs_type, bootloader_name): 11 print("### Creating HDD_IMG") 11 12 12 13 # echo "Dont forget to check the numbers of sectors for each file" … … 28 29 sys.exit() 29 30 31 # Remove current disk image if it exists, otherwise the creation fails 32 if (os.path.isfile(target)): 33 print "rm", target 34 os.remove(target) 30 35 31 36 size_bytes = 512000 … … 43 48 back_up_sector = reserved_sectors - 1 # last reserved sector 44 49 45 print("******** HDD_IMG *********") 46 print("%d reserved sectors --> backup at back up sector %d" % (reserved_sectors, back_up_sector)) 50 print "# %d reserved sectors --> backup at back up sector %d" % (reserved_sectors, back_up_sector) 47 51 # the first two cluster are not in the data region 48 52 # data_region_clusters=$cluster_size-2 … … 73 77 74 78 # copy bootloader, arch-info (boot-info) and kernel-img in reserved sectors from sector 2 75 print ("Insert boot_loader at sector $offset")79 print "# Inserting boot_loader at sector %d" % (offset) 76 80 77 81 cmd = ['dd', 'bs=%d' % sector_size, 'seek=%d' % offset, 'count=%d' % sectors_boot, 'conv=notrunc', 'if=%s' % bootloader_name, 'of=%s' % target] … … 79 83 subprocess.call(cmd) 80 84 85 print "### End of HDD image generation" 86 81 87 82 88 if __name__ == '__main__': 83 89 84 90 if len(sys.argv) != 5: 85 print ("Usage: %s path/to/partition/root <hdd-filename> <fs_type> <bootloader-filename>" % sys.argv[0])91 print "Usage: %s path/to/partition/root <hdd-filename> <fs_type> <bootloader-filename>" % sys.argv[0] 86 92 sys.exit() 87 93 -
trunk/platforms/tsar_generic_xbar/scripts/run_simus.py
r1012 r1023 15 15 16 16 # User parameters 17 bscpu = 0 18 #nb_procs = [ 4 ]19 nb_procs = [ 1, 4, 8, 16, 32, 64, 128, 256 ]20 rerun_stats = True21 use_omp = True17 bscpu = 0 # bootstrap CPU 18 nb_procs = [ 4 ] 19 #nb_procs = [ 1, 4, 8, 16, 32, 64, 128, 256 ] 20 rerun_stats = False 21 use_omp = False 22 22 protocol = 'rwt' 23 23 cpu_per_cluster = 4 24 24 # mode must be one of 'test' and 'simu' 25 mode = ' simu'25 mode = 'test' 26 26 27 27 #apps = [ 'cholesky', 'fft', 'fft_ga', 'filter', 'filt_ga', 'histogram', 'kmeans', 'lu', 'mandel', 'mat_mult', 'pca', 'radix_ga' ] 28 28 #apps = [ 'histogram', 'mandel', 'filter', 'radix_ga', 'fft_ga', 'kmeans' ] 29 apps = [ 'blackscholes', 'linear_regression', 'string_match', 'swaptions', 'fluidanimate' ] 29 #apps = [ 'blackscholes', 'linear_regression', 'string_match', 'swaptions', 'fluidanimate' ] 30 apps = [ 'hello', 'taquin', '2048' ] 30 31 31 32 … … 40 41 # Global Variables 41 42 42 all_apps = [ ' blackscholes', 'boot_only', 'cholesky', 'fft', 'fft_ga', 'filter', 'filt_ga', 'fluidanimate', 'histogram', 'histo-opt', 'kmeans', 'kmeans-opt', 'linear_regression', 'lu', 'mandel', 'mat_mult', 'mat_mult-opt', 'pca', 'pca-opt', 'radix', 'radix_ga', 'showimg', 'string_match', 'swaptions',]43 all_apps = [ '2048', 'blackscholes', 'boot_only', 'cholesky', 'fft', 'fft_ga', 'filter', 'filt_ga', 'fluidanimate', 'hello', 'histogram', 'histo-opt', 'kmeans', 'kmeans-opt', 'linear_regression', 'lu', 'mandel', 'mat_mult', 'mat_mult-opt', 'pca', 'pca-opt', 'radix', 'radix_ga', 'showimg', 'string_match', 'swaptions', 'taquin'] 43 44 # to come: 'barnes', 'fmm', 'ocean', 'raytrace', 'radiosity', 'waters', 'watern' 44 45 45 46 all_protocols = [ 'dhccp', 'rwt', 'hmesi', 'wtidl', 'snoop' ] 46 47 47 top_path = os.path. join(os.path.dirname(os.path.realpath(__file__)), "..")48 top_path = os.path.abspath(os.path.join(os.path.dirname(os.path.realpath(__file__)), "..")) 48 49 config_name = os.path.join(os.path.dirname(os.path.realpath(__file__)), "config.py") 49 50 50 scripts_path = os.path.join(top_path, 'scripts') 51 almos_path = os.path.join(top_path, 'almos') 52 soclib_conf_name = os.path.join(top_path, "soclib.conf") 53 topcell_name = os.path.join(top_path, "top.cpp") 54 partition_root_path = os.path.join(top_path, "hdd_root") 55 arch_info_name = os.path.join(almos_path, "arch-info-gen.info") 56 arch_info_bib_name = os.path.join(almos_path, 'arch-info.bib') 57 hdd_img_file_name = os.path.join(almos_path, "hdd-img.bin") 58 shrc_file_name = os.path.join(almos_path, "shrc") 59 hard_config_name = os.path.join(almos_path, "hard_config.h") 60 bootloader_link_name = os.path.join(almos_path, "bootloader-tsar-mipsel.bin") 51 scripts_path = os.path.join(top_path, 'scripts') 52 almos_path = os.path.join(top_path, 'almos') 53 soclib_conf_name = os.path.join(top_path, "soclib.conf") 54 topcell_name = os.path.join(top_path, "top.cpp") 55 partition_root_path = os.path.join(top_path, "hdd_root") 56 arch_info_name = os.path.join(almos_path, "arch-info.info") 57 arch_info_bib_name = os.path.join(almos_path, 'arch-info.bib') 58 hdd_img_file_name = os.path.join(almos_path, "hdd-img.bin") 59 shrc_file_name = os.path.join(almos_path, "shrc") 60 hard_config_name = os.path.join(almos_path, "hard_config.h") 61 bootloader_file_name = os.path.join(almos_path, "bootloader-tsar-mipsel.bin") 62 preloader_file_name = os.path.join(almos_path, "preloader.elf") 63 preloader_build_path = os.path.join(almos_path, "build_preloader") 64 bootloader_build_path = os.path.join(almos_path, "build_bootloader") 61 65 62 66 … … 87 91 - almos_src_dir: path to almos source directory (for kernel and bootloader binaries) 88 92 - preloader_src_dir: path to the preloader main directory (where to run make) 89 - hdd_img_name: path to the hdd image to use (will be copied but not modified)90 93 - tsar_dir: path to tsar repository 91 94 Optional definitions (necessary if you want to use alternative protocols): … … 102 105 103 106 # Check that variables and paths exist 104 for var in [ 'apps_dir', 'almos_src_dir', ' hdd_img_name', 'tsar_dir' ]:107 for var in [ 'apps_dir', 'almos_src_dir', 'tsar_dir' ]: 105 108 if eval(var) == "": 106 109 print "*** Error: variable %s not defined in config file" % (var) … … 183 186 def gen_soclib_conf(): 184 187 if os.path.isfile(soclib_conf_name): 185 print " Updating file %s" % (soclib_conf_name)188 print "# Updating file %s" % (soclib_conf_name) 186 189 # First, remove lines containing "addDescPath" 187 190 f = open(soclib_conf_name, "r") … … 196 199 f.close() 197 200 else: 198 print " Creating file %s" % (soclib_conf_name)201 print "# Creating file %s" % (soclib_conf_name) 199 202 f = open(soclib_conf_name, "w") 200 203 f.close() … … 245 248 246 249 247 def gen_arch_info_bib(x, y, arch_info, arch_info_bib): 250 def gen_arch_info_bib(x, y, x_width, y_width): 251 print "### Generating arch-info files" 248 252 old_path = os.getcwd() 249 253 250 254 print "cd", scripts_path 251 255 os.chdir(scripts_path) 252 gen_arch_info(x, y, x_width, y_width, bscpu, arch_info)256 gen_arch_info(x, y, x_width, y_width, cpu_per_cluster, bscpu, arch_info_name) 253 257 os.chdir(almos_path) 254 258 255 cmd = ['./info2bib', '-i', arch_info , '-o', arch_info_bib]259 cmd = ['./info2bib', '-i', arch_info_name, '-o', arch_info_bib_name] 256 260 print_and_call(cmd) 257 261 258 262 print "cd", old_path 259 263 os.chdir(old_path) 264 265 print "### End of arch-info files generation" 260 266 261 267 262 def gen_sym_links(): 263 target = os.path.join(almos_src_dir, 'tools/soclib-bootloader/bootloader-tsar-mipsel.bin') 264 if not os.path.isfile(bootloader_link_name): 265 print "ln -s", target, bootloader_link_name 266 os.symlink(target, bootloader_link_name) 267 268 #target = os.path.join(almos_src_dir, 'kernel/obj.tsar/almix-tsar-mipsel.bin') 269 #link_name = 'kernel-soclib.bin' 270 #if not os.path.isfile(link_name): 271 # print "ln -s", target, link_name 272 # os.symlink(target, link_name) 268 #def gen_sym_links(): 269 # print "### Generating symbolic links" 270 # target = os.path.join(almos_src_dir, 'tools/soclib-bootloader/bootloader-tsar-mipsel.bin') 271 # if not os.path.isfile(bootloader_link_name): 272 # print "ln -s", target, bootloader_link_name 273 # os.symlink(target, bootloader_link_name) 274 # 275 # print "### End of symbolic links generation" 276 # #target = os.path.join(almos_src_dir, 'kernel/obj.tsar/almix-tsar-mipsel.bin') 277 # #link_name = 'kernel-soclib.bin' 278 # #if not os.path.isfile(link_name): 279 # # print "ln -s", target, link_name 280 # # os.symlink(target, link_name) 273 281 274 282 275 283 def compile_almos(): 284 print "### Compiling Almos" 276 285 old_path = os.getcwd() 277 286 … … 279 288 os.chdir(almos_src_dir) 280 289 cmd = ['make'] 281 print_and_call(cmd) 290 retval = print_and_call(cmd) 291 if retval != 0: 292 sys.exit() 293 294 print "cd", old_path 295 os.chdir(old_path) 296 297 print "### End of Almos compilation" 298 299 300 def compile_bootloader(): 301 # This function depends upon the file arch-info.bib and should be called 302 # every time it is modified 303 print "### Compiling Almos bootloader" 304 old_path = os.getcwd() 305 282 306 bootloader_dir = os.path.join(almos_src_dir, 'tools/soclib-bootloader') 283 307 print "cd", bootloader_dir 284 308 os.chdir(bootloader_dir) 285 print_and_call(cmd) 309 cmd = ['make', 'ARCH_BIB=%s' % (arch_info_bib_name), 'BUILD_DIR=%s' % (bootloader_build_path), 'TARGET_DIR=%s' % (almos_path)] 310 retval = print_and_call(cmd) 311 if retval != 0: 312 sys.exit() 286 313 287 314 print "cd", old_path 288 315 os.chdir(old_path) 289 316 317 print "### End of Almos bootloader compilation" 318 319 290 320 291 321 def compile_preloader(): 322 # This function depends upon the file hard_config.h, and should be called 323 # every time it is modified 324 print "### Compiling preloader" 292 325 old_path = os.getcwd() 326 293 327 hard_conf_path_set = "HARD_CONFIG_PATH=" + almos_path 294 328 bscpu_set = "BS_PROC=%d" % bscpu … … 296 330 print "cd", preloader_src_dir 297 331 os.chdir(preloader_src_dir) 298 cmd = ['make', hard_conf_path_set, bscpu_set, 'USE_DT=0'] 299 print_and_call(cmd) 332 cmd = ['make', hard_conf_path_set, bscpu_set, 'USE_DT=0', 'BUILD_DIR=%s' % (preloader_build_path)] 333 retval = print_and_call(cmd) 334 if retval != 0: 335 sys.exit() 300 336 301 337 print "cd", old_path 302 338 os.chdir(old_path) 303 339 340 print "### End of preloader compilation" 341 304 342 305 343 306 344 307 345 def compile_app(app_name): 346 print "### Compiling application %s" % (app_name) 308 347 309 348 #if app_name in splash2: … … 352 391 print "cd", old_path 353 392 os.chdir(old_path) 393 394 print "### End of compilation for application %s" % (app_name) 354 395 # end of compile_app 355 396 … … 358 399 359 400 def gen_shrc(app_name, nprocs): 360 # Creation/Modification du shrc de almos 401 # Creation/Modification of almos shrc file 402 print "### Generating shrc for application %s and %d threads" % (app_name, nprocs) 361 403 if mode == 'test': 362 404 if (app_name == "blackscholes"): … … 374 416 elif (app_name == "fluidanimate"): 375 417 shrc = "exec -p 0 /bin/fluidani -n%(nproc)d -i /etc/flui_15K.flu\n" % dict(nproc = nprocs) 418 elif (app_name == "hello"): 419 shrc = "exec -p 0 /bin/hello -n%(nproc)d\n" % dict(nproc = nprocs) 376 420 elif (app_name == "histogram"): 377 421 shrc = "exec -p 0 /bin/histogra -n%(nproc)d /etc/histo_s.bmp\n" % dict(nproc = nprocs) … … 480 524 cmd = ['cp', shrc_file_name, os.path.join(partition_root_path, "etc", "shrc")] 481 525 print_and_call(cmd) 526 527 print "### End of shrc generation for application %s and %d threads" % (app_name, nprocs) 482 528 # end of gen_shrc 483 529 … … 487 533 print_and_call(cmd) 488 534 489 gen_sym_links()535 #gen_sym_links() 490 536 gen_soclib_conf() 491 compile_preloader()492 537 compile_almos() 493 538 # Compile application once at the beginning not to intererfere with … … 507 552 x_width = get_nb_bits(x) 508 553 y_width = get_nb_bits(y) 509 nthreads = min(4, x * y) 554 nthreads = min(4, x * y) # thread number for parallel systemcass 510 555 hard_config(x, y, x_width, y_width, cpu_per_cluster, hard_config_name, protocol) 511 gen_arch_info_bib(x, y, arch_info_name, arch_info_bib_name) 556 gen_arch_info_bib(x, y, x_width, y_width) 557 # We must recompile the preloader because we modified the hard_config file 558 # and the bootloader because we modified the arch-info.bib file 559 compile_preloader() 560 compile_bootloader() 512 561 513 562 cmd = ['touch', topcell_name] … … 523 572 gen_shrc(app, i) 524 573 525 # Remove current disk image526 print "rm", hdd_img_file_name527 os.remove(hdd_img_file_name)528 529 574 # Regenerate disk image 530 hdd_img(partition_root_path, hdd_img_file_name, "fat32", bootloader_ link_name)575 hdd_img(partition_root_path, hdd_img_file_name, "fat32", bootloader_file_name) 531 576 532 577 # Launch simulation … … 560 605 assert(start2_found and end_found) 561 606 562 # Regenerate shrc andhdd to ensure having the same hdd image563 gen_shrc(app, i)607 # Regenerate hdd to ensure having the same hdd image 608 hdd_img(partition_root_path, hdd_img_file_name, "fat32", bootloader_file_name) 564 609 565 610 # Relauching simulation with reset and dump of counters … … 581 626 file.write(output) 582 627 file.close() 583 584 628 585 629 ## End of simulations -
trunk/platforms/tsar_generic_xbar/top.cpp
r1012 r1023 271 271 int64_t debug_from = 0; // trace start cycle 272 272 int64_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 273 size_t cluster_io_id; // index of cluster containing IOs274 273 int64_t reset_counters = -1; 275 274 int64_t dump_counters = -1; … … 280 279 281 280 ////////////// command line arguments ////////////////////// 282 if (argc > 1) 283 { 284 for (int n = 1; n < argc; n = n + 2) 285 { 286 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) 287 { 281 if (argc > 1) { 282 for (int n = 1; n < argc; n = n + 2) { 283 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) { 288 284 ncycles = (int64_t) strtol(argv[n + 1], NULL, 0); 289 285 } 290 else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) 291 { 286 else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) { 292 287 #ifdef USE_ALMOS 293 288 assert( 0 && "Can't define almos soft name" ); … … 297 292 #endif 298 293 } 299 else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc)) 300 { 294 else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc)) { 301 295 strcpy(disk_name, argv[n + 1]); 302 296 } 303 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) 304 { 297 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) { 305 298 debug_ok = true; 306 299 debug_from = (int64_t) strtol(argv[n + 1], NULL, 0); 307 300 } 308 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) 309 { 301 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) { 310 302 debug_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); 311 303 #ifdef USE_ALMOS … … 320 312 #endif 321 313 } 322 else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc)) 323 { 314 else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc)) { 324 315 debug_proc_id = (size_t) strtol(argv[n + 1], NULL, 0); 325 316 #ifdef USE_ALMOS … … 335 326 #endif 336 327 } 337 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) 338 { 328 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) { 339 329 threads_nr = (ssize_t) strtol(argv[n + 1], NULL, 0); 340 330 threads_nr = (threads_nr < 1) ? 1 : threads_nr; 341 331 } 342 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) 343 { 332 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) { 344 333 frozen_cycles = (int64_t) strtol(argv[n + 1], NULL, 0); 345 334 } 346 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc)) 347 { 335 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc)) { 348 336 debug_period = (size_t) strtol(argv[n + 1], NULL, 0); 349 337 } 350 else if ((strcmp(argv[n], "--reset-counters") == 0) && (n + 1 < argc)) 351 { 338 else if ((strcmp(argv[n], "--reset-counters") == 0) && (n + 1 < argc)) { 352 339 reset_counters = (int64_t) strtol(argv[n + 1], NULL, 0); 353 340 do_reset_counters = true; 354 341 } 355 else if ((strcmp(argv[n], "--dump-counters") == 0) && (n + 1 < argc)) 356 { 342 else if ((strcmp(argv[n], "--dump-counters") == 0) && (n + 1 < argc)) { 357 343 dump_counters = (int64_t) strtol(argv[n + 1], NULL, 0); 358 344 do_dump_counters = true; 359 345 } 360 else 361 { 346 else { 362 347 std::cout << " Arguments are (key,value) couples." << std::endl; 363 348 std::cout << " The order is not important." << std::endl; … … 461 446 else if (X_SIZE <= 4) x_width = 2; 462 447 else if (X_SIZE <= 8) x_width = 3; 463 else x_width = 4;448 else x_width = 4; 464 449 465 450 if (Y_SIZE == 1) y_width = 0; … … 467 452 else if (Y_SIZE <= 4) y_width = 2; 468 453 else if (Y_SIZE <= 8) y_width = 3; 469 else y_width = 4;454 else y_width = 4; 470 455 471 456 #else … … 480 465 481 466 #endif 482 483 // index of cluster containing IOs484 cluster_io_id = 0x00bfc00000ULL >> (vci_address_width - x_width - y_width);485 486 467 487 468 ///////////////////// … … 495 476 0x00FF800000); 496 477 497 for (size_t x = 0; x < X_SIZE; x++) 498 { 499 for (size_t y = 0; y < Y_SIZE; y++) 500 { 478 for (size_t x = 0; x < X_SIZE; x++) { 479 for (size_t y = 0; y < Y_SIZE; y++) { 501 480 sc_uint<vci_address_width> offset; 502 481 offset = (sc_uint<vci_address_width>) cluster(x,y) … … 518 497 IntTab(cluster(x,y), RAM_TGTID), true)); 519 498 520 if ( cluster(x,y) == cluster_io_id ) 521 { 499 if (x == X_IO && y == Y_IO) { 522 500 maptabd.add(Segment("seg_mtty", SEG_TTY_BASE, SEG_TTY_SIZE, 523 501 IntTab(cluster(x,y),TTY_TGTID), false)); … … 545 523 0xFFFF000000ULL); 546 524 547 for (size_t x = 0; x < X_SIZE; x++) 548 { 549 for (size_t y = 0; y < Y_SIZE ; y++) 550 { 525 for (size_t x = 0; x < X_SIZE; x++) { 526 for (size_t y = 0; y < Y_SIZE ; y++) { 551 527 552 528 sc_uint<vci_address_width> offset; … … 672 648 #pragma omp for 673 649 #endif 674 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) 675 { 650 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) { 676 651 size_t x = i / Y_SIZE; 677 652 size_t y = i % Y_SIZE; … … 704 679 y_width, 705 680 vci_srcid_width - x_width - y_width, // l_id width, 681 P_WIDTH, 706 682 RAM_TGTID, 707 683 XCU_TGTID, … … 722 698 IRQ_PER_PROCESSOR, 723 699 XRAM_LATENCY, 724 (cluster(x,y) == cluster_io_id),700 x == X_IO && y == Y_IO, 725 701 FBF_X_SIZE, 726 702 FBF_Y_SIZE, … … 752 728 753 729 // Clock & RESET 754 for ( size_t x = 0; x < (X_SIZE); x++){755 for ( size_t y = 0; y < Y_SIZE; y++){756 clusters[x][y]->p_clk 757 clusters[x][y]->p_resetn 730 for (int x = 0; x < X_SIZE; x++) { 731 for (int y = 0; y < Y_SIZE; y++) { 732 clusters[x][y]->p_clk (signal_clk); 733 clusters[x][y]->p_resetn (signal_resetn); 758 734 } 759 735 } 760 736 761 737 // Inter Clusters horizontal connections 762 if (X_SIZE > 1) { 763 for (size_t x = 0; x < (X_SIZE-1); x++) { 764 for (size_t y = 0; y < (Y_SIZE); y++) { 765 clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]); 766 clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]); 767 clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]); 768 clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]); 769 770 clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]); 771 clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]); 772 clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]); 773 clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]); 774 775 clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]); 776 clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]); 777 clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]); 778 clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]); 779 780 clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]); 781 clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]); 782 clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]); 783 clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]); 784 785 clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]); 786 clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]); 787 clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]); 788 clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]); 789 } 790 } 738 for (int x = 0; x < X_SIZE - 1; x++) { 739 for (int y = 0; y < Y_SIZE; y++) { 740 clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]); 741 clusters[x + 1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]); 742 clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]); 743 clusters[x + 1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]); 744 745 clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]); 746 clusters[x + 1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]); 747 clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]); 748 clusters[x + 1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]); 749 750 clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]); 751 clusters[x + 1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]); 752 clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]); 753 clusters[x + 1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]); 754 755 clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]); 756 clusters[x + 1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]); 757 clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]); 758 clusters[x + 1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]); 759 760 clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]); 761 clusters[x + 1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]); 762 clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]); 763 clusters[x + 1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]); 764 } 791 765 } 792 766 std::cout << std::endl << "Horizontal connections done" << std::endl; 793 767 794 768 // Inter Clusters vertical connections 795 if (Y_SIZE > 1) { 796 for (size_t y = 0; y < (Y_SIZE-1); y++) { 797 for (size_t x = 0; x < X_SIZE; x++) { 798 clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]); 799 clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]); 800 clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]); 801 clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]); 802 803 clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]); 804 clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]); 805 clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]); 806 clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]); 807 808 clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]); 809 clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]); 810 clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]); 811 clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]); 812 813 clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]); 814 clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]); 815 clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]); 816 clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]); 817 818 clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]); 819 clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]); 820 clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]); 821 clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]); 822 } 823 } 769 for (int y = 0; y < Y_SIZE - 1; y++) { 770 for (int x = 0; x < X_SIZE; x++) { 771 clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]); 772 clusters[x][y + 1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]); 773 clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]); 774 clusters[x][y + 1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]); 775 776 clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]); 777 clusters[x][y + 1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]); 778 clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]); 779 clusters[x][y + 1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]); 780 781 clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]); 782 clusters[x][y + 1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]); 783 clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]); 784 clusters[x][y + 1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]); 785 786 clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]); 787 clusters[x][y + 1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]); 788 clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]); 789 clusters[x][y + 1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]); 790 791 clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]); 792 clusters[x][y + 1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]); 793 clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]); 794 clusters[x][y + 1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]); 795 } 824 796 } 825 797 std::cout << std::endl << "Vertical connections done" << std::endl; 826 798 827 799 // East & West boundary cluster connections 828 for (size_t y = 0; y < (Y_SIZE); y++) {800 for (size_t y = 0; y < Y_SIZE; y++) { 829 801 clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]); 830 802 clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]); 831 clusters[X_SIZE -1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]);832 clusters[X_SIZE -1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]);803 clusters[X_SIZE - 1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE - 1][y][EAST]); 804 clusters[X_SIZE - 1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE - 1][y][EAST]); 833 805 834 806 clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]); 835 807 clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]); 836 clusters[X_SIZE -1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]);837 clusters[X_SIZE -1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]);808 clusters[X_SIZE - 1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE - 1][y][EAST]); 809 clusters[X_SIZE - 1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE - 1][y][EAST]); 838 810 839 811 clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]); 840 812 clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]); 841 clusters[X_SIZE -1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]);842 clusters[X_SIZE -1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]);813 clusters[X_SIZE - 1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE - 1][y][EAST]); 814 clusters[X_SIZE - 1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE - 1][y][EAST]); 843 815 844 816 clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]); 845 817 clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]); 846 clusters[X_SIZE -1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]);847 clusters[X_SIZE -1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]);818 clusters[X_SIZE - 1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE - 1][y][EAST]); 819 clusters[X_SIZE - 1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE - 1][y][EAST]); 848 820 849 821 clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]); 850 822 clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]); 851 clusters[X_SIZE -1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]);852 clusters[X_SIZE -1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]);823 clusters[X_SIZE - 1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE - 1][y][EAST]); 824 clusters[X_SIZE - 1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE - 1][y][EAST]); 853 825 } 854 826 … … 859 831 clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]); 860 832 clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]); 861 clusters[x][Y_SIZE -1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);862 clusters[x][Y_SIZE -1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);833 clusters[x][Y_SIZE - 1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE - 1][NORTH]); 834 clusters[x][Y_SIZE - 1]->p_cmd_out[NORTH](signal_dspin_bound_cmd_out[x][Y_SIZE - 1][NORTH]); 863 835 864 836 clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]); 865 837 clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]); 866 clusters[x][Y_SIZE -1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);867 clusters[x][Y_SIZE -1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);838 clusters[x][Y_SIZE - 1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE - 1][NORTH]); 839 clusters[x][Y_SIZE - 1]->p_rsp_out[NORTH](signal_dspin_bound_rsp_out[x][Y_SIZE - 1][NORTH]); 868 840 869 841 clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]); 870 842 clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]); 871 clusters[x][Y_SIZE -1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);872 clusters[x][Y_SIZE -1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);843 clusters[x][Y_SIZE - 1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE - 1][NORTH]); 844 clusters[x][Y_SIZE - 1]->p_m2p_out[NORTH](signal_dspin_bound_m2p_out[x][Y_SIZE - 1][NORTH]); 873 845 874 846 clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]); 875 847 clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]); 876 clusters[x][Y_SIZE -1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);877 clusters[x][Y_SIZE -1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);848 clusters[x][Y_SIZE - 1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE - 1][NORTH]); 849 clusters[x][Y_SIZE - 1]->p_p2m_out[NORTH](signal_dspin_bound_p2m_out[x][Y_SIZE - 1][NORTH]); 878 850 879 851 clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]); 880 852 clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]); 881 clusters[x][Y_SIZE -1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]);882 clusters[x][Y_SIZE -1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]);853 clusters[x][Y_SIZE - 1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE - 1][NORTH]); 854 clusters[x][Y_SIZE - 1]->p_cla_out[NORTH](signal_dspin_bound_cla_out[x][Y_SIZE - 1][NORTH]); 883 855 } 884 856 … … 893 865 GdbServer<Mips32ElIss> > * > l1_caches; 894 866 895 for ( size_t x = 0; x < X_SIZE; x++) {896 for ( size_t y = 0; y < Y_SIZE; y++) {867 for (int x = 0; x < X_SIZE; x++) { 868 for (int y = 0; y < Y_SIZE; y++) { 897 869 for (int proc = 0; proc < NB_PROCS_MAX; proc++) { 898 870 l1_caches.push_back(clusters[x][y]->proc[proc]); … … 901 873 } 902 874 903 for ( size_t x = 0; x < X_SIZE; x++) {904 for ( size_t y = 0; y < Y_SIZE; y++) {875 for (int x = 0; x < X_SIZE; x++) { 876 for (int y = 0; y < Y_SIZE; y++) { 905 877 clusters[x][y]->memc->set_vcache_list(l1_caches); 906 878 } … … 913 885 sc_trace_file * tf = sc_create_vcd_trace_file("my_trace_file"); 914 886 915 if (X_SIZE > 1){ 916 for (size_t x = 0; x < (X_SIZE-1); x++){ 917 for (size_t y = 0; y < Y_SIZE; y++){ 918 for (size_t k = 0; k < 3; k++){ 919 signal_dspin_h_cmd_inc[x][y][k].trace(tf, "dspin_h_cmd_inc"); 920 signal_dspin_h_cmd_dec[x][y][k].trace(tf, "dspin_h_cmd_dec"); 921 } 922 923 for (size_t k = 0; k < 2; k++){ 924 signal_dspin_h_rsp_inc[x][y][k].trace(tf, "dspin_h_rsp_inc"); 925 signal_dspin_h_rsp_dec[x][y][k].trace(tf, "dspin_h_rsp_dec"); 926 } 927 } 928 } 929 } 930 931 if (Y_SIZE > 1) { 932 for (size_t y = 0; y < (Y_SIZE-1); y++){ 933 for (size_t x = 0; x < X_SIZE; x++){ 934 for (size_t k = 0; k < 3; k++){ 935 signal_dspin_v_cmd_inc[x][y][k].trace(tf, "dspin_v_cmd_inc"); 936 signal_dspin_v_cmd_dec[x][y][k].trace(tf, "dspin_v_cmd_dec"); 937 } 938 939 for (size_t k = 0; k < 2; k++){ 940 signal_dspin_v_rsp_inc[x][y][k].trace(tf, "dspin_v_rsp_inc"); 941 signal_dspin_v_rsp_dec[x][y][k].trace(tf, "dspin_v_rsp_dec"); 942 } 943 } 944 } 945 } 946 947 for (size_t x = 0; x < (X_SIZE); x++){ 948 for (size_t y = 0; y < Y_SIZE; y++){ 887 for (int x = 0; x < X_SIZE - 1; x++) { 888 for (int y = 0; y < Y_SIZE; y++) { 889 for (int k = 0; k < 3; k++) { 890 signal_dspin_h_cmd_inc[x][y][k].trace(tf, "dspin_h_cmd_inc"); 891 signal_dspin_h_cmd_dec[x][y][k].trace(tf, "dspin_h_cmd_dec"); 892 } 893 894 for (int k = 0; k < 2; k++) { 895 signal_dspin_h_rsp_inc[x][y][k].trace(tf, "dspin_h_rsp_inc"); 896 signal_dspin_h_rsp_dec[x][y][k].trace(tf, "dspin_h_rsp_dec"); 897 } 898 } 899 } 900 901 for (int y = 0; y < Y_SIZE - 1; y++) { 902 for (int x = 0; x < X_SIZE; x++) { 903 for (int k = 0; k < 3; k++) { 904 signal_dspin_v_cmd_inc[x][y][k].trace(tf, "dspin_v_cmd_inc"); 905 signal_dspin_v_cmd_dec[x][y][k].trace(tf, "dspin_v_cmd_dec"); 906 } 907 908 for (int k = 0; k < 2; k++) { 909 signal_dspin_v_rsp_inc[x][y][k].trace(tf, "dspin_v_rsp_inc"); 910 signal_dspin_v_rsp_dec[x][y][k].trace(tf, "dspin_v_rsp_dec"); 911 } 912 } 913 } 914 915 for (int x = 0; x < (X_SIZE); x++) { 916 for (int y = 0; y < Y_SIZE; y++) { 949 917 std::ostringstream signame; 950 918 signame << "cluster" << x << "_" << y; … … 994 962 } 995 963 } 964 // @M debug fu** 965 clusters[0][0]->signal_dspin_m2p_proc[2].read = true; 996 966 997 967 sc_start(sc_core::sc_time(1, SC_NS)); … … 1008 978 } 1009 979 1010 for (int64_t n = 1; n < ncycles && !stop_called; n++) 1011 { 1012 if ((n % max_cycles) == 0) 1013 { 1014 1015 if (gettimeofday(&t2, NULL) != 0) 1016 { 980 for (int64_t n = 1; n < ncycles && !stop_called; n++) { 981 if ((n % max_cycles) == 0) { 982 983 if (gettimeofday(&t2, NULL) != 0) { 1017 984 perror("gettimeofday"); 1018 985 return EXIT_FAILURE; … … 1047 1014 } 1048 1015 1049 if ((n > debug_from) and (n % debug_period == 0)) 1050 { 1016 if ((n > debug_from) and (n % debug_period == 0)) { 1051 1017 std::cout << "****************** cycle " << std::dec << n ; 1052 1018 std::cout << "************************************************" << std::endl; 1053 1019 1054 for (size_t x = 0; x < X_SIZE ; x++) {1055 for (size_t y = 0; y < Y_SIZE ; y++) {1020 for (size_t x = 0; x < X_SIZE ; x++) { 1021 for (size_t y = 0; y < Y_SIZE ; y++) { 1056 1022 for (int proc = 0; proc < NB_PROCS_MAX; proc++) { 1023 if (x == 0 && y == 0 && proc == 2) { 1024 continue; 1025 } 1057 1026 clusters[x][y]->proc[proc]->print_trace(); 1058 1027 std::ostringstream proc_signame; … … 1141 1110 1142 1111 // Free memory 1143 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) 1144 { 1112 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) { 1145 1113 size_t x = i / Y_SIZE; 1146 1114 size_t y = i % Y_SIZE; … … 1148 1116 } 1149 1117 1150 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X_SIZE -1, Y_SIZE);1151 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X_SIZE -1, Y_SIZE);1152 1153 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X_SIZE -1, Y_SIZE);1154 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X_SIZE -1, Y_SIZE);1155 1156 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_m2p_inc, X_SIZE -1, Y_SIZE);1157 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_m2p_dec, X_SIZE -1, Y_SIZE);1158 1159 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_p2m_inc, X_SIZE -1, Y_SIZE);1160 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_p2m_dec, X_SIZE -1, Y_SIZE);1161 1162 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cla_inc, X_SIZE -1, Y_SIZE);1163 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cla_dec, X_SIZE -1, Y_SIZE);1164 1165 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE -1);1166 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE -1);1167 1168 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE -1);1169 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE -1);1170 1171 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_m2p_inc, X_SIZE, Y_SIZE -1);1172 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_m2p_dec, X_SIZE, Y_SIZE -1);1173 1174 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_p2m_inc, X_SIZE, Y_SIZE -1);1175 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_p2m_dec, X_SIZE, Y_SIZE -1);1176 1177 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cla_inc, X_SIZE, Y_SIZE -1);1178 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cla_dec, X_SIZE, Y_SIZE -1);1118 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X_SIZE - 1, Y_SIZE); 1119 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X_SIZE - 1, Y_SIZE); 1120 1121 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X_SIZE - 1, Y_SIZE); 1122 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X_SIZE - 1, Y_SIZE); 1123 1124 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_m2p_inc, X_SIZE - 1, Y_SIZE); 1125 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_m2p_dec, X_SIZE - 1, Y_SIZE); 1126 1127 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_p2m_inc, X_SIZE - 1, Y_SIZE); 1128 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_p2m_dec, X_SIZE - 1, Y_SIZE); 1129 1130 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cla_inc, X_SIZE - 1, Y_SIZE); 1131 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cla_dec, X_SIZE - 1, Y_SIZE); 1132 1133 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE - 1); 1134 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE - 1); 1135 1136 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE - 1); 1137 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE - 1); 1138 1139 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_m2p_inc, X_SIZE, Y_SIZE - 1); 1140 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_m2p_dec, X_SIZE, Y_SIZE - 1); 1141 1142 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_p2m_inc, X_SIZE, Y_SIZE - 1); 1143 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_p2m_dec, X_SIZE, Y_SIZE - 1); 1144 1145 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cla_inc, X_SIZE, Y_SIZE - 1); 1146 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cla_dec, X_SIZE, Y_SIZE - 1); 1179 1147 1180 1148 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cmd_in, X_SIZE, Y_SIZE, 4); … … 1204 1172 void voidhandler(int dummy = 0) {} 1205 1173 1206 int sc_main (int argc, char *argv[]) 1207 { 1174 int sc_main (int argc, char *argv[]) { 1208 1175 signal(SIGINT, handler); 1209 1176 signal(SIGPIPE, voidhandler); … … 1213 1180 } catch (std::exception &e) { 1214 1181 std::cout << e.what() << std::endl; 1215 } catch (...) { 1182 } 1183 catch (...) { 1216 1184 std::cout << "Unknown exception occured" << std::endl; 1217 1185 throw; -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
r885 r1023 190 190 size_t y_width, // y field bits 191 191 size_t l_width, // l field bits 192 size_t p_width, 192 193 size_t tgtid_memc, 193 194 size_t tgtid_xicu, -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp
r885 r1023 50 50 size_t y_width, 51 51 size_t l_width, 52 size_t p_width, 52 53 size_t tgtid_memc, 53 54 size_t tgtid_xicu, … … 85 86 : soclib::caba::BaseModule(insname), 86 87 p_clk("clk"), 87 p_resetn("resetn") 88 89 { 88 p_resetn("resetn") { 90 89 91 90 n_procs = nb_procs; … … 114 113 ///////////////////////////////////////////////////////////////////////////// 115 114 116 for (size_t p = 0; p < nb_procs; p++) 117 { 115 for (size_t p = 0; p < nb_procs; p++) { 118 116 std::ostringstream sproc; 119 117 sproc << "proc_" << x_id << "_" << y_id << "_" << p; … … 123 121 GdbServer<Mips32ElIss> >( 124 122 sproc.str().c_str(), 125 cluster_id * nb_procs + p,// GLOBAL PROC_ID123 (cluster_id << p_width) + p, // GLOBAL PROC_ID 126 124 mtd, // Mapping Table 127 IntTab(cluster_id, p),// SRCID125 IntTab(cluster_id, p), // SRCID 128 126 (cluster_id << l_width) + p, // CC_GLOBAL_ID 129 127 8, // ITLB ways … … 205 203 size_t nb_direct_initiators = nb_procs + 1; 206 204 size_t nb_direct_targets = 3; 207 if (io) 208 { 205 if (io) { 209 206 nb_direct_initiators = nb_procs + 3; 210 207 nb_direct_targets = 10; … … 321 318 322 319 // IO cluster components 323 if (io) 324 { 320 if (io) { 325 321 ///////////////////////////////////////////// 326 322 brom = new VciSimpleRom<vci_param_int>( … … 371 367 ///////////////////////////////////////////// 372 368 std::vector<std::string> vect_names; 373 for (size_t tid = 0; tid < nb_ttys; tid++) 374 { 369 for (size_t tid = 0; tid < nb_ttys; tid++) { 375 370 std::ostringstream term_name; 376 371 term_name << "term" << tid; … … 406 401 407 402 // loop on N/S/E/W ports 408 for (size_t i = 0; i < 4; i++) 409 { 403 for (size_t i = 0; i < 4; i++) { 410 404 router_cmd->p_out[i] (this->p_cmd_out[i]); 411 405 router_cmd->p_in[i] (this->p_cmd_in[i]); … … 469 463 xbar_d->p_to_initiator[nb_procs] (signal_vci_ini_mdma); 470 464 471 for (size_t p = 0; p < nb_procs; p++) 465 for (size_t p = 0; p < nb_procs; p++) { 472 466 xbar_d->p_to_initiator[p] (signal_vci_ini_proc[p]); 473 474 if (io) 475 {467 } 468 469 if (io) { 476 470 xbar_d->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty); 477 471 xbar_d->p_to_target[tgtid_brom] (signal_vci_tgt_brom); … … 494 488 xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c); 495 489 xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc); 496 for (size_t p = 0; p < nb_procs; p++) 490 for (size_t p = 0; p < nb_procs; p++) { 497 491 xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]); 492 } 498 493 499 494 std::cout << " - M2P Coherence crossbar connected" << std::endl; … … 505 500 xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c); 506 501 xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc); 507 for (size_t p = 0; p < nb_procs; p++) 502 for (size_t p = 0; p < nb_procs; p++) { 508 503 xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]); 504 } 509 505 510 506 std::cout << " - Clack Coherence crossbar connected" << std::endl; … … 516 512 xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c); 517 513 xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc); 518 for (size_t p = 0; p < nb_procs; p++) 514 for (size_t p = 0; p < nb_procs; p++) { 519 515 xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]); 516 } 520 517 521 518 std::cout << " - P2M Coherence crossbar connected" << std::endl; … … 523 520 524 521 //////////////////////////////////// Processors 525 for (size_t p = 0; p < nb_procs; p++) 526 { 522 for (size_t p = 0; p < nb_procs; p++) { 527 523 proc[p]->p_clk (this->p_clk); 528 524 proc[p]->p_resetn (this->p_resetn); … … 532 528 proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]); 533 529 534 for ( size_t i = 0; i < irq_per_processor; i++) 535 { 530 for ( size_t i = 0; i < irq_per_processor; i++) { 536 531 proc[p]->p_irq[i] (signal_proc_it[p*irq_per_processor + i]); 537 532 } 538 for ( size_t j = irq_per_processor; j < 6; j++) // 6 = number of irqs in the MIPS539 {533 for ( size_t j = irq_per_processor; j < 6; j++) { 534 // 6 = number of irqs in the MIPS 540 535 proc[p]->p_irq[j] (signal_false); 541 536 } … … 549 544 xicu->p_resetn (this->p_resetn); 550 545 xicu->p_vci (signal_vci_tgt_xicu); 551 for (size_t p = 0; p < nb_procs * irq_per_processor; p++) 552 { 546 for (size_t p = 0; p < nb_procs * irq_per_processor; p++) { 553 547 xicu->p_irq[p] (signal_proc_it[p]); 554 548 } 555 for (size_t i = 0; i < 32; i++) 556 { 557 if (io) // I/O cluster 558 { 549 for (size_t i = 0; i < 32; i++) { 550 if (io) { 551 // I/O cluster 559 552 if (i < 8) xicu->p_hwi[i] (signal_false); 560 553 else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); … … 565 558 else xicu->p_hwi[i] (signal_irq_bdev); 566 559 } 567 else // other clusters568 {560 else { 561 // other clusters 569 562 if (i < 8) xicu->p_hwi[i] (signal_false); 570 563 else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); … … 601 594 mdma->p_vci_target (signal_vci_tgt_mdma); 602 595 mdma->p_vci_initiator (signal_vci_ini_mdma); 603 for (size_t i = 0; i < nb_dmas; i++) 596 for (size_t i = 0; i < nb_dmas; i++) { 604 597 mdma->p_irq[i] (signal_irq_mdma[i]); 598 } 605 599 606 600 std::cout << " - MDMA connected" << std::endl; … … 608 602 /////////////////////////////// Components in I/O cluster 609 603 610 if (io) 611 { 604 if (io) { 612 605 // BDEV 613 606 bdev->p_clk (this->p_clk); … … 630 623 mnic->p_resetn (this->p_resetn); 631 624 mnic->p_vci (signal_vci_tgt_mnic); 632 for (size_t i = 0; i < nic_channels; i++) 633 { 625 for (size_t i = 0; i < nic_channels; i++) { 634 626 mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); 635 627 mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); … … 643 635 chbuf->p_vci_target (signal_vci_tgt_chbuf); 644 636 chbuf->p_vci_initiator (signal_vci_ini_chbuf); 645 for (size_t i = 0; i < chbufdma_channels; i++) 646 { 637 for (size_t i = 0; i < chbufdma_channels; i++) { 647 638 chbuf->p_irq[i] (signal_irq_chbuf[i]); 648 639 } … … 661 652 mtty->p_resetn (this->p_resetn); 662 653 mtty->p_vci (signal_vci_tgt_mtty); 663 for (size_t i = 0; i < nb_ttys; i++) 664 { 654 for (size_t i = 0; i < nb_ttys; i++) { 665 655 mtty->p_irq[i] (signal_irq_mtty[i]); 666 656 } … … 703 693 dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cla_out, 4); 704 694 705 for (size_t p = 0; p < n_procs; p++) 706 { 695 for (size_t p = 0; p < n_procs; p++) { 707 696 delete proc[p]; 708 697 } … … 720 709 delete router_cmd; 721 710 delete router_rsp; 722 if (brom != NULL) 723 { 711 if (brom != NULL) { 724 712 delete brom; 725 713 delete fbuf;
Note: See TracChangeset
for help on using the changeset viewer.