Changeset 1023 for trunk/platforms/tsar_generic_xbar/scripts/gen_hard_config.py

Timestamp:

Oct 21, 2015, 11:48:40 AM (9 years ago)

Author:

meunier

Message:

• Update the scripts to use a common file hard_params.py in both gen_arch_info and gen_hdd
• Adding the P_WIDTH parameter in the topcell

File:

• trunk/platforms/tsar_generic_xbar/scripts/gen_hard_config.py (modified) (4 diffs)

trunk/platforms/tsar_generic_xbar/scripts/gen_hard_config.py

@@ -1 +1 @@
 
+
+exec(file("hard_params.py"))
 
 
 def hard_config(x, y, x_width, y_width, p, hard_config, protocol):
+
+    x_io = get_x_io(x_width, y_width)
+    y_io = get_y_io(x_width, y_width)
     
-    ram_tgtid = 0
-    xcu_tgtid = 1
-    dma_tgtid = 2
-    tty_tgtid = 3
-    ioc_tgtid = 4
-    nic_tgtid = 5
-    rom_tgtid = 6
-    cma_tgtid = 7
-    sim_tgtid = 8
-    fbf_tgtid = 9
-
-    nb_dma_channels = 1
-    nb_cma_channels = 0
-    nb_tty_channels = 4
-    nb_ioc_channels = 1
-
-    fbf_x_size = 1024
-    fbf_y_size = 1024
-
-    seg_rom_base = 0xbfc00000
-    seg_rom_size = 0x00100000
-
-    cluster_inc = 0x80000000 / (x * y) * 2
-    cluster_io_id = seg_rom_base >> (32 - x_width - y_width)
-    cluster_io_inc = cluster_io_id * cluster_inc
-    ram_max_size = 0x40000000 / (x * y) # 1 Go Max
-    
-    seg_ram_base = 0x00000000
-    seg_ram_size = min(0x10000000, ram_max_size)
-
-    seg_xcu_base = (cluster_inc >> 1) + (xcu_tgtid << 19)
-    seg_xcu_size = 0x00001000 # 4Ko
-
-    seg_dma_base = (cluster_inc >> 1) + (dma_tgtid << 19)
-    seg_dma_size = 0x00001000 * nb_dma_channels
-
-    def periph_address(tgtid):
-        return (cluster_inc >> 1) + cluster_io_inc + (tgtid << 19)
-
-    seg_ioc_base = periph_address(ioc_tgtid);
-    seg_ioc_size = 0x00001000
-
-    seg_tty_base = periph_address(tty_tgtid)
-    seg_tty_size = 0x00001000
-
-    seg_fbf_base = periph_address(fbf_tgtid)
-    seg_fbf_size = fbf_x_size * fbf_y_size * 2
-
-    seg_nic_base = periph_address(nic_tgtid)
-    seg_nic_size = 0x00080000
-
-    seg_cma_base = periph_address(cma_tgtid)
-    seg_cma_size = 0x00004000 * nb_cma_channels
-
-    seg_sim_base = periph_address(sim_tgtid)
-    seg_sim_size = 0x00001000
+    seg_rom_base = BOOT_ADDR
+    seg_rom_size = ROM_SIZE
+
+    seg_ram_base = RAM_BASE
+    seg_ram_size = ram_size(x_width, y_width)
+
+    seg_xcu_base = replicated_periph_base_addr(x_width, y_width, XCU_TGTID)
+    seg_xcu_size = XCU_SIZE
+
+    seg_dma_base = replicated_periph_base_addr(x_width, y_width, DMA_TGTID)
+    seg_dma_size = DMA_SIZE * NB_DMA_CHANNELS
+
+    seg_ioc_base = periph_addr(x_width, y_width, IOC_TGTID);
+    seg_ioc_size = IOC_SIZE
+
+    seg_tty_base = periph_addr(x_width, y_width, TTY_TGTID)
+    seg_tty_size = TTY_SIZE
+
+    seg_fbf_base = periph_addr(x_width, y_width, FBF_TGTID)
+    seg_fbf_size = FBF_X_SIZE * FBF_Y_SIZE * 2
+
+    seg_nic_base = periph_addr(x_width, y_width, NIC_TGTID)
+    seg_nic_size = NIC_SIZE
+
+    seg_cma_base = periph_addr(x_width, y_width, CMA_TGTID)
+    seg_cma_size = CMA_SIZE * NB_CMA_CHANNELS
+
+    seg_sim_base = periph_addr(x_width, y_width, SIM_TGTID)
+    seg_sim_size = SIM_SIZE
 
     header = '''
@@ -65 +43 @@
 #define _HARD_CONFIG_H_
 
-/* Generated from run_simus.py */
+/* Generated from gen_hard_config.py */
 
 /* General platform parameters */
@@ -74 +52 @@
 #define Y_WIDTH                %(y_width)d
 #define P_WIDTH                4
-#define X_IO                   0
-#define Y_IO                   0
+#define X_IO                   %(x_io)d
+#define Y_IO                   %(y_io)d
 #define NB_PROCS_MAX           %(proc_per_clus)d
 #define IRQ_PER_PROCESSOR      4
@@ -169 +147 @@
 
 ''' % dict(x_size = x, y_size = y, x_width = x_width, y_width = y_width,
+        x_io = x_io,
+        y_io = y_io,
         proc_per_clus = p,
-        nb_tty_channels = nb_tty_channels,
-        nb_ioc_channels = nb_ioc_channels,
-        nb_cma_channels = nb_cma_channels,
-        nb_dma_channels = nb_dma_channels,
-        fbf_x_size = fbf_x_size, fbf_y_size = fbf_y_size,
-        ram_tgtid = ram_tgtid,
-        xcu_tgtid = xcu_tgtid,
-        dma_tgtid = dma_tgtid,
-        tty_tgtid = tty_tgtid,
-        ioc_tgtid = ioc_tgtid,
-        nic_tgtid = nic_tgtid,
-        rom_tgtid = rom_tgtid,
-        cma_tgtid = cma_tgtid,
-        sim_tgtid = sim_tgtid,
-        fbf_tgtid = fbf_tgtid,
+        nb_tty_channels = NB_TTY_CHANNELS,
+        nb_ioc_channels = NB_IOC_CHANNELS,
+        nb_cma_channels = NB_CMA_CHANNELS,
+        nb_dma_channels = NB_DMA_CHANNELS,
+        fbf_x_size = FBF_X_SIZE, fbf_y_size = FBF_Y_SIZE,
+        ram_tgtid = RAM_TGTID,
+        xcu_tgtid = XCU_TGTID,
+        dma_tgtid = DMA_TGTID,
+        tty_tgtid = TTY_TGTID,
+        ioc_tgtid = IOC_TGTID,
+        nic_tgtid = NIC_TGTID,
+        rom_tgtid = ROM_TGTID,
+        cma_tgtid = CMA_TGTID,
+        sim_tgtid = SIM_TGTID,
+        fbf_tgtid = FBF_TGTID,
         seg_ram_base = seg_ram_base,
         seg_ram_size = seg_ram_size,