Changeset 1050 for trunk/platforms/tsar_generic_iob
- Timestamp:
- Apr 6, 2017, 5:01:31 PM (8 years ago)
- Location:
- trunk/platforms/tsar_generic_iob
- Files:
-
- 6 edited
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arch.py (modified) (4 diffs)
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arch_info.py (modified) (14 diffs)
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top.cpp (modified) (43 diffs)
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top.desc (modified) (1 diff)
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tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (1 diff)
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tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/platforms/tsar_generic_iob/arch.py
r1033 r1050 65 65 ### define architecture constants 66 66 67 nb_nics = 1 68 nb_cmas = 4 67 if ( x_size * y_size >= 4 ) : nb_nics = 4 68 elif ( x_size * y_size == 2 ) : nb_nics = 2 69 else : nb_nics = 1 70 71 nb_cmas = 1 69 72 x_io = 0 70 73 y_io = 0 … … 124 127 125 128 nic_base = 0x00B5000000 126 nic_size = 0x 80000 # 512kbytes129 nic_size = 0x1000 # 4 Kkbytes 127 130 128 131 cma_base = 0x00B6000000 … … 171 174 172 175 kernel_heap_vbase = 0xD0000000 173 kernel_heap_size = 0x00 400000 # 4Mbytes per cluster176 kernel_heap_size = 0x00200000 # 2 Mbytes per cluster 174 177 175 178 kernel_sched_vbase = 0xA0000000 … … 267 270 ptype = 'PIC', channels = 32 ) 268 271 272 if ( ioc_type == 'BDV' ): isr_ioc = 'ISR_BDV' 273 if ( ioc_type == 'HBA' ): isr_ioc = 'ISR_HBA' 274 if ( ioc_type == 'SDC' ): isr_ioc = 'ISR_SDC' 275 if ( ioc_type == 'SPI' ): isr_ioc = 'ISR_SPI' 276 269 277 mapping.addIrq( pic, index = 0, src = nic, 270 278 isrtype = 'ISR_NIC_RX', channel = 0 ) 271 279 mapping.addIrq( pic, index = 1, src = nic, 272 280 isrtype = 'ISR_NIC_RX', channel = 1 ) 273 274 281 mapping.addIrq( pic, index = 2, src = nic, 282 isrtype = 'ISR_NIC_RX', channel = 2 ) 283 mapping.addIrq( pic, index = 3, src = nic, 284 isrtype = 'ISR_NIC_RX', channel = 3 ) 285 286 mapping.addIrq( pic, index = 4, src = nic, 275 287 isrtype = 'ISR_NIC_TX', channel = 0 ) 276 mapping.addIrq( pic, index = 3, src = nic,288 mapping.addIrq( pic, index = 5, src = nic, 277 289 isrtype = 'ISR_NIC_TX', channel = 1 ) 278 279 mapping.addIrq( pic, index = 4, src = cma, 290 mapping.addIrq( pic, index = 6, src = nic, 291 isrtype = 'ISR_NIC_TX', channel = 2 ) 292 mapping.addIrq( pic, index = 7, src = nic, 293 isrtype = 'ISR_NIC_TX', channel = 3 ) 294 295 mapping.addIrq( pic, index = 8 , src = cma, 280 296 isrtype = 'ISR_CMA', channel = 0 ) 281 mapping.addIrq( pic, index = 5, src = cma,297 mapping.addIrq( pic, index = 9 , src = cma, 282 298 isrtype = 'ISR_CMA', channel = 1 ) 283 mapping.addIrq( pic, index = 6, src = cma,299 mapping.addIrq( pic, index = 10, src = cma, 284 300 isrtype = 'ISR_CMA', channel = 2 ) 285 mapping.addIrq( pic, index = 7, src = cma,301 mapping.addIrq( pic, index = 11, src = cma, 286 302 isrtype = 'ISR_CMA', channel = 3 ) 287 303 288 if ( ioc_type == 'BDV' ): isr_ioc = 'ISR_BDV' 289 if ( ioc_type == 'HBA' ): isr_ioc = 'ISR_HBA' 290 if ( ioc_type == 'SDC' ): isr_ioc = 'ISR_SDC' 291 if ( ioc_type == 'SPI' ): isr_ioc = 'ISR_SPI' 292 293 mapping.addIrq( pic, index = 8, src = ioc, 304 mapping.addIrq( pic, index = 12, src = ioc, 294 305 isrtype = isr_ioc, channel = 0 ) 306 295 307 mapping.addIrq( pic, index = 16, src = tty, 296 308 isrtype = 'ISR_TTY_RX', channel = 0 ) -
trunk/platforms/tsar_generic_iob/arch_info.py
r1046 r1050 29 29 # - nb_ttys : number of TTY channels (can be from 1 to 8) 30 30 # - nb_nics : number of NIC channels (from 1 to 2) 31 # - nb_cmas : number of CMA channels (from 1 to 4)32 31 # - fbf_width : frame_buffer width = frame_buffer heigth 33 32 # - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' … … 35 34 # - io_cxy : IO cluster identifier 36 35 # - boot_cxy : boot cluster identifier 36 # - cache_line : number of bytes in cache line (in 16,32,64) 37 37 # 38 38 # The following parameters are imposed by the "tsar_generic_iob" architecture: … … 51 51 nb_ttys = 1, 52 52 nb_nics = 1, 53 nb_cmas = 2,54 53 fbf_width = 128, 55 54 ioc_type = 'IOC_BDV', 56 55 mwr_type = 'MWR_CPY', 57 56 io_cxy = 0, 58 boot_cxy = 0 ): 57 boot_cxy = 0, 58 cache_line = 64): 59 59 60 60 ### architecture constants … … 81 81 assert( (nb_nics >= 1) and (nb_nics <= 2) ) 82 82 83 assert( (nb_cmas >= 1) and (nb_cmas <= 4) )84 85 83 assert( ioc_type in ['IOC_BDV','IOC_HBA','IOC_SDC','IOC_SPI','IOC_RDK'] ) 86 84 … … 90 88 91 89 assert( ((boot_cxy >> y_width) < x_size) and ((boot_cxy & ((1<<y_width)-1)) < y_size) ) 90 91 assert( (cache_line == 16) or (cache_line == 32) or (cache_line == 64) ) 92 92 93 93 ### define platform name … … 98 98 99 99 ram_base = 0x0000000000 100 ram_size = 0x 4000000 # 64Mbytes100 ram_size = 0x800000 # 8 Mbytes 101 101 102 102 xcu_base = 0x00B0000000 … … 119 119 120 120 nic_base = 0x00B5000000 121 nic_size = 0x80000 # 512 kbytes 122 123 cma_base = 0x00B6000000 124 cma_size = 0x1000 * nb_cmas # 4 kbytes * nb_cmas 121 nic_size = 0x4000 # 16 kbytes 125 122 126 123 fbf_base = 0x00B7000000 … … 151 148 io_cxy = io_cxy, 152 149 boot_cxy = boot_cxy, 150 cache_line = cache_line, 153 151 reset_address = rom_base, 154 152 p_width = p_width ) … … 163 161 offset = cxy << (paddr_width - x_width - y_width) 164 162 165 # builddevices166 ram = archi.addDevice( ptype = 'RAM ' ,163 # define internal devices 164 ram = archi.addDevice( ptype = 'RAM_SCL' , 167 165 base = ram_base + offset, 168 166 size = ram_size ) 169 167 170 xcu = archi.addDevice( ptype = ' XCU',168 xcu = archi.addDevice( ptype = 'ICU_XCU', 171 169 base = xcu_base + offset, 172 170 size = xcu_size, 173 channels = nb_cores * irqs_per_core,171 channels = 1, 174 172 arg0 = 16, 175 173 arg1 = 16, 176 arg2 = 16 ) 177 178 mmc = archi.addDevice( ptype = 'MMC', 174 arg2 = 16, 175 arg3 = 16 ) 176 177 mmc = archi.addDevice( ptype = 'MMC_TSR', 179 178 base = mmc_base + offset, 180 179 size = mmc_size ) 181 archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc, isrtype = 'ISR_MMC' ) 180 181 archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc ) 182 182 183 183 if ( mwr_type == 'MWR_GCD' ): … … 189 189 arg2 = 1, 190 190 arg3 = 0 ) 191 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr , isrtype = 'ISR_MWR')191 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 192 192 193 193 if ( mwr_type == 'MWR_DCT' ): … … 199 199 arg2 = 1, 200 200 arg3 = 0 ) 201 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr , isrtype = 'ISR_MWR')201 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 202 202 203 203 if ( mwr_type == 'MWR_CPY' ): … … 209 209 arg2 = 1, 210 210 arg3 = 0 ) 211 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) 212 211 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 212 213 # define external devices 213 214 if( cxy == io_cxy ): 214 215 215 iob = archi.addDevice( ptype = 'IOB ',216 iob = archi.addDevice( ptype = 'IOB_TSR', 216 217 base = iob_base + offset, 217 218 size = iob_size ) … … 221 222 size = ioc_size ) 222 223 223 tty = archi.addDevice( ptype = 'T TY',224 tty = archi.addDevice( ptype = 'TXT_TTY', 224 225 base = tty_base + offset, 225 226 size = tty_size, 226 227 channels = nb_ttys ) 227 228 228 nic = archi.addDevice( ptype = 'NIC ',229 nic = archi.addDevice( ptype = 'NIC_CBF', 229 230 base = nic_base + offset, 230 231 size = nic_size, 231 232 channels = nb_nics ) 232 233 233 cma = archi.addDevice( ptype = 'CMA', 234 base = cma_base + offset, 235 size = cma_size, 236 channels = nb_cmas ) 237 238 fbf = archi.addDevice( ptype = 'FBF', 234 fbf = archi.addDevice( ptype = 'FBF_SCL', 239 235 base = fbf_base + offset, 240 236 size = fbf_size, … … 242 238 arg1 = fbf_width ) 243 239 244 rom = archi.addDevice( ptype = 'ROM ',240 rom = archi.addDevice( ptype = 'ROM_SCL', 245 241 base = rom_base + offset, 246 242 size = rom_size ) 247 243 248 pic = archi.addDevice( ptype ='PIC ',244 pic = archi.addDevice( ptype ='PIC_TSR', 249 245 base = pic_base + offset, 250 246 size = pic_size, 251 247 arg0 = 32 ) 252 248 253 if ( ioc_type == 'IOC_BDV' ): isr_ioc = 'ISR_BDV' 254 elif ( ioc_type == 'IOC_HBA' ): isr_ioc = 'ISR_HBA' 255 elif ( ioc_type == 'IOC_SDC' ): isr_ioc = 'ISR_SDC' 256 elif ( ioc_type == 'IOC_SPI' ): isr_ioc = 'ISR_SPI' 257 else : isr_ioc = 'ISR_DEFAULT' 258 259 archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 0 ) 260 archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 1 ) 261 archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 0 ) 262 archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 1 ) 263 archi.addIrq( dstdev = pic, port = 4 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 0 ) 264 archi.addIrq( dstdev = pic, port = 5 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 1 ) 265 archi.addIrq( dstdev = pic, port = 6 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 2 ) 266 archi.addIrq( dstdev = pic, port = 7 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 3 ) 267 archi.addIrq( dstdev = pic, port = 8 , srcdev = ioc, isrtype = isr_ioc , channel = 0 ) 268 archi.addIrq( dstdev = pic, port = 16, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 0 ) 269 archi.addIrq( dstdev = pic, port = 17, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 1 ) 270 archi.addIrq( dstdev = pic, port = 18, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 2 ) 271 archi.addIrq( dstdev = pic, port = 19, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 3 ) 272 archi.addIrq( dstdev = pic, port = 20, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 4 ) 273 archi.addIrq( dstdev = pic, port = 21, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 5 ) 274 archi.addIrq( dstdev = pic, port = 22, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 6 ) 275 archi.addIrq( dstdev = pic, port = 23, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 7 ) 276 277 # build cores 249 archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, channel = 0 , is_rx = True ) 250 archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, channel = 1 , is_rx = True ) 251 archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, channel = 2 , is_rx = True ) 252 archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, channel = 3 , is_rx = True ) 253 254 archi.addIrq( dstdev = pic, port = 4 , srcdev = nic, channel = 0 , is_rx = False ) 255 archi.addIrq( dstdev = pic, port = 5 , srcdev = nic, channel = 1 , is_rx = False ) 256 archi.addIrq( dstdev = pic, port = 6 , srcdev = nic, channel = 2 , is_rx = False ) 257 archi.addIrq( dstdev = pic, port = 7 , srcdev = nic, channel = 3 , is_rx = False ) 258 259 archi.addIrq( dstdev = pic, port = 12, srcdev = ioc ) 260 261 archi.addIrq( dstdev = pic, port = 16, srcdev = tty, channel = 0 , is_rx = True ) 262 archi.addIrq( dstdev = pic, port = 17, srcdev = tty, channel = 1 , is_rx = True ) 263 archi.addIrq( dstdev = pic, port = 18, srcdev = tty, channel = 2 , is_rx = True ) 264 archi.addIrq( dstdev = pic, port = 19, srcdev = tty, channel = 3 , is_rx = True ) 265 archi.addIrq( dstdev = pic, port = 20, srcdev = tty, channel = 4 , is_rx = True ) 266 archi.addIrq( dstdev = pic, port = 21, srcdev = tty, channel = 5 , is_rx = True ) 267 archi.addIrq( dstdev = pic, port = 22, srcdev = tty, channel = 6 , is_rx = True ) 268 archi.addIrq( dstdev = pic, port = 23, srcdev = tty, channel = 7 , is_rx = True ) 269 270 # define cores 278 271 for p in xrange ( nb_cores ): 279 core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p, # hardware id entifier280 (x<<y_width) + y, # cluster identifier272 core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p, # hardware id 273 (x<<y_width) + y, # cluster 281 274 p ) # local index 282 275 -
trunk/platforms/tsar_generic_iob/top.cpp
r1046 r1050 12 12 // - FBUF : Frame Buffer 13 13 // - MTTY : multi TTY (one channel) 14 // - MNIC : Network controller (up to 16 channels) 15 // - CDMA : Chained Buffer DMA controller (up to 4 channels) 14 // - MNIC : Network controller (up to 4 channels) 16 15 // - DISK : Block device controler (BDV / HBA / SDC) 17 16 // - IOPI : HWI to SWI translator. … … 42 41 // external IOPIC component, that must be configured by the OS to route 43 42 // these WTI IRQS to one or several internal XICU components. 44 // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] 45 // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] 46 // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] 47 // - IOPIC HWI[8] connected to IRQ_DISK 43 // - IOPIC HWI[3:0] connected to IRQ_NIC_RX[3:0] 44 // - IOPIC HWI[7:4] connected to IRQ_NIC_TX[3:0] 45 // - IOPIC HWI[12] connected to IRQ_IOC 48 46 // - IOPIC HWI[31:16] connected to IRQ_TTY_RX[15:0] 49 47 // … … 60 58 // 61 59 // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) 62 // contain an extra IO bridge component. These IOB0 & IOB1 components are 60 // contain an extra IO bridge component and two DSPIN local-xbar to multiplex 61 // the MEMC and IOB access to RAM network. These IOB0 & IOB1 components are 63 62 // connected to the three networks (INT, RAM, IOX). 64 63 // … … 86 85 // - NB_PROCS_MAX : number of processors per cluster (up to 8) 87 86 // - NB_DMA_CHANNELS : number of DMA channels per cluster (>= NB_PROCS_MAX) 88 // - NB_TTY_CHANNELS : number of TTY channels in I/O network (up to 16) 89 // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) 90 // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) 87 // - NB_TXT_CHANNELS : number of TTY channels in I/O network (up to 16) 88 // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 4) 91 89 // - FBUF_X_SIZE : width of frame buffer (pixels) 92 90 // - FBUF_Y_SIZE : heigth of frame buffer (lines) 93 // - XCU_NB_HWI : number of XCU HWIs (>= NB_PROCS_MAX + 1)94 // - XCU_NB_PTI : number of XCU PTIs (>= NB_PROCS_MAX)95 // - XCU_NB_WTI : number of XCU WTIs (>= 4*NB_PROCS_MAX)96 // - XCU_NB_OUT : number of XCU output IRQs (>= 4*NB_PROCS_MAX)91 // - ICU_NB_HWI : number of ICU HWIs (>= NB_PROCS_MAX + 1) 92 // - ICU_NB_PTI : number of ICU PTIs (>= NB_PROCS_MAX) 93 // - ICU_NB_WTI : number of ICU WTIs (>= 4*NB_PROCS_MAX) 94 // - ICU_NB_OUT : number of ICU output IRQs (>= 4*NB_PROCS_MAX) 97 95 // - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC) 98 96 // … … 119 117 // |X_ID|Y_ID| L_ID | 120 118 // | 4 | 4 | 6 | 119 // 120 // The NIC controler has one VCI target port, and one VCI initiator port, 121 // but it uses two different LOCAL_SRCID values to distinguish TX and TX 122 // transactions, because there is not enough bits in 4 bits TRDID field. 121 123 ///////////////////////////////////////////////////////////////////////// 122 124 … … 132 134 #include "mapping_table.h" 133 135 134 135 136 136 #include "tsar_iob_cluster.h" 137 137 #include "vci_chbuf_dma.h" 138 138 #include "vci_multi_tty.h" 139 #include "vci_m ulti_nic.h"139 #include "vci_master_nic.h" 140 140 #include "vci_simple_rom.h" 141 141 #include "vci_multi_ahci.h" … … 229 229 #define MEMC_SETS 256 230 230 231 #define MNIC_MAC_4 0x33445566 // 32 LSB bits 232 #define MNIC_MAC_2 0X1122 // 16 MSB bits 233 231 234 #define L1_IWAYS 4 232 235 #define L1_ISETS 64 … … 264 267 // All initiators are in the same indexing space (14 bits). 265 268 // The SRCID is structured in two fields: 266 // - The 8 MSB bits define the cluster index (left aligned)269 // - The 8 MSB bits define the cluster index. 267 270 // - The 6 LSB bits define the local index. 268 271 // Two different initiators cannot have the same SRCID, but a given … … 285 288 #define IOBX_LOCAL_SRCID 0x9 286 289 #define MEMC_LOCAL_SRCID 0xA 287 #define CDMA_LOCAL_SRCID 0xB288 290 #define DISK_LOCAL_SRCID 0xC 289 291 #define IOPI_LOCAL_SRCID 0xD 292 #define MNRX_LOCAL_SRCID 0xE // NIC_RX transactions 293 #define MNTX_LOCAL_SRCID 0xF // NIC_TX transactions 290 294 291 295 /////////////////////////////////////////////////////////////////////// … … 318 322 #define IOX_DISK_TGT_ID 1 319 323 #define IOX_MNIC_TGT_ID 2 320 #define IOX_CDMA_TGT_ID 3 321 #define IOX_BROM_TGT_ID 4 322 #define IOX_MTTY_TGT_ID 5 323 #define IOX_IOPI_TGT_ID 6 324 #define IOX_IOB0_TGT_ID 7 325 #define IOX_IOB1_TGT_ID 8 324 #define IOX_BROM_TGT_ID 3 325 #define IOX_MTTY_TGT_ID 4 326 #define IOX_IOPI_TGT_ID 5 327 #define IOX_IOB0_TGT_ID 6 328 #define IOX_IOB1_TGT_ID 7 326 329 327 330 #define IOX_DISK_INI_ID 0 328 #define IOX_ CDMA_INI_ID 1329 #define IOX_ IOPI_INI_ID 2331 #define IOX_IOPI_INI_ID 1 332 #define IOX_MNIC_INI_ID 2 330 333 #define IOX_IOB0_INI_ID 3 331 334 #define IOX_IOB1_INI_ID 4 … … 454 457 "Error in tsar_generic_iob : NB_PROCS_MAX parameter cannot be larger than 8" ); 455 458 456 assert( ( XCU_NB_HWI > NB_PROCS_MAX) and457 "Error in tsar_generic_iob : XCU_NB_HWI must be larger than NB_PROCS_MAX" );458 459 assert( ( XCU_NB_PTI >= NB_PROCS_MAX) and460 "Error in tsar_generic_iob : XCU_NB_PTI cannot be smaller than NB_PROCS_MAX" );461 462 assert( ( XCU_NB_WTI >= 4*NB_PROCS_MAX) and463 "Error in tsar_generic_iob : XCU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" );464 465 assert( ( XCU_NB_OUT >= 4*NB_PROCS_MAX) and466 "Error in tsar_generic_iob : XCU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" );459 assert( (ICU_NB_HWI > NB_PROCS_MAX) and 460 "Error in tsar_generic_iob : ICU_NB_HWI cannot be smaller than NB_PROCS_MAX" ); 461 462 assert( (ICU_NB_PTI >= NB_PROCS_MAX) and 463 "Error in tsar_generic_iob : ICU_NB_PTI cannot be smaller than NB_PROCS_MAX" ); 464 465 assert( (ICU_NB_WTI >= 4*NB_PROCS_MAX) and 466 "Error in tsar_generic_iob : ICU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" ); 467 468 assert( (ICU_NB_OUT >= 4*NB_PROCS_MAX) and 469 "Error in tsar_generic_iob : ICU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" ); 467 470 468 assert( (NB_TTY_CHANNELS >= 1) and (NB_TTY_CHANNELS <= 16) and 469 "Error in tsar_generic_iob : NB_TTY_CHANNELS parameter cannot be larger than 16" ); 470 471 assert( (NB_NIC_CHANNELS <= 2) and 472 "Error in tsar_generic_iob : NB_NIC_CHANNELS parameter cannot be larger than 2" ); 473 474 assert( (NB_CMA_CHANNELS <= 4) and 475 "Error in tsar_generic_iob : NB_CMA_CHANNELS parameter cannot be larger than 4" ); 471 assert( (NB_TXT_CHANNELS >= 1) and (NB_TXT_CHANNELS <= 16) and 472 "Error in tsar_generic_iob : NB_TXT_CHANNELS parameter cannot be larger than 16" ); 473 474 assert( (NB_NIC_CHANNELS <= 4) and 475 "Error in tsar_generic_iob : NB_NIC_CHANNELS parameter cannot be larger than 4" ); 476 476 477 477 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and … … 488 488 << " - YMAX = " << YMAX << std::endl 489 489 << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl 490 << " - NB_T TY_CHANNELS = " << NB_TTY_CHANNELS << std::endl490 << " - NB_TXT_CHANNELS = " << NB_TXT_CHANNELS << std::endl 491 491 << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl 492 << " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl493 492 << " - MEMC_WAYS = " << MEMC_WAYS << std::endl 494 493 << " - MEMC_SETS = " << MEMC_SETS << std::endl … … 568 567 std::ostringstream sxicu; 569 568 sxicu << "int_seg_xicu_" << x << "_" << y; 570 maptab_int.add(Segment(sxicu.str(), SEG_ XCU_BASE+offset, SEG_XCU_SIZE,569 maptab_int.add(Segment(sxicu.str(), SEG_ICU_BASE+offset, SEG_ICU_SIZE, 571 570 IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); 572 571 … … 587 586 std::ostringstream stty; 588 587 stty << "int_seg_mtty_" << x << "_" << y; 589 maptab_int.add(Segment(stty.str(), SEG_T TY_BASE+offset, SEG_TTY_SIZE,588 maptab_int.add(Segment(stty.str(), SEG_TXT_BASE+offset, SEG_TXT_SIZE, 590 589 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 591 590 … … 609 608 maptab_int.add(Segment(srom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, 610 609 IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); 611 612 std::ostringstream sdma;613 sdma << "int_seg_cdma_" << x << "_" << y;614 maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE,615 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable));616 610 617 611 std::ostringstream spic; … … 669 663 // This define the mapping between the initiators SRCID 670 664 // and the port index on the RAM local interconnect. 671 // External initiator have two alias SRCID (iob0 / iob1) 672 673 maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), 674 IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); 675 676 maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), 677 IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); 665 // This routing table is used to route the response to the 666 // relevant initiator: external peripherals transactions 667 // use IOBX port, while MEMC transactions use MEMC port. 678 668 679 669 maptab_ram.srcid_map( IntTab( cluster_iob0, DISK_LOCAL_SRCID ), … … 689 679 IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); 690 680 681 maptab_ram.srcid_map( IntTab( cluster_iob0, MNRX_LOCAL_SRCID ), 682 IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); 683 684 maptab_ram.srcid_map( IntTab( cluster_iob1, MNRX_LOCAL_SRCID ), 685 IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); 686 687 maptab_ram.srcid_map( IntTab( cluster_iob0, MNTX_LOCAL_SRCID ), 688 IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); 689 690 maptab_ram.srcid_map( IntTab( cluster_iob1, MNTX_LOCAL_SRCID ), 691 IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); 692 691 693 maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), 692 694 IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); … … 699 701 /////////////////////////////////////////////////////////////////////// 700 702 // IOX network mapping table 701 // - two levels address decoding for commands (9, 7) bits703 // - two levels address decoding for commands 702 704 // - two levels srcid decoding for responses 703 // - 5 initiators (IOB0, IOB1, DISK, CDMA, IOPI)704 // - 9 targets (IOB0, IOB1, DISK, CDMA, MTTY, FBUF, BROM, MNIC, IOPI)705 // - 5 initiators (IOB0, IOB1, DISK, MNIC, IOPI) 706 // - 8 targets (IOB0, IOB1, DISK, MTTY, FBUF, BROM, MNIC, IOPI) 705 707 // 706 708 // Address bit 32 is used to determine if a command must be routed to … … 720 722 << (vci_address_width - x_width - y_width); 721 723 722 maptab_iox.add(Segment("iox_seg_mtty_0", SEG_T TY_BASE + iob0_base, SEG_TTY_SIZE,724 maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TXT_BASE + iob0_base, SEG_TXT_SIZE, 723 725 IntTab(0, IOX_MTTY_TGT_ID), false)); 724 726 maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, … … 728 730 maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, 729 731 IntTab(0, IOX_MNIC_TGT_ID), false)); 730 maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE,731 IntTab(0, IOX_CDMA_TGT_ID), false));732 732 maptab_iox.add(Segment("iox_seg_brom_0", SEG_ROM_BASE + iob0_base, SEG_ROM_SIZE, 733 733 IntTab(0, IOX_BROM_TGT_ID), false)); … … 740 740 << (vci_address_width - x_width - y_width); 741 741 742 maptab_iox.add(Segment("iox_seg_mtty_1", SEG_T TY_BASE + iob1_base, SEG_TTY_SIZE,742 maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TXT_BASE + iob1_base, SEG_TXT_SIZE, 743 743 IntTab(0, IOX_MTTY_TGT_ID), false)); 744 744 maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, … … 748 748 maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, 749 749 IntTab(0, IOX_MNIC_TGT_ID), false)); 750 maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE,751 IntTab(0, IOX_CDMA_TGT_ID), false));752 750 maptab_iox.add(Segment("iox_seg_brom_1", SEG_ROM_BASE + iob1_base, SEG_ROM_SIZE, 753 751 IntTab(0, IOX_BROM_TGT_ID), false)); … … 770 768 << (vci_address_width-x_width-y_width); 771 769 772 const uint64_t xicu_base = SEG_ XCU_BASE + offset;770 const uint64_t xicu_base = SEG_ICU_BASE + offset; 773 771 774 772 if ( (y & 0x1) == 0 ) // use IOB0 … … 776 774 std::ostringstream sxcu0; 777 775 sxcu0 << "iox_seg_xcu0_" << x << "_" << y; 778 maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_ XCU_SIZE,776 maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_ICU_SIZE, 779 777 IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); 780 778 781 779 std::ostringstream siob0; 782 780 siob0 << "iox_seg_ram0_" << x << "_" << y; 783 maptab_iox.add(Segment(siob0.str(), offset, SEG_ XCU_BASE,781 maptab_iox.add(Segment(siob0.str(), offset, SEG_ICU_BASE, 784 782 IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); 785 783 } … … 788 786 std::ostringstream sxcu1; 789 787 sxcu1 << "iox_seg_xcu1_" << x << "_" << y; 790 maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_ XCU_SIZE,788 maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_ICU_SIZE, 791 789 IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); 792 790 793 791 std::ostringstream siob1; 794 792 siob1 << "iox_seg_ram1_" << x << "_" << y; 795 maptab_iox.add(Segment(siob1.str(), offset, SEG_ XCU_BASE,793 maptab_iox.add(Segment(siob1.str(), offset, SEG_ICU_BASE, 796 794 IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); 797 795 } … … 800 798 801 799 // This define the mapping between the external initiators (SRCID) 802 // and the port index on the IOX local interconnect. 803 804 maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , 805 IntTab( 0, IOX_CDMA_INI_ID ) ); 800 // and the initiator port index on the IOX local interconnect. 801 806 802 maptab_iox.srcid_map( IntTab( 0, DISK_LOCAL_SRCID ) , 807 803 IntTab( 0, IOX_DISK_INI_ID ) ); 804 808 805 maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , 809 806 IntTab( 0, IOX_IOPI_INI_ID ) ); 807 810 808 maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , 811 809 IntTab( 0, IOX_IOB0_INI_ID ) ); 810 811 maptab_iox.srcid_map( IntTab( 0, MNRX_LOCAL_SRCID ) , 812 IntTab( 0, IOX_MNIC_INI_ID ) ); 813 814 maptab_iox.srcid_map( IntTab( 0, MNTX_LOCAL_SRCID ) , 815 IntTab( 0, IOX_MNIC_INI_ID ) ); 812 816 813 817 if ( cluster_iob0 != cluster_iob1 ) … … 828 832 sc_signal<bool> signal_irq_false; 829 833 sc_signal<bool> signal_irq_disk; 830 sc_signal<bool> signal_irq_mtty_rx[NB_T TY_CHANNELS];834 sc_signal<bool> signal_irq_mtty_rx[NB_TXT_CHANNELS]; 831 835 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; 832 836 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; 833 sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];834 837 835 838 // VCI signals for IOX network … … 837 840 VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); 838 841 VciSignals<vci_param_ext> signal_vci_ini_disk("signal_vci_ini_disk"); 839 VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma");840 842 VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); 843 VciSignals<vci_param_ext> signal_vci_ini_mnic("signal_vci_ini_mnic"); 841 844 842 845 VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); … … 847 850 VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); 848 851 VciSignals<vci_param_ext> signal_vci_tgt_disk("signal_vci_tgt_disk"); 849 VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma");850 852 VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_tgt_iopi"); 851 853 … … 1006 1008 1007 1009 const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; 1008 const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 9 : 8;1010 const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 8 : 7; 1009 1011 1010 1012 // IOX network … … 1020 1022 maptab_iox, 1021 1023 loader ); 1022 // Network Controller 1023 VciMultiNic<vci_param_ext>* mnic; 1024 mnic = new VciMultiNic<vci_param_ext>( "mnic", 1025 IntTab(0, IOX_MNIC_TGT_ID), 1026 maptab_iox, 1027 NB_NIC_CHANNELS, 1028 0, // mac_4 address 1029 0, // mac_2 address 1030 1, // NIC_MODE_SYNTHESIS 1031 12); // INTER_FRAME_GAP 1024 // Ethernet Controller 1025 VciMasterNic<vci_param_ext>* mnic; 1026 mnic = new VciMasterNic<vci_param_ext>( "mnic", 1027 maptab_iox, 1028 IntTab(0, MNRX_LOCAL_SRCID), 1029 IntTab(0, MNTX_LOCAL_SRCID), 1030 IntTab(0, IOX_MNIC_TGT_ID), 1031 NB_NIC_CHANNELS, 1032 64, // burst length 1033 MNIC_MAC_4, // default MAC address (LSB) 1034 MNIC_MAC_2, // default MAC address (MSB) 1035 1, // NIC_MODE_SYNTHESIS 1036 12); // INTER_FRAME_GAP 1032 1037 1033 1038 // Frame Buffer … … 1079 1084 #endif 1080 1085 1081 // Chained Buffer DMA controller1082 VciChbufDma<vci_param_ext>* cdma;1083 cdma = new VciChbufDma<vci_param_ext>( "cdma",1084 maptab_iox,1085 IntTab(0, CDMA_LOCAL_SRCID),1086 IntTab(0, IOX_CDMA_TGT_ID),1087 64, // burst size (bytes)1088 NB_CMA_CHANNELS,1089 4 ); // number of pipelined bursts1090 1091 1086 // Multi-TTY controller 1092 1087 std::vector<std::string> vect_names; 1093 for( size_t tid = 0 ; tid < NB_T TY_CHANNELS ; tid++ )1088 for( size_t tid = 0 ; tid < NB_TXT_CHANNELS ; tid++ ) 1094 1089 { 1095 1090 std::ostringstream term_name; … … 1204 1199 L1_DSETS, 1205 1200 XRAM_LATENCY, 1206 XCU_NB_HWI,1207 XCU_NB_PTI,1208 XCU_NB_WTI,1209 XCU_NB_OUT,1201 ICU_NB_HWI, 1202 ICU_NB_PTI, 1203 ICU_NB_WTI, 1204 ICU_NB_OUT, 1210 1205 1211 1206 coproc_type, … … 1240 1235 iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); 1241 1236 iox_network->p_to_ini[IOX_DISK_INI_ID] (signal_vci_ini_disk); 1242 iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma);1243 1237 iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); 1238 iox_network->p_to_ini[IOX_MNIC_INI_ID] (signal_vci_ini_mnic); 1244 1239 1245 1240 iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); … … 1249 1244 iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); 1250 1245 iox_network->p_to_tgt[IOX_DISK_TGT_ID] (signal_vci_tgt_disk); 1251 iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma);1252 1246 iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); 1253 1247 … … 1333 1327 mnic->p_clk (signal_clk); 1334 1328 mnic->p_resetn (signal_resetn); 1335 mnic->p_vci (signal_vci_tgt_mnic); 1329 mnic->p_vci_tgt (signal_vci_tgt_mnic); 1330 mnic->p_vci_ini (signal_vci_ini_mnic); 1336 1331 for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) 1337 1332 { … … 1353 1348 mtty->p_resetn (signal_resetn); 1354 1349 mtty->p_vci (signal_vci_tgt_mtty); 1355 for ( size_t i=0 ; i<NB_T TY_CHANNELS ; i++ )1350 for ( size_t i=0 ; i<NB_TXT_CHANNELS ; i++ ) 1356 1351 { 1357 1352 mtty->p_irq[i] (signal_irq_mtty_rx[i]); 1358 1353 } 1359 1354 std::cout << " - MTTY connected" << std::endl; 1360 1361 // CDMA connexion1362 cdma->p_clk (signal_clk);1363 cdma->p_resetn (signal_resetn);1364 cdma->p_vci_target (signal_vci_tgt_cdma);1365 cdma->p_vci_initiator (signal_vci_ini_cdma);1366 for ( size_t i=0 ; i<(NB_CMA_CHANNELS) ; i++)1367 {1368 cdma->p_irq[i] (signal_irq_cdma[i]);1369 }1370 1371 std::cout << " - CDMA connected" << std::endl;1372 1355 1373 1356 // IOPI connexion … … 1379 1362 { 1380 1363 if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); 1381 else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false);1382 else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]);1383 1364 else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); 1384 else if(i < 4+NB_ CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]);1385 else if(i < 8)iopi->p_hwi[i] (signal_irq_false);1386 else if(i < 9)iopi->p_hwi[i] (signal_irq_disk);1365 else if(i < 4+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-4]); 1366 else if(i < 12) iopi->p_hwi[i] (signal_irq_false); 1367 else if(i < 13) iopi->p_hwi[i] (signal_irq_disk); 1387 1368 else if(i < 16) iopi->p_hwi[i] (signal_irq_false); 1388 else if(i < 16+NB_T TY_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]);1369 else if(i < 16+NB_TXT_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); 1389 1370 else iopi->p_hwi[i] (signal_irq_false); 1390 1371 } … … 1688 1669 1689 1670 // Monitor a specific address for one L2 cache (single word if second argument true) 1690 // clusters[0][0]->memc->cache_monitor( 0x00 FF8000ULL, false);1671 // clusters[0][0]->memc->cache_monitor( 0x00007000ULL, false ); 1691 1672 1692 1673 // Monitor a specific address for one XRAM 1693 // clusters[0][0]->xram->start_monitor( 0x 600800ULL , 64);1674 // clusters[0][0]->xram->start_monitor( 0x00007000ULL , 64); 1694 1675 1695 1676 if ( debug_ok and (n > debug_from) ) … … 1717 1698 1718 1699 // coprocessor in cluster(x,y) 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1700 // clusters[x][y]->mwmr->print_trace(); 1701 // std::ostringstream mwmr_tgt_signame; 1702 // mwmr_tgt_signame << "[SIG]MWMR_TGT_" << x << "_" << y; 1703 // clusters[x][y]->signal_int_vci_tgt_mwmr.print_trace(mwmr_tgt_signame.str()); 1704 // std::ostringstream mwmr_ini_signame; 1705 // mwmr_ini_signame << "[SIG]MWMR_INI_" << x << "_" << y; 1706 // clusters[x][y]->signal_int_vci_ini_mwmr.print_trace(mwmr_ini_signame.str()); 1707 // if ( USE_MWR_CPY ) clusters[x][y]->cpy->print_trace(); 1708 // if ( USE_MWR_DCT ) clusters[x][y]->dct->print_trace(); 1709 // if ( USE_MWR_GCD ) clusters[x][y]->gcd->print_trace(); 1729 1710 1730 1711 // local interrupts in cluster(x,y) … … 1766 1747 // clusters[x][y]->ram_router_cmd->print_trace(); 1767 1748 // clusters[x][y]->ram_router_rsp->print_trace(); 1749 1750 // clusters[x][y]->ram_xbar_cmd->print_trace(); 1751 // clusters[x][y]->ram_xbar_rsp->print_trace(); 1768 1752 } 1769 1753 … … 1778 1762 // signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); 1779 1763 1780 cdma->print_trace();1781 signal_vci_tgt_cdma.print_trace("[SIG]CDMA_TGT");1782 signal_vci_ini_cdma.print_trace("[SIG]CDMA_INI");1783 1784 1764 // brom->print_trace(); 1785 1765 // signal_vci_tgt_brom.print_trace("[SIG]BROM_TGT"); … … 1796 1776 #endif 1797 1777 1798 // mnic->print_trace( 0x000 ); 1799 // signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); 1800 1801 fbuf->print_trace(); 1802 signal_vci_tgt_fbuf.print_trace("[SIG]FBUF_TGT"); 1778 mnic->print_trace( 0 ); 1779 signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); 1780 signal_vci_ini_mnic.print_trace("[SIG]MNIC_INI"); 1781 1782 // fbuf->print_trace(); 1783 // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF_TGT"); 1803 1784 1804 1785 // iopi->print_trace(); -
trunk/platforms/tsar_generic_iob/top.desc
r1002 r1050 61 61 62 62 # NIC 63 Uses('caba:vci_m ulti_nic',63 Uses('caba:vci_master_nic', 64 64 cell_size = vci_cell_size_ext), 65 65 -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r1030 r1050 198 198 DspinRouter<dspin_ram_rsp_width>* ram_router_rsp; 199 199 200 // IO Network Components (not instanciated in all clusters) 201 200 202 DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd; 201 203 DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp; 202 203 204 // IO Network Components (not instanciated in all clusters)205 204 206 205 VciIoBridge<vci_param_int, -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r1034 r1050 340 340 nb_procs, // number of local targets 341 341 1, 1, // fifo depths 342 true, // CMD342 true, // pseudo CMD 343 343 false, // no routing table 344 false); // broadcast344 false); // no broadcast 345 345 346 346 //////////// DSPIN INT_CMD ROUTER //////////////////////////////////////////// … … 470 470 2, 2, // in fifo, out fifo depths 471 471 true, // is cmd ? 472 false, // use routing table ?473 false); // support broadcast ?472 false, // no routing table 473 false); // no broadcast 474 474 475 475 //////////// DSPIN RAM_RSP LOCAL_XBAR /////////////////////////////////// … … 484 484 2, 2, // in fifo, out fifo depths 485 485 false, // is cmd ? 486 true, // use routing table ?487 false); // support broadcast ?486 true, // use routing table 487 false); // no broadcast 488 488 489 489 } // end if IO
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