Changeset 1051
- Timestamp:
- Apr 11, 2017, 11:50:57 PM (8 years ago)
- Location:
- trunk/platforms/tsar_generic_iob
- Files:
-
- 5 edited
-
arch_info.py (modified) (7 diffs)
-
top.cpp (modified) (14 diffs)
-
tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (modified) (2 diffs)
-
tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (5 diffs)
-
tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/arch_info.py
r1050 r1051 31 31 # - fbf_width : frame_buffer width = frame_buffer heigth 32 32 # - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' 33 # - mwr_type : can be 'MWR_GCD','MWR_DCT','MWR_CPY','NONE'34 33 # - io_cxy : IO cluster identifier 35 34 # - boot_cxy : boot cluster identifier … … 53 52 fbf_width = 128, 54 53 ioc_type = 'IOC_BDV', 55 mwr_type = 'MWR_CPY',56 54 io_cxy = 0, 57 55 boot_cxy = 0, … … 83 81 assert( ioc_type in ['IOC_BDV','IOC_HBA','IOC_SDC','IOC_SPI','IOC_RDK'] ) 84 82 85 assert( mwr_type in ['MWR_GCD','MWR_DCT','MWR_CPY'] )86 87 83 assert( (io_cxy == 0) or (io_cxy == ((x_size-1)<<y_width) + (y_size-1)) ) 88 84 … … 103 99 xcu_size = 0x1000 # 4 Kbytes 104 100 105 mwr_base = 0x00B1000000106 mwr_size = 0x1000 # 4 Kbytes101 dma_base = 0x00B1000000 102 dma_size = 0x1000 # 4 Kbytes 107 103 108 104 mmc_base = 0x00B2000000 … … 170 166 size = xcu_size, 171 167 channels = 1, 172 arg0 = 16, 173 arg1 = 16, 174 arg2 = 16, 175 arg3 = 16 ) 168 arg0 = 16, # number of HWIs 169 arg1 = 16, # number of WTIs 170 arg2 = 16, # number of PTIs 171 arg3 = 16 ) # number of output IRQs 176 172 177 173 mmc = archi.addDevice( ptype = 'MMC_TSR', … … 181 177 archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc ) 182 178 183 if ( mwr_type == 'MWR_GCD' ): 184 mwr = archi.addDevice( ptype = 'MWR_GCD', 185 base = mwr_base + offset, 186 size = mwr_size, 187 arg0 = 2, 188 arg1 = 1, 189 arg2 = 1, 190 arg3 = 0 ) 191 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 192 193 if ( mwr_type == 'MWR_DCT' ): 194 mwr = archi.addDevice( ptype = 'MWR_DCT', 195 base = mwr_base + offset, 196 size = mwr_size, 197 arg0 = 1, 198 arg1 = 1, 199 arg2 = 1, 200 arg3 = 0 ) 201 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 202 203 if ( mwr_type == 'MWR_CPY' ): 204 mwr = archi.addDevice( ptype = 'MWR_CPY', 205 base = mwr_base + offset, 206 size = mwr_size, 207 arg0 = 1, 208 arg1 = 1, 209 arg2 = 1, 210 arg3 = 0 ) 211 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 179 dma = archi.addDevice( ptype = 'DMA_SCL', 180 base = dma_base + offset, 181 size = dma_size, 182 channels = nb_cores ) 183 184 archi.addIrq( dstdev = xcu, port = 1, srcdev = dma, channel = 0 ) 185 archi.addIrq( dstdev = xcu, port = 2, srcdev = dma, channel = 1 ) 186 archi.addIrq( dstdev = xcu, port = 3, srcdev = dma, channel = 2 ) 187 archi.addIrq( dstdev = xcu, port = 4, srcdev = dma, channel = 3 ) 212 188 213 189 # define external devices 214 190 if( cxy == io_cxy ): 191 192 pic = archi.addDevice( ptype ='PIC_TSR', 193 base = pic_base + offset, 194 size = pic_size, 195 arg0 = 32 ) # number of input IRQs 215 196 216 197 iob = archi.addDevice( ptype = 'IOB_TSR', … … 241 222 base = rom_base + offset, 242 223 size = rom_size ) 243 244 pic = archi.addDevice( ptype ='PIC_TSR',245 base = pic_base + offset,246 size = pic_size,247 arg0 = 32 )248 224 249 225 archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, channel = 0 , is_rx = True ) -
trunk/platforms/tsar_generic_iob/top.cpp
r1050 r1051 50 50 // - One L2 cache controller 51 51 // - One XICU component, 52 // - One - optional - single channel DMA controler, 53 // - One - optional - hardware coprocessor 52 // - One multi channels DMA controler (number of channels is defined by nprocs) 54 53 // The XICU component is mainly used to handle WTI IRQs, as at most 55 // 2HWI IRQs are connected to XICU in each cluster:54 // (nprocs + 1) HWI IRQs are connected to XICU in each cluster: 56 55 // - IRQ_IN[0] : MMC 57 // - IRQ_IN[1 ] : MWR56 // - IRQ_IN[1 to nprocs] : DMA 58 57 // 59 58 // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) … … 151 150 152 151 ////////////////////////////////////////////////////////////////// 153 // Coprocessor type (must be replicated in tsar_iob_cluster)154 //////////////////////////////////////////////////////////////////155 156 #define MWR_COPROC_CPY 0157 #define MWR_COPROC_DCT 1158 #define MWR_COPROC_GCD 2159 160 //////////////////////////////////////////////////////////////////161 152 // Virtual disk selection => OS selection 162 153 ////////////////////////////////////////////////////////////////// … … 271 262 // Two different initiators cannot have the same SRCID, but a given 272 263 // initiator can have two alias SRCIDs: 273 // - Internal initiators (procs, m wmr) are replicated in all clusters,264 // - Internal initiators (procs, mdma) are replicated in all clusters, 274 265 // and each initiator has one single SRCID. 275 266 // - External initiators (disk, cdma) are not replicated, but can be … … 285 276 286 277 #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 287 #define M WMR_LOCAL_SRCID 0x8278 #define MDMA_LOCAL_SRCID 0x8 288 279 #define IOBX_LOCAL_SRCID 0x9 289 280 #define MEMC_LOCAL_SRCID 0xA … … 299 290 #define INT_MEMC_TGT_ID 0 300 291 #define INT_XICU_TGT_ID 1 301 #define INT_M WMR_TGT_ID 2292 #define INT_MDMA_TGT_ID 2 302 293 #define INT_IOBX_TGT_ID 3 303 294 304 295 #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) 305 #define INT_M WMR_INI_ID (NB_PROCS_MAX)296 #define INT_MDMA_INI_ID (NB_PROCS_MAX) 306 297 #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) 307 298 … … 478 469 "Error in tsar_generic_iob : You must have X_WIDTH == Y_WIDTH == 4"); 479 470 480 assert( ((USE_MWR_CPY + USE_MWR_GCD + USE_MWR_DCT) == 1) and481 "Error in tsar_generic_iob : No MWR coprocessor found in hard_config.h");482 483 471 assert( ((USE_IOC_HBA + USE_IOC_BDV + USE_IOC_SDC) == 1) and 484 472 "Error in tsar_generic_iob : NoIOC controller found in hard_config.h"); … … 536 524 // - two levels address decoding for commands 537 525 // - two levels srcid decoding for responses 538 // - NB_PROCS_MAX + 2 (M WMR, IOBX) local initiators per cluster539 // - 4 local targets (MEMC, XICU, M WMR, IOBX) per cluster526 // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster 527 // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster 540 528 ///////////////////////////////////////////////////////////////////// 541 529 MappingTable maptab_int( vci_address_width, … … 570 558 IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); 571 559 572 std::ostringstream sm wmr;573 sm wmr << "int_seg_mwmr_" << x << "_" << y;574 maptab_int.add(Segment(sm wmr.str(), SEG_MWR_BASE+offset, SEG_MWR_SIZE,575 IntTab(cluster(x,y), INT_M WMR_TGT_ID), not cacheable));560 std::ostringstream smdma; 561 smdma << "int_seg_mdma_" << x << "_" << y; 562 maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, 563 IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); 576 564 577 565 // the following segments are only defined in cluster_iob0 or in cluster_iob1 … … 618 606 // and the port index on the local interconnect. 619 607 620 maptab_int.srcid_map( IntTab( cluster(x,y), M WMR_LOCAL_SRCID ),621 IntTab( cluster(x,y), INT_M WMR_INI_ID ) );608 maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), 609 IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); 622 610 623 611 maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), … … 1114 1102 dspin_ram_rsp_width>* clusters[XMAX][YMAX]; 1115 1103 1116 unsigned int coproc_type; 1117 if ( USE_MWR_CPY ) coproc_type = MWR_COPROC_CPY; 1118 if ( USE_MWR_DCT ) coproc_type = MWR_COPROC_DCT; 1119 if ( USE_MWR_GCD ) coproc_type = MWR_COPROC_GCD; 1104 unsigned int coproc_type = 0; 1120 1105 1121 1106 #if USE_OPENMP … … 1176 1161 INT_MEMC_TGT_ID, 1177 1162 INT_XICU_TGT_ID, 1178 INT_M WMR_TGT_ID,1163 INT_MDMA_TGT_ID, 1179 1164 INT_IOBX_TGT_ID, 1180 1165 1181 1166 INT_PROC_INI_ID, 1182 INT_M WMR_INI_ID,1167 INT_MDMA_INI_ID, 1183 1168 INT_IOBX_INI_ID, 1184 1169 … … 1692 1677 clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); 1693 1678 1679 // XICU 1694 1680 clusters[x][y]->xicu->print_trace(1); 1695 1681 std::ostringstream xicu_signame; … … 1697 1683 clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); 1698 1684 1699 // coprocessor in cluster(x,y) 1700 // clusters[x][y]->mwmr->print_trace(); 1701 // std::ostringstream mwmr_tgt_signame; 1702 // mwmr_tgt_signame << "[SIG]MWMR_TGT_" << x << "_" << y; 1703 // clusters[x][y]->signal_int_vci_tgt_mwmr.print_trace(mwmr_tgt_signame.str()); 1704 // std::ostringstream mwmr_ini_signame; 1705 // mwmr_ini_signame << "[SIG]MWMR_INI_" << x << "_" << y; 1706 // clusters[x][y]->signal_int_vci_ini_mwmr.print_trace(mwmr_ini_signame.str()); 1707 // if ( USE_MWR_CPY ) clusters[x][y]->cpy->print_trace(); 1708 // if ( USE_MWR_DCT ) clusters[x][y]->dct->print_trace(); 1709 // if ( USE_MWR_GCD ) clusters[x][y]->gcd->print_trace(); 1685 // MDMA 1686 // clusters[x][y]->mdma->print_trace(); 1687 // std::ostringstream mdma_tgt_signame; 1688 // mdma_tgt_signame << "[SIG]MDMA_TGT_" << x << "_" << y; 1689 // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_tgt_signame.str()); 1690 // std::ostringstream mdma_ini_signame; 1691 // mdma_ini_signame << "[SIG]MDMA_INI_" << x << "_" << y; 1692 // clusters[x][y]->signal_int_vci_ini_mdma.print_trace(mdma_ini_signame.str()); 1710 1693 1711 1694 // local interrupts in cluster(x,y) … … 1714 1697 << " ACTIVE" << std::endl; 1715 1698 1716 if( clusters[x][y]->signal_irq_mwmr.read() ) 1717 std::cout << "### IRQ_MWR_" << std::dec << x << "_" << y 1718 << " ACTIVE" << std::endl; 1719 1720 for ( size_t c = 0 ; c < NB_PROCS_MAX ; c++ ) 1699 for( size_t i = 0 ; i < NB_PROCS_MAX ; i++ ) 1721 1700 { 1722 if( clusters[x][y]->signal_proc_it[c<<2].read() ) 1723 std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << c 1701 if( clusters[x][y]->signal_irq_mdma[i].read() ) 1702 std::cout << "### IRQ_DMA_" << std::dec << x << "_" << y << "_" << i 1703 << " ACTIVE" << std::endl; 1704 1705 if( clusters[x][y]->signal_proc_it[i<<2].read() ) 1706 std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << i 1724 1707 << " ACTIVE" << std::endl; 1725 1708 } -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
r1002 r1051 29 29 Uses('common:iss2'), 30 30 Uses('common:elf_file_loader'), 31 Uses('caba:coproc_signals'),32 31 33 32 # internal network components … … 48 47 cell_size = parameter.Reference('vci_data_width_int')), 49 48 50 Uses('caba:vci_m wmr_dma',49 Uses('caba:vci_multi_dma', 51 50 cell_size = parameter.Reference('vci_data_width_int')), 52 53 Uses('caba:coproc_gcd'),54 Uses('caba:coproc_dct'),55 Uses('caba:coproc_cpy'),56 51 57 52 Uses('caba:vci_local_crossbar', -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r1050 r1051 27 27 #include "vci_dspin_target_wrapper.h" 28 28 #include "dspin_router.h" 29 #include "vci_m wmr_dma.h"29 #include "vci_multi_dma.h" 30 30 #include "vci_mem_cache.h" 31 31 #include "vci_cc_vcache_wrapper.h" 32 32 #include "vci_io_bridge.h" 33 #include "coproc_signals.h"34 #include "coproc_gcd.h"35 #include "coproc_dct.h"36 #include "coproc_cpy.h"37 33 38 34 namespace soclib { namespace caba { … … 80 76 sc_signal<bool> signal_false; 81 77 sc_signal<bool> signal_proc_it[32]; 82 sc_signal<bool> signal_irq_m wmr;78 sc_signal<bool> signal_irq_mdma[8]; 83 79 sc_signal<bool> signal_irq_memc; 84 80 85 // Coprocessor signals86 CoprocSignals<uint32_t,uint8_t> signal_to_coproc[8];87 CoprocSignals<uint32_t,uint8_t> signal_from_coproc[8];88 sc_signal<uint32_t> signal_config_coproc[8];89 sc_signal<uint32_t> signal_status_coproc[8];90 91 81 // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars 92 82 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; … … 107 97 // INT network VCI signals between VCI components and VCI local crossbar 108 98 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 109 VciSignals<vci_param_int> signal_int_vci_ini_m wmr;99 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 110 100 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 111 101 112 102 VciSignals<vci_param_int> signal_int_vci_tgt_memc; 113 103 VciSignals<vci_param_int> signal_int_vci_tgt_xicu; 114 VciSignals<vci_param_int> signal_int_vci_tgt_m wmr;104 VciSignals<vci_param_int> signal_int_vci_tgt_mdma; 115 105 VciSignals<vci_param_int> signal_int_vci_tgt_iobx; 116 106 … … 163 153 VciXicu<vci_param_int>* xicu; 164 154 165 VciMwmrDma<vci_param_int>* mwmr; 166 167 CoprocGcd* gcd; 168 CoprocDct* dct; 169 CoprocCpy* cpy; 155 VciMultiDma<vci_param_int>* mdma; 170 156 171 157 VciLocalCrossbar<vci_param_int>* int_xbar_d; … … 229 215 size_t int_memc_tgt_id, 230 216 size_t int_xicu_tgt_id, 231 size_t int_m wmr_tgt_id,217 size_t int_mdma_tgt_id, 232 218 size_t int_iobx_tgt_id, 233 219 size_t int_proc_ini_id, 234 size_t int_m wmr_ini_id,220 size_t int_mdma_ini_id, 235 221 size_t int_iobx_ini_id, 236 222 -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r1050 r1051 15 15 #include "../include/tsar_iob_cluster.h" 16 16 17 #define MWR_COPROC_CPY 018 #define MWR_COPROC_DCT 119 #define MWR_COPROC_GCD 220 21 17 #define tmpl(x) \ 22 18 template<typename vci_param_int , typename vci_param_ext,\ … … 51 47 size_t int_memc_tgt_id, // local index 52 48 size_t int_xicu_tgt_id, // local index 53 size_t int_m wmr_tgt_id, // local index49 size_t int_mdma_tgt_id, // local index 54 50 size_t int_iobx_tgt_id, // local index 55 51 56 52 size_t int_proc_ini_id, // local index 57 size_t int_m wmr_ini_id, // local index53 size_t int_mdma_ini_id, // local index 58 54 size_t int_iobx_ini_id, // local index 59 55 … … 62 58 size_t ram_iobx_ini_id, // local index 63 59 64 bool is_io, // is IO cluster ( IOB)?60 bool is_io, // is IO cluster ( 65 61 size_t iox_iobx_tgt_id, // local_index 66 62 size_t iox_iobx_ini_id, // local index … … 213 209 xcu_nb_out); // number of output IRQs 214 210 215 //////////// MWMR controller and COPROC //////////////////////////////////////// 216 std::ostringstream s_mwmr; 217 std::ostringstream s_copro; 218 s_mwmr << "mwmr_" << x_id << "_" << y_id; 219 220 if ( coproc_type == MWR_COPROC_CPY) 221 { 222 s_copro << "cpy_" << x_id << "_" << y_id; 223 cpy = new CoprocCpy( s_copro.str().c_str(), 64 ); // burst size 224 225 mwmr = new VciMwmrDma<vci_param_int>( 226 s_mwmr.str().c_str(), 211 //////////// MDMA ////////////////////////////////////////////////////////////// 212 std::ostringstream s_mdma; 213 s_mdma << "mdma_" << x_id << "_" << y_id; 214 mdma = new VciMultiDma<vci_param_int>( 215 s_mdma.str().c_str(), 227 216 mt_int, 228 IntTab(cluster_id, int_mwmr_ini_id), // SRCID 229 IntTab(cluster_id, int_mwmr_tgt_id), // TGTID 230 1, // nb to_coproc ports 231 1, // nb from_coproc ports 232 1, // nb config registers 233 0, // nb status registers 234 64 ); // burst size (bytes) 235 } 236 if ( coproc_type == MWR_COPROC_DCT ) 237 { 238 s_copro << "dct_" << x_id << "_" << y_id; 239 dct = new CoprocDct( s_copro.str().c_str(), 64 , 16 ); // burst size / latency 240 241 mwmr = new VciMwmrDma<vci_param_int>( 242 s_mwmr.str().c_str(), 243 mt_int, 244 IntTab(cluster_id, int_mwmr_ini_id), // SRCID 245 IntTab(cluster_id, int_mwmr_tgt_id), // TGTID 246 1, // nb to_coproc ports 247 1, // nb from_coproc ports 248 1, // nb config registers 249 0, // nb status registers 250 64 ); // burst size (bytes) 251 } 252 if ( coproc_type == MWR_COPROC_GCD ) 253 { 254 s_copro << "gcd_" << x_id << "_" << y_id; 255 gcd = new CoprocGcd( s_copro.str().c_str(), 64 ); // burst size 256 257 mwmr = new VciMwmrDma<vci_param_int>( 258 s_mwmr.str().c_str(), 259 mt_int, 260 IntTab(cluster_id, int_mwmr_ini_id), // SRCID 261 IntTab(cluster_id, int_mwmr_tgt_id), // TGTID 262 2, // nb to_coproc ports 263 1, // nb from_coproc ports 264 1, // nb config registers 265 0, // nb status registers 266 64 ); // burst size (bytes) 267 } 217 IntTab(cluster_id, int_mdma_ini_id), // SRCID 218 IntTab(cluster_id, int_mdma_tgt_id), // TGTID 219 64, // burst size 220 nb_procs ); // number of channels 268 221 269 222 /////////// VCI INT_CMD/RSP LOCAL_XBAR ////////////////////////////////////// … … 526 479 for ( size_t i=0 ; i < xcu_nb_hwi ; i++) 527 480 { 528 if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);529 else if ( i == 1 ) xicu->p_hwi[i] (signal_irq_mwmr);530 else xicu->p_hwi[i] (signal_false);481 if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); 482 else if ( i < (nb_procs+1) ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); 483 else xicu->p_hwi[i] (signal_false); 531 484 } 532 485 … … 566 519 std::cout << " - xram connected" << std::endl; 567 520 568 /////////////////////////////////// GCD coprocessor 569 if ( coproc_type == MWR_COPROC_GCD ) 570 { 571 gcd->p_clk (this->p_clk); 572 gcd->p_resetn (this->p_resetn); 573 gcd->p_opa (signal_to_coproc[0]); 574 gcd->p_opb (signal_to_coproc[1]); 575 gcd->p_res (signal_from_coproc[0]); 576 gcd->p_config (signal_config_coproc[0]); 577 578 mwmr->p_clk (this->p_clk); 579 mwmr->p_resetn (this->p_resetn); 580 mwmr->p_vci_target (signal_int_vci_tgt_mwmr); 581 mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); 582 mwmr->p_to_coproc[0] (signal_to_coproc[0]); 583 mwmr->p_to_coproc[1] (signal_to_coproc[1]); 584 mwmr->p_from_coproc[0] (signal_from_coproc[0]); 585 mwmr->p_config[0] (signal_config_coproc[0]); 586 mwmr->p_irq (signal_irq_mwmr); 587 } 588 589 /////////////////////////////////// DCT coprocessor 590 if ( coproc_type == MWR_COPROC_DCT ) 591 { 592 dct->p_clk (this->p_clk); 593 dct->p_resetn (this->p_resetn); 594 dct->p_in (signal_to_coproc[0]); 595 dct->p_out (signal_from_coproc[0]); 596 dct->p_config (signal_config_coproc[0]); 597 598 mwmr->p_clk (this->p_clk); 599 mwmr->p_resetn (this->p_resetn); 600 mwmr->p_vci_target (signal_int_vci_tgt_mwmr); 601 mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); 602 mwmr->p_to_coproc[0] (signal_to_coproc[0]); 603 mwmr->p_from_coproc[0] (signal_from_coproc[0]); 604 mwmr->p_config[0] (signal_config_coproc[0]); 605 mwmr->p_irq (signal_irq_mwmr); 606 } 607 608 std::cout << " - coproc connected" << std::endl; 609 610 /////////////////////////////////// CPY coprocessor 611 if ( coproc_type == MWR_COPROC_CPY ) 612 { 613 cpy->p_clk (this->p_clk); 614 cpy->p_resetn (this->p_resetn); 615 cpy->p_load (signal_to_coproc[0]); 616 cpy->p_store (signal_from_coproc[0]); 617 cpy->p_config (signal_config_coproc[0]); 618 619 mwmr->p_clk (this->p_clk); 620 mwmr->p_resetn (this->p_resetn); 621 mwmr->p_vci_target (signal_int_vci_tgt_mwmr); 622 mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); 623 mwmr->p_to_coproc[0] (signal_to_coproc[0]); 624 mwmr->p_from_coproc[0] (signal_from_coproc[0]); 625 mwmr->p_config[0] (signal_config_coproc[0]); 626 mwmr->p_irq (signal_irq_mwmr); 627 } 521 /////////////////////////////////// MDMA 522 mdma->p_clk (this->p_clk); 523 mdma->p_resetn (this->p_resetn); 524 mdma->p_vci_target (signal_int_vci_tgt_mdma); 525 mdma->p_vci_initiator (signal_int_vci_ini_mdma); 526 for( size_t i = 0 ; i < nb_procs ; i++ ) 527 { 528 mdma->p_irq[i] (signal_irq_mdma[i]); 529 } 530 531 std::cout << " - mdma connected" << std::endl; 628 532 629 533 //////////////////////////// RAM NETWORK ROUTERS … … 712 616 int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); 713 617 int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); 714 int_xbar_d->p_to_target[int_m wmr_tgt_id] (signal_int_vci_tgt_mwmr);715 int_xbar_d->p_to_initiator[int_m wmr_ini_id] (signal_int_vci_ini_mwmr);618 int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); 619 int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); 716 620 for (size_t p = 0; p < nb_procs; p++) 717 621 int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
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