Ignore:
Timestamp:
Sep 15, 2017, 12:32:44 AM (7 years ago)
Author:
alain
Message:

Replace the "vci_mlti_tty" component by the "vci_tty_tsar" component,
in yje tsar_generic_iob platform.
This new component povide two IRQs per channel:

  • RX_IRQ, when the read buffer is non-empty
  • TX_IRQ, when the write buffer is not full.

The new tsar_generic_iob platform supports up to 8 TTY channels.
The new vci_tty_tsar component is stored in the TSAR SVN.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/platforms/tsar_generic_iob/arch_info.py

    r1051 r1053  
    99#########################################################################################
    1010#  This python script defines a specific instance of "tsar_generic_iob" architecture
    11 #  for the ALMOS-MK operating system. It is used to generate the "hard_config.h"
    12 #  and the "arch_info.bin files, used by bthe ALMOS-MK bootloader.
     11#  for the ALMOS-MKH operating system. It is used to generate the "hard_config.h" file,
     12#  used to configure the hardware architecture, and the "arch_info.bin" file, used by
     13#  the ALMOS-MK bootloader.
    1314#
    1415#  The constructor prototype format is imposed by the genarch.py application,
     
    3132#  - fbf_width      : frame_buffer width = frame_buffer heigth
    3233#  - ioc_type       : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE'
    33 #  - io_cxy         : IO cluster identifier
    34 #  - boot_cxy       : boot cluster identifier
    35 #  - cache_line     : number of bytes in cache line (in 16,32,64)
    3634#
    3735#  The following parameters are imposed by the "tsar_generic_iob" architecture:
     
    4240#  - p_width        : number of bits for local processor index
    4341#  - irqs_per_core  : number of input IRQs per processor
     42#  - io_cxy         : IO cluster identifier
     43#  - boot_cxy       : boot cluster identifier
     44#  - cache_line     : number of bytes in cache line (in 16,32,64)
    4445########################################################################################
    4546
     
    5152          nb_nics       = 1,
    5253          fbf_width     = 128,
    53           ioc_type      = 'IOC_BDV',
    54           io_cxy        = 0,
    55           boot_cxy      = 0,
    56           cache_line    = 64):
     54          ioc_type      = 'IOC_BDV'):
    5755
    5856    ### architecture constants
     
    6462    irqs_per_core = 4           
    6563    devices_max   = 16 
     64    boot_cxy      = 0
     65    cache_line    = 64
     66    io_cxy        = ((x_size-1)<<y_width) + (y_size-1)   # upper right cluster
    6667
    6768    ### constructor parameters checking
     
    182183                                   channels = nb_cores )
    183184
    184             archi.addIrq( dstdev = xcu, port = 1, srcdev = dma, channel = 0 )
    185             archi.addIrq( dstdev = xcu, port = 2, srcdev = dma, channel = 1 )
    186             archi.addIrq( dstdev = xcu, port = 3, srcdev = dma, channel = 2 )
    187             archi.addIrq( dstdev = xcu, port = 4, srcdev = dma, channel = 3 )
     185            for i in xrange( nb_cores ):
     186                archi.addIrq( dstdev = xcu, port = i+1 , srcdev = dma, channel = i )
    188187
    189188            # define external devices
     
    244243                archi.addIrq( dstdev = pic, port = 23, srcdev = tty, channel = 7 , is_rx = True )
    245244
     245                archi.addIrq( dstdev = pic, port = 24, srcdev = tty, channel = 0 , is_rx = False )
     246                archi.addIrq( dstdev = pic, port = 25, srcdev = tty, channel = 1 , is_rx = False )
     247                archi.addIrq( dstdev = pic, port = 26, srcdev = tty, channel = 2 , is_rx = False )
     248                archi.addIrq( dstdev = pic, port = 27, srcdev = tty, channel = 3 , is_rx = False )
     249                archi.addIrq( dstdev = pic, port = 28, srcdev = tty, channel = 4 , is_rx = False )
     250                archi.addIrq( dstdev = pic, port = 29, srcdev = tty, channel = 5 , is_rx = False )
     251                archi.addIrq( dstdev = pic, port = 30, srcdev = tty, channel = 6 , is_rx = False )
     252                archi.addIrq( dstdev = pic, port = 31, srcdev = tty, channel = 7 , is_rx = False )
     253
    246254            # define cores
    247255            for p in xrange ( nb_cores ):
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