Changeset 1053 for trunk/platforms/tsar_generic_iob/arch_info.py
- Timestamp:
- Sep 15, 2017, 12:32:44 AM (7 years ago)
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trunk/platforms/tsar_generic_iob/arch_info.py
r1051 r1053 9 9 ######################################################################################### 10 10 # This python script defines a specific instance of "tsar_generic_iob" architecture 11 # for the ALMOS-MK operating system. It is used to generate the "hard_config.h" 12 # and the "arch_info.bin files, used by bthe ALMOS-MK bootloader. 11 # for the ALMOS-MKH operating system. It is used to generate the "hard_config.h" file, 12 # used to configure the hardware architecture, and the "arch_info.bin" file, used by 13 # the ALMOS-MK bootloader. 13 14 # 14 15 # The constructor prototype format is imposed by the genarch.py application, … … 31 32 # - fbf_width : frame_buffer width = frame_buffer heigth 32 33 # - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' 33 # - io_cxy : IO cluster identifier34 # - boot_cxy : boot cluster identifier35 # - cache_line : number of bytes in cache line (in 16,32,64)36 34 # 37 35 # The following parameters are imposed by the "tsar_generic_iob" architecture: … … 42 40 # - p_width : number of bits for local processor index 43 41 # - irqs_per_core : number of input IRQs per processor 42 # - io_cxy : IO cluster identifier 43 # - boot_cxy : boot cluster identifier 44 # - cache_line : number of bytes in cache line (in 16,32,64) 44 45 ######################################################################################## 45 46 … … 51 52 nb_nics = 1, 52 53 fbf_width = 128, 53 ioc_type = 'IOC_BDV', 54 io_cxy = 0, 55 boot_cxy = 0, 56 cache_line = 64): 54 ioc_type = 'IOC_BDV'): 57 55 58 56 ### architecture constants … … 64 62 irqs_per_core = 4 65 63 devices_max = 16 64 boot_cxy = 0 65 cache_line = 64 66 io_cxy = ((x_size-1)<<y_width) + (y_size-1) # upper right cluster 66 67 67 68 ### constructor parameters checking … … 182 183 channels = nb_cores ) 183 184 184 archi.addIrq( dstdev = xcu, port = 1, srcdev = dma, channel = 0 ) 185 archi.addIrq( dstdev = xcu, port = 2, srcdev = dma, channel = 1 ) 186 archi.addIrq( dstdev = xcu, port = 3, srcdev = dma, channel = 2 ) 187 archi.addIrq( dstdev = xcu, port = 4, srcdev = dma, channel = 3 ) 185 for i in xrange( nb_cores ): 186 archi.addIrq( dstdev = xcu, port = i+1 , srcdev = dma, channel = i ) 188 187 189 188 # define external devices … … 244 243 archi.addIrq( dstdev = pic, port = 23, srcdev = tty, channel = 7 , is_rx = True ) 245 244 245 archi.addIrq( dstdev = pic, port = 24, srcdev = tty, channel = 0 , is_rx = False ) 246 archi.addIrq( dstdev = pic, port = 25, srcdev = tty, channel = 1 , is_rx = False ) 247 archi.addIrq( dstdev = pic, port = 26, srcdev = tty, channel = 2 , is_rx = False ) 248 archi.addIrq( dstdev = pic, port = 27, srcdev = tty, channel = 3 , is_rx = False ) 249 archi.addIrq( dstdev = pic, port = 28, srcdev = tty, channel = 4 , is_rx = False ) 250 archi.addIrq( dstdev = pic, port = 29, srcdev = tty, channel = 5 , is_rx = False ) 251 archi.addIrq( dstdev = pic, port = 30, srcdev = tty, channel = 6 , is_rx = False ) 252 archi.addIrq( dstdev = pic, port = 31, srcdev = tty, channel = 7 , is_rx = False ) 253 246 254 # define cores 247 255 for p in xrange ( nb_cores ):
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