Changeset 1060 for trunk/platforms/tsar_generic_iob/top.cpp
- Timestamp:
- Mar 1, 2019, 12:27:13 PM (6 years ago)
- File:
-
- 1 edited
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trunk/platforms/tsar_generic_iob/top.cpp
r1056 r1060 1656 1656 1657 1657 // Monitor a specific address for one L1 cache 1658 // clusters[0][ 0]->proc[0]->cache_monitor( 0x00032D74ULL );1658 // clusters[0][1]->proc[0]->cache_monitor( 0x10003ddb4ULL ); 1659 1659 1660 1660 // Monitor a specific address for L2 cache (single word if second argument true) 1661 clusters[0][0]->memc->cache_monitor( 0xdbc7cULL , true );1661 // clusters[0][0]->memc->cache_monitor( 0x0000d74c0ULL , false ); 1662 1662 1663 1663 // Monitor a specific address for one XRAM 1664 // clusters[0][ 0]->xram->start_monitor( 0x0008A000ULL , 64);1664 // clusters[0][1]->xram->start_monitor( 0x100094000ULL , 64); 1665 1665 1666 1666 if ( debug_ok and (n > debug_from) ) … … 1668 1668 std::cout << "****************** cycle " << std::dec << n ; 1669 1669 std::cout << " ************************************************" << std::endl; 1670 // 1670 1671 // trace proc[debug_proc_id] 1671 1672 if ( debug_proc_id != 0xFFFFFFFF ) … … 1679 1680 // 0x20 : itlb trace 1680 1681 // 0x40 : SR 1682 1681 1683 size_t l = debug_proc_id & ((1<<P_WIDTH)-1) ; 1682 1684 size_t cluster_xy = debug_proc_id >> P_WIDTH ; … … 1767 1769 // signal_vci_tgt_brom.print_trace("[SIG]BROM_TGT"); 1768 1770 1769 1770 1771 1772 //disk->print_trace();1773 //signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT");1774 //signal_vci_ini_disk.print_trace("[SIG]DISK_INI");1771 // mtty->print_trace( 1 ); 1772 // signal_vci_tgt_mtty.print_trace("[SIG]MTTY_TGT"); 1773 1774 disk->print_trace(); 1775 signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT"); 1776 signal_vci_ini_disk.print_trace("[SIG]DISK_INI"); 1775 1777 1776 1778 #if ( USE_IOC_SDC )
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