Changeset 1062
- Timestamp:
- Oct 21, 2019, 5:51:34 PM (5 years ago)
- Location:
- trunk/platforms/tsar_generic_iob
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/arch_info.py
r1060 r1062 72 72 cache_line = 64 73 73 devices_max = 16 74 fbf_width = 25674 fbf_width = 128 75 75 76 76 ### constructor parameters checking … … 103 103 104 104 ram_base = 0x0000000000 105 ram_size = 0x 1000000 # 16Mbytes105 ram_size = 0x4000000 # 64 Mbytes 106 106 107 107 xcu_base = 0x00B0000000 … … 117 117 ## These segments are only defined in cluster_io 118 118 119 ioc_base = 0x00B3000000 119 ioc_base = 0x00B3000000 120 120 ioc_size = 0x1000 # 4 Kbytes 121 121 … … 127 127 128 128 fbf_base = 0x00B7000000 129 fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes129 fbf_size = 0x400000 + 0x1000 # 4 Mbytes + 4 Kbytes 130 130 131 131 pic_base = 0x00B8000000 … … 133 133 134 134 iob_base = 0x00BE000000 135 iob_size = 0x1000 # 4 bytes135 iob_size = 0x1000 # 4 Kbytes 136 136 137 137 rom_base = 0x00BFC00000 -
trunk/platforms/tsar_generic_iob/top.cpp
r1060 r1062 1655 1655 } 1656 1656 1657 // Monitor a specific address for one L1 cache1657 // Monitor a specific address for one L1 data cache 1658 1658 // clusters[0][1]->proc[0]->cache_monitor( 0x10003ddb4ULL ); 1659 1659 1660 1660 // Monitor a specific address for L2 cache (single word if second argument true) 1661 // clusters[0][0]->memc->cache_monitor( 0x 0000d74c0ULL , false );1661 // clusters[0][0]->memc->cache_monitor( 0xcfe90ULL , true ); 1662 1662 1663 1663 // Monitor a specific address for one XRAM 1664 1664 // clusters[0][1]->xram->start_monitor( 0x100094000ULL , 64); 1665 1666 // Monitor the MMU for one L1 cache 1667 // clusters[0][0]->proc[0]->mmu_monitor(); 1665 1668 1666 1669 if ( debug_ok and (n > debug_from) )
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