Changeset 1063

Timestamp:

Nov 13, 2019, 6:24:53 PM (5 years ago)

Author:

alain

Message:

Improve the print_trace() function to display CP2 registers.

Location:

trunk/modules/vci_cc_vcache_wrapper/caba/source

Files:

• include/vci_cc_vcache_wrapper.h (modified) (4 diffs)
• src/vci_cc_vcache_wrapper.cpp (modified) (9 diffs)

trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -357 +357 @@
     sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
     sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
+    sc_signal<uint32_t>     r_mmu_dext;                 // data address extension (when vci_address > 32 bits)
+    sc_signal<uint32_t>     r_mmu_iext;                 // inst address extension (when vci_address > 32 bits)
     uint32_t                r_mmu_params;                       // read-only
     uint32_t                r_mmu_release;                      // read_only
@@ -408 +410 @@
     sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
     sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
-
-    // Physical address extension for data access
-    sc_signal<uint32_t>     r_icache_paddr_ext;             // CP2 register (if vci_address > 32)
 
     ///////////////////////////////
@@ -510 +509 @@
     bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
     bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
-
-    // Physical address extension for data access
-    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
 
     ///////////////////////////////////
@@ -766 +762 @@
     // Set the m_dcache_paddr_ext_reset attribute
     //
-    // The r_dcache_paddr_ext register will be initialized after
+    // The r_mmu_dext register will be initialized after
     // reset with the m_dcache_paddr_ext_reset value
     /////////////////////////////////////////////////////////////

trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -502 +502 @@
               << "  MMU_MODE = " << r_mmu_mode.read()
               << " | MMU_PTPR = " << r_mmu_ptpr.read()
-              << " | LLSC_COUNT = " << r_llsc_count.read()
+              << " | MMU_DEXT = " << r_mmu_dext.read()
+              << " | MMU_IEXT = " << r_mmu_iext.read() << std::endl;
+
+    std::cout << "  LLSC_COUNT = " << r_llsc_count.read()
               << " | LLSC_PADDR = " << r_llsc_paddr.read()
               << " | LLSC_KEY = " << r_llsc_key.read();
@@ -793 +796 @@
 
         // reset data physical address extension
-        r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
+        r_mmu_dext = m_dcache_paddr_ext_reset;
 
         // reset inst physical address extension
-        r_icache_paddr_ext = m_icache_paddr_ext_reset;
+        r_mmu_iext = m_icache_paddr_ext_reset;
 
         // reset dcache directory extension
@@ -1153 +1156 @@
             else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
             {
-                r_icache_paddr_ext = r_dcache_save_wdata.read();
+                r_mmu_iext = r_dcache_save_wdata.read();
                 r_dcache_xtn_req   = false;
             }
@@ -1200 +1203 @@
             else if (vci_param::N > 32)
             {
-                paddr = paddr | ((paddr_t) r_icache_paddr_ext.read() << 32);
+                paddr = paddr | ((paddr_t) r_mmu_iext.read() << 32);
             }
 
@@ -2327 +2330 @@
                 // we take into account the paddr extension
                 if (vci_param::N > 32)
-                    paddr = paddr | ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
+                    paddr = paddr | ((paddr_t) (r_mmu_dext.read()) << 32);
             }
         } // end physical address computation
@@ -2550 +2553 @@
 
                     case iss_t::XTN_DATA_PADDR_EXT:
-                        m_drsp.rdata = r_dcache_paddr_ext.read();
+                        m_drsp.rdata = r_mmu_dext.read();
                         m_drsp.valid = true;
                         m_drsp.error = false;
@@ -2556 +2559 @@
 
                     case iss_t::XTN_INST_PADDR_EXT:
-                        m_drsp.rdata = r_icache_paddr_ext.read();
+                        m_drsp.rdata = r_mmu_iext.read();
                         m_drsp.valid = true;
                         m_drsp.error = false;
@@ -2678 +2681 @@
 
                     case iss_t::XTN_DATA_PADDR_EXT:  // no cache or tlb access
-                        r_dcache_paddr_ext = m_dreq.wdata;
+                        r_mmu_dext = m_dreq.wdata;
                         m_drsp.valid       = true;
                         r_dcache_fsm       = DCACHE_IDLE;
@@ -3997 +4000 @@
             paddr = (paddr_t)r_dcache_save_wdata.read();
             if (vci_param::N > 32)
-                paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
+                paddr = paddr | ((paddr_t)(r_mmu_dext.read()) << 32);
             hit = true;
         }