- Timestamp:
- Nov 13, 2019, 6:24:53 PM (5 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r1061 r1063 357 357 sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type 358 358 sc_signal<uint32_t> r_mmu_detr; // mmu data error type 359 sc_signal<uint32_t> r_mmu_dext; // data address extension (when vci_address > 32 bits) 360 sc_signal<uint32_t> r_mmu_iext; // inst address extension (when vci_address > 32 bits) 359 361 uint32_t r_mmu_params; // read-only 360 362 uint32_t r_mmu_release; // read_only … … 408 410 sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way 409 411 sc_signal<size_t> r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index 410 411 // Physical address extension for data access412 sc_signal<uint32_t> r_icache_paddr_ext; // CP2 register (if vci_address > 32)413 412 414 413 /////////////////////////////// … … 510 509 bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 511 510 bool *r_dcache_contains_ptd; // cache line contains a PTD 512 513 // Physical address extension for data access514 sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32)515 511 516 512 /////////////////////////////////// … … 766 762 // Set the m_dcache_paddr_ext_reset attribute 767 763 // 768 // The r_ dcache_paddr_ext register will be initialized after764 // The r_mmu_dext register will be initialized after 769 765 // reset with the m_dcache_paddr_ext_reset value 770 766 ///////////////////////////////////////////////////////////// -
trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r1061 r1063 502 502 << " MMU_MODE = " << r_mmu_mode.read() 503 503 << " | MMU_PTPR = " << r_mmu_ptpr.read() 504 << " | LLSC_COUNT = " << r_llsc_count.read() 504 << " | MMU_DEXT = " << r_mmu_dext.read() 505 << " | MMU_IEXT = " << r_mmu_iext.read() << std::endl; 506 507 std::cout << " LLSC_COUNT = " << r_llsc_count.read() 505 508 << " | LLSC_PADDR = " << r_llsc_paddr.read() 506 509 << " | LLSC_KEY = " << r_llsc_key.read(); … … 793 796 794 797 // reset data physical address extension 795 r_ dcache_paddr_ext = m_dcache_paddr_ext_reset;798 r_mmu_dext = m_dcache_paddr_ext_reset; 796 799 797 800 // reset inst physical address extension 798 r_ icache_paddr_ext = m_icache_paddr_ext_reset;801 r_mmu_iext = m_icache_paddr_ext_reset; 799 802 800 803 // reset dcache directory extension … … 1153 1156 else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT) 1154 1157 { 1155 r_ icache_paddr_ext = r_dcache_save_wdata.read();1158 r_mmu_iext = r_dcache_save_wdata.read(); 1156 1159 r_dcache_xtn_req = false; 1157 1160 } … … 1200 1203 else if (vci_param::N > 32) 1201 1204 { 1202 paddr = paddr | ((paddr_t) r_ icache_paddr_ext.read() << 32);1205 paddr = paddr | ((paddr_t) r_mmu_iext.read() << 32); 1203 1206 } 1204 1207 … … 2327 2330 // we take into account the paddr extension 2328 2331 if (vci_param::N > 32) 2329 paddr = paddr | ((paddr_t) (r_ dcache_paddr_ext.read()) << 32);2332 paddr = paddr | ((paddr_t) (r_mmu_dext.read()) << 32); 2330 2333 } 2331 2334 } // end physical address computation … … 2550 2553 2551 2554 case iss_t::XTN_DATA_PADDR_EXT: 2552 m_drsp.rdata = r_ dcache_paddr_ext.read();2555 m_drsp.rdata = r_mmu_dext.read(); 2553 2556 m_drsp.valid = true; 2554 2557 m_drsp.error = false; … … 2556 2559 2557 2560 case iss_t::XTN_INST_PADDR_EXT: 2558 m_drsp.rdata = r_ icache_paddr_ext.read();2561 m_drsp.rdata = r_mmu_iext.read(); 2559 2562 m_drsp.valid = true; 2560 2563 m_drsp.error = false; … … 2678 2681 2679 2682 case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access 2680 r_ dcache_paddr_ext = m_dreq.wdata;2683 r_mmu_dext = m_dreq.wdata; 2681 2684 m_drsp.valid = true; 2682 2685 r_dcache_fsm = DCACHE_IDLE; … … 3997 4000 paddr = (paddr_t)r_dcache_save_wdata.read(); 3998 4001 if (vci_param::N > 32) 3999 paddr = paddr | ((paddr_t)(r_ dcache_paddr_ext.read()) << 32);4002 paddr = paddr | ((paddr_t)(r_mmu_dext.read()) << 32); 4000 4003 hit = true; 4001 4004 }
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