Changeset 119 for trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp
- Timestamp:
- Dec 6, 2010, 6:12:46 AM (14 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
- Removed
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trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp
r104 r119 41 41 "ICACHE_TLB1_LL_WAIT", 42 42 "ICACHE_TLB1_SC_WAIT", 43 "ICACHE_TLB1_UPDT_SEL", 43 44 "ICACHE_TLB1_UPDT", 44 45 "ICACHE_TLB2_READ", 45 46 "ICACHE_TLB2_LL_WAIT", 46 47 "ICACHE_TLB2_SC_WAIT", 48 "ICACHE_TLB2_UPDT_SEL", 47 49 "ICACHE_TLB2_UPDT", 48 50 "ICACHE_TLB_FLUSH", … … 64 66 "DCACHE_TLB1_LL_WAIT", 65 67 "DCACHE_TLB1_SC_WAIT", 68 "DCACHE_TLB1_UPDT_SEL", 66 69 "DCACHE_TLB1_UPDT", 67 70 "DCACHE_TLB2_READ", 68 71 "DCACHE_TLB2_LL_WAIT", 69 72 "DCACHE_TLB2_SC_WAIT", 73 "DCACHE_TLB2_UPDT_SEL", 70 74 "DCACHE_TLB2_UPDT", 71 75 "DCACHE_CTXT_SWITCH", … … 395 399 r_dcache_tlb_ll_dirty_req = false; 396 400 r_dcache_tlb_sc_dirty_req = false; 401 r_dcache_sc_updt_dirty = false; 397 402 r_dcache_tlb_sc_fail = false; 398 403 r_dcache_tlb_ptba_read = false; … … 614 619 615 620 // multi-update or multi-invalidate for data type 616 if ( ( (address &0x3) != 0x3 ) && ( ! m_segment.contains(address)) )621 if ( ( (address&0x3) != 0x3 ) && ( ! m_segment.contains(address)) ) 617 622 { 618 623 std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl; … … 628 633 (paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4; 629 634 630 if ( (address &0x3) == 0x3 ) // broadcast invalidate for data or instruction type635 if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type 631 636 { 632 637 if ( ! p_vci_tgt.eop.read() ) … … 793 798 case TGT_RSP_ICACHE: 794 799 { 795 if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() )800 if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 796 801 { 797 802 r_vci_tgt_fsm = TGT_IDLE; … … 803 808 case TGT_RSP_DCACHE: 804 809 { 805 if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )810 if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() ) 806 811 { 807 812 r_vci_tgt_fsm = TGT_IDLE; … … 1208 1213 { 1209 1214 r_icache_pte_update = r_icache_miss_buf[0]; 1210 r_icache_fsm = ICACHE_TLB1_UPDT ;1215 r_icache_fsm = ICACHE_TLB1_UPDT_SEL; 1211 1216 } 1212 1217 else … … 1224 1229 { 1225 1230 r_icache_pte_update = r_icache_miss_buf[0]; 1226 r_icache_fsm = ICACHE_TLB1_UPDT ;1231 r_icache_fsm = ICACHE_TLB1_UPDT_SEL; 1227 1232 } 1228 1233 else … … 1356 1361 else 1357 1362 { 1358 r_icache_fsm = ICACHE_TLB1_UPDT ;1363 r_icache_fsm = ICACHE_TLB1_UPDT_SEL; 1359 1364 } 1360 1365 } … … 1362 1367 break; 1363 1368 } 1364 ////////////////////// 1365 case ICACHE_TLB1_UPDT :1369 ////////////////////////// 1370 case ICACHE_TLB1_UPDT_SEL: 1366 1371 { 1367 1372 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; … … 1375 1380 } 1376 1381 1377 // TLB update and invalidate different PTE1378 if ( !r_icache_inval_tlb_rsp && !r_icache_cleanup_req )1379 {1380 paddr_t victim_index = 0;1381 r_icache_cleanup_req = icache_tlb.update1(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_icache_words)+2)),&victim_index);1382 r_icache_cleanup_line = victim_index;1383 r_icache_cleanup_type = TLB_CLEANUP;1384 m_cpt_cc_cleanup_ins++;1385 r_icache_fsm = ICACHE_IDLE;1386 }1387 1388 1382 // TLB update and invalidate same PTE 1389 1383 if ( r_icache_inval_tlb_rsp ) … … 1392 1386 r_icache_fsm = ICACHE_IDLE; 1393 1387 } 1388 1389 // TLB update and invalidate different PTE 1390 if ( !r_icache_cleanup_req ) 1391 { 1392 size_t way = 0; 1393 size_t set = 0; 1394 paddr_t victim_index = 0; 1395 1396 bool cleanup = icache_tlb.select1((r_icache_vaddr_req.read()>> PAGE_M_NBITS),&victim_index,&way,&set); 1397 r_icache_way = way; 1398 r_icache_set = set; 1399 if (cleanup) 1400 { 1401 r_icache_cleanup_req = true; 1402 r_icache_cleanup_line = victim_index; 1403 r_icache_cleanup_type = TLB_CLEANUP; 1404 m_cpt_cc_cleanup_ins++; 1405 } 1406 r_icache_fsm = ICACHE_TLB1_UPDT; 1407 } 1408 break; 1409 } 1410 ///////////////////// 1411 case ICACHE_TLB1_UPDT: 1412 { 1413 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1414 1415 icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2))); 1416 r_icache_fsm = ICACHE_IDLE; 1394 1417 break; 1395 1418 } … … 1445 1468 if ( (r_icache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set 1446 1469 { 1447 r_icache_fsm = ICACHE_TLB2_UPDT ;1470 r_icache_fsm = ICACHE_TLB2_UPDT_SEL; 1448 1471 r_icache_pte_update = r_icache_miss_buf[0]; 1449 1472 } … … 1461 1484 if ( (r_icache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set 1462 1485 { 1463 r_icache_fsm = ICACHE_TLB2_UPDT ;1486 r_icache_fsm = ICACHE_TLB2_UPDT_SEL; 1464 1487 r_icache_pte_update = r_icache_miss_buf[0]; 1465 1488 } … … 1595 1618 else 1596 1619 { 1597 r_icache_fsm = ICACHE_TLB2_UPDT ;1620 r_icache_fsm = ICACHE_TLB2_UPDT_SEL; 1598 1621 } 1599 1622 } 1600 1623 } 1601 1624 break; 1625 } 1626 ////////////////////////// 1627 case ICACHE_TLB2_UPDT_SEL: 1628 { 1629 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1630 1631 // external cache invalidate request 1632 if ( r_tgt_icache_req ) 1633 { 1634 r_icache_fsm = ICACHE_CC_INVAL; 1635 r_icache_fsm_save = r_icache_fsm; 1636 break; 1637 } 1638 1639 // TLB update and invalidate same PTE 1640 if ( r_icache_inval_tlb_rsp ) 1641 { 1642 r_icache_inval_tlb_rsp = false; 1643 r_icache_fsm = ICACHE_IDLE; 1644 } 1645 1646 // TLB update and invalidate different PTE 1647 if ( !r_icache_cleanup_req ) 1648 { 1649 size_t way = 0; 1650 size_t set = 0; 1651 paddr_t victim_index = 0; 1652 1653 bool cleanup = icache_tlb.select1((r_icache_vaddr_req.read()>> PAGE_K_NBITS),&victim_index,&way,&set); 1654 r_icache_way = way; 1655 r_icache_set = set; 1656 if (cleanup) 1657 { 1658 r_icache_cleanup_req = true; 1659 r_icache_cleanup_line = victim_index; 1660 r_icache_cleanup_type = TLB_CLEANUP; 1661 m_cpt_cc_cleanup_ins++; 1662 } 1663 r_icache_fsm = ICACHE_TLB2_UPDT; 1664 } 1665 1666 break; 1602 1667 } 1603 1668 ///////////////////// 1604 1669 case ICACHE_TLB2_UPDT: 1605 1670 { 1606 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1607 1608 // external cache invalidate request 1609 if ( r_tgt_icache_req ) 1610 { 1611 r_icache_fsm = ICACHE_CC_INVAL; 1612 r_icache_fsm_save = r_icache_fsm; 1613 break; 1614 } 1615 1616 // TLB update and invalidate different PTE 1617 1618 if ( !r_icache_inval_tlb_rsp && !r_icache_cleanup_req ) 1619 { 1620 paddr_t victim_index = 0; 1621 r_icache_cleanup_req = icache_tlb.update1(r_icache_pte_update,r_icache_miss_buf[1],r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_icache_words)+2)),&victim_index); 1622 r_icache_cleanup_line = victim_index; 1623 r_icache_cleanup_type = TLB_CLEANUP; 1624 m_cpt_cc_cleanup_ins++; 1625 r_icache_fsm = ICACHE_IDLE; 1626 } 1627 1628 // TLB update and invalidate same PTE 1629 if ( r_icache_inval_tlb_rsp ) 1630 { 1631 r_icache_inval_tlb_rsp = false; 1632 r_icache_fsm = ICACHE_IDLE; 1633 } 1671 icache_tlb.update(r_icache_pte_update,r_icache_miss_buf[1],r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_icache_words)+2))); 1672 r_icache_fsm = ICACHE_IDLE; 1634 1673 break; 1635 1674 } … … 1662 1701 } 1663 1702 if (clean) break; 1703 set = 0; 1664 1704 } 1665 1705 … … 1711 1751 } 1712 1752 if (clean) break; 1753 set = 0; 1713 1754 } 1714 1755 if (way == m_icache_ways) … … 2016 2057 2017 2058 // invalidate cache 2018 if( (( r_icache_fsm_save.read() == ICACHE_TLB1_READ ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_READ ) ||2019 ( r_icache_fsm_save.read() == ICACHE_TLB1_LL_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_LL_WAIT ) ||2020 ( r_icache_fsm_save.read() == ICACHE_TLB1_SC_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_SC_WAIT ) ||2021 ( r_icache_fsm_save.read() == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_UPDT)) &&2059 if( (( r_icache_fsm_save.read() == ICACHE_TLB1_READ ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_READ ) || 2060 ( r_icache_fsm_save.read() == ICACHE_TLB1_LL_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_LL_WAIT ) || 2061 ( r_icache_fsm_save.read() == ICACHE_TLB1_SC_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_SC_WAIT ) || 2062 ( r_icache_fsm_save.read() == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_UPDT_SEL )) && 2022 2063 ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == r_tgt_addr.read()) ) 2023 2064 { … … 2032 2073 2033 2074 if( (/*( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) ||*/ 2034 ( r_icache_fsm_save.read() == ICACHE_TLB1_LL_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_LL_WAIT ) ||2035 ( r_icache_fsm_save.read() == ICACHE_TLB1_SC_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_SC_WAIT ) ||2036 ( r_icache_fsm_save.read() == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_UPDT)) &&2075 ( r_icache_fsm_save.read() == ICACHE_TLB1_LL_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_LL_WAIT ) || 2076 ( r_icache_fsm_save.read() == ICACHE_TLB1_SC_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_SC_WAIT ) || 2077 ( r_icache_fsm_save.read() == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_UPDT_SEL )) && 2037 2078 ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == r_tgt_addr.read()) ) 2038 2079 { … … 2621 2662 else 2622 2663 { 2623 r_dcache_unc_req = true; 2624 r_dcache_fsm = DCACHE_UNC_WAIT; 2625 m_cpt_unc_read++; 2664 if ( (dreq.type == iss_t::DATA_SC) && !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required 2665 { 2666 m_cpt_data_tlb_update_dirty++; 2667 m_cost_data_tlb_update_dirty_frz++; 2668 r_dcache_sc_updt_dirty = true; 2669 if (dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set)) 2670 { 2671 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2672 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2673 r_dcache_tlb_ll_dirty_req = true; 2674 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2675 } 2676 else 2677 { 2678 if (dcache_hit_p) 2679 { 2680 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2681 r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 2682 r_dcache_tlb_ll_dirty_req = true; 2683 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2684 } 2685 else // get PTBA to calculate the physical address of PTE 2686 { 2687 data_t ptba; 2688 if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba)) 2689 { 2690 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2691 r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 2692 (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 2693 r_dcache_tlb_ll_dirty_req = true; 2694 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2695 } 2696 else 2697 { 2698 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2699 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2700 r_dcache_tlb_read_req = true; 2701 r_dcache_tlb_first_req = true; 2702 r_dcache_tlb_ptba_read = true; 2703 r_dcache_fsm = DCACHE_TLB1_READ; 2704 } 2705 } 2706 } 2707 } 2708 else 2709 { 2710 r_dcache_unc_req = true; 2711 r_dcache_fsm = DCACHE_UNC_WAIT; 2712 m_cpt_unc_read++; 2713 } 2626 2714 m_cost_unc_read_frz++; 2627 2715 } … … 2661 2749 { 2662 2750 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2663 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2664 r_dcache_tlb_read_req = true; 2665 r_dcache_tlb_first_req = true; 2666 r_dcache_tlb_ptba_read = true; 2667 r_dcache_fsm = DCACHE_TLB1_READ; 2751 data_t ptba; 2752 if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba)) 2753 { 2754 r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 2755 r_dcache_tlb_ll_dirty_req = true; 2756 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2757 } 2758 else 2759 { 2760 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2761 r_dcache_tlb_read_req = true; 2762 r_dcache_tlb_first_req = true; 2763 r_dcache_tlb_ptba_read = true; 2764 r_dcache_fsm = DCACHE_TLB1_READ; 2765 } 2668 2766 } 2669 2767 } … … 2791 2889 else 2792 2890 { 2793 r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK; 2794 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2795 r_dcache_tlb_read_req = true; 2796 r_dcache_tlb_first_req = true; 2797 r_dcache_tlb_ptba_read = true; 2798 r_dcache_fsm = DCACHE_TLB1_READ; 2891 r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK; 2892 data_t ptba; 2893 if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba)) 2894 { 2895 r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 2896 r_dcache_tlb_ll_dirty_req = true; 2897 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2898 } 2899 else 2900 { 2901 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2902 r_dcache_tlb_read_req = true; 2903 r_dcache_tlb_first_req = true; 2904 r_dcache_tlb_ptba_read = true; 2905 r_dcache_fsm = DCACHE_TLB1_READ; 2906 } 2799 2907 } 2800 2908 } … … 2847 2955 if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false; 2848 2956 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 2957 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 2849 2958 } 2850 2959 else … … 2865 2974 if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false; 2866 2975 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 2976 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 2867 2977 } 2868 2978 else if ( r_dcache_inval_tlb_rsp ) … … 2870 2980 r_dcache_inval_tlb_rsp = false; 2871 2981 r_dcache_fsm = DCACHE_IDLE; 2982 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 2872 2983 } 2873 2984 else if ( r_dcache_inval_rsp ) … … 2875 2986 r_dcache_inval_rsp = false; 2876 2987 r_dcache_fsm = DCACHE_IDLE; 2988 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 2877 2989 } 2878 2990 else … … 2915 3027 if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false; 2916 3028 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 3029 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 2917 3030 } 2918 3031 else … … 2923 3036 r_dcache_inval_tlb_rsp = false; 2924 3037 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3038 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 2925 3039 r_dcache_fsm = DCACHE_IDLE; 2926 3040 } … … 2929 3043 r_dcache_inval_rsp = false; 2930 3044 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3045 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 2931 3046 r_dcache_fsm = DCACHE_IDLE; 2932 3047 } … … 2977 3092 if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false; 2978 3093 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 3094 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 2979 3095 break; 2980 3096 } … … 2988 3104 m_cpt_cc_cleanup_data++; 2989 3105 r_dcache_inval_tlb_rsp = false; 3106 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 2990 3107 break; 2991 3108 } … … 3047 3164 { 3048 3165 r_dcache_pte_update = r_dcache_miss_buf[0]; 3049 r_dcache_fsm = DCACHE_TLB1_UPDT ;3166 r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 3050 3167 } 3051 3168 else … … 3063 3180 { 3064 3181 r_dcache_pte_update = r_dcache_miss_buf[0]; 3065 r_dcache_fsm = DCACHE_TLB1_UPDT ;3182 r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 3066 3183 } 3067 3184 else … … 3189 3306 else 3190 3307 { 3191 r_dcache_fsm = DCACHE_TLB1_UPDT ;3308 r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 3192 3309 } 3193 3310 } 3194 3311 } 3195 3312 break; 3313 } 3314 ////////////////////// 3315 case DCACHE_TLB1_UPDT_SEL: 3316 { 3317 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3318 3319 // external cache invalidate request 3320 if ( r_tgt_dcache_req ) 3321 { 3322 r_dcache_fsm = DCACHE_CC_CHECK; 3323 r_dcache_fsm_save = r_dcache_fsm; 3324 break; 3325 } 3326 3327 // TLB update and invalidate same PTE 3328 if ( r_dcache_inval_tlb_rsp ) 3329 { 3330 r_dcache_inval_tlb_rsp = false; 3331 r_dcache_fsm = DCACHE_IDLE; 3332 } 3333 3334 // TLB update and invalidate different PTE 3335 if ( !r_dcache_cleanup_req ) 3336 { 3337 size_t way = 0; 3338 size_t set = 0; 3339 paddr_t victim_index = 0; 3340 bool cleanup = dcache_tlb.select1((dreq.addr >> PAGE_M_NBITS),&victim_index,&way,&set); 3341 r_dcache_way = way; 3342 r_dcache_set = set; 3343 if (cleanup) 3344 { 3345 r_dcache_cleanup_req = true; 3346 r_dcache_cleanup_line = victim_index; 3347 r_dcache_cleanup_type = TLB_CLEANUP; 3348 m_cpt_cc_cleanup_data++; 3349 } 3350 r_dcache_fsm = DCACHE_TLB1_UPDT; 3351 } 3352 break; 3196 3353 } 3197 3354 ////////////////////// … … 3200 3357 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3201 3358 3202 // external cache invalidate request 3203 if ( r_tgt_dcache_req ) 3204 { 3205 r_dcache_fsm = DCACHE_CC_CHECK; 3206 r_dcache_fsm_save = r_dcache_fsm; 3207 break; 3208 } 3209 3210 // TLB update and invalidate different PTE 3211 if ( !r_dcache_inval_tlb_rsp && !r_dcache_cleanup_req) 3212 { 3213 paddr_t victim_index = 0; 3214 r_dcache_cleanup_req = dcache_tlb.update1(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index); 3215 r_dcache_cleanup_line = victim_index; 3216 r_dcache_cleanup_type = TLB_CLEANUP; 3217 m_cpt_cc_cleanup_data++; 3218 r_dcache_fsm = DCACHE_IDLE; 3219 } 3220 3221 // TLB update and invalidate same PTE 3222 if ( r_dcache_inval_tlb_rsp ) 3223 { 3224 r_dcache_inval_tlb_rsp = false; 3225 r_dcache_fsm = DCACHE_IDLE; 3226 } 3359 dcache_tlb.update(r_dcache_pte_update,dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2))); 3360 r_dcache_fsm = DCACHE_IDLE; 3227 3361 break; 3228 3362 } … … 3293 3427 { 3294 3428 r_dcache_pte_update = r_dcache_miss_buf[0]; 3295 r_dcache_fsm = DCACHE_TLB2_UPDT ;3429 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 3296 3430 } 3297 3431 else … … 3302 3436 { 3303 3437 r_dcache_pte_update = r_dcache_miss_buf[0]; 3304 r_dcache_fsm = DCACHE_TLB2_UPDT ;3438 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 3305 3439 } 3306 3440 else … … 3318 3452 { 3319 3453 r_dcache_pte_update = r_dcache_miss_buf[0]; 3320 r_dcache_fsm = DCACHE_TLB2_UPDT ;3454 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 3321 3455 } 3322 3456 else … … 3444 3578 else 3445 3579 { 3446 r_dcache_fsm = DCACHE_TLB2_UPDT ;3580 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 3447 3581 } 3448 3582 } 3449 3583 } 3450 3584 break; 3585 } 3586 ////////////////////////// 3587 case DCACHE_TLB2_UPDT_SEL: 3588 { 3589 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3590 3591 // external cache invalidate request 3592 if ( r_tgt_dcache_req ) 3593 { 3594 r_dcache_fsm = DCACHE_CC_CHECK; 3595 r_dcache_fsm_save = r_dcache_fsm; 3596 break; 3597 } 3598 3599 // TLB update and invalidate same PTE 3600 if ( r_dcache_inval_tlb_rsp ) 3601 { 3602 r_dcache_inval_tlb_rsp = false; 3603 r_dcache_fsm = DCACHE_IDLE; 3604 } 3605 3606 // TLB update and invalidate different PTE 3607 if ( !r_dcache_cleanup_req ) 3608 { 3609 size_t way = 0; 3610 size_t set = 0; 3611 paddr_t victim_index = 0; 3612 bool cleanup = dcache_tlb.select1((dreq.addr >> PAGE_K_NBITS),&victim_index,&way,&set); 3613 r_dcache_way = way; 3614 r_dcache_set = set; 3615 if (cleanup) 3616 { 3617 r_dcache_cleanup_req = true; 3618 r_dcache_cleanup_line = victim_index; 3619 r_dcache_cleanup_type = TLB_CLEANUP; 3620 m_cpt_cc_cleanup_data++; 3621 } 3622 r_dcache_fsm = DCACHE_TLB2_UPDT; 3623 } 3624 break; 3451 3625 } 3452 3626 ////////////////////// … … 3455 3629 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3456 3630 3457 // external cache invalidate request 3458 if ( r_tgt_dcache_req ) 3459 { 3460 r_dcache_fsm = DCACHE_CC_CHECK; 3461 r_dcache_fsm_save = r_dcache_fsm; 3462 break; 3463 } 3464 3465 // TLB update and invalidate different PTE 3466 if ( !r_dcache_inval_tlb_rsp && !r_dcache_cleanup_req) 3467 { 3468 paddr_t victim_index = 0; 3469 r_dcache_cleanup_req = dcache_tlb.update1(r_dcache_pte_update,r_dcache_miss_buf[1],dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index); 3470 r_dcache_cleanup_line = victim_index; 3471 r_dcache_cleanup_type = TLB_CLEANUP; 3472 m_cpt_cc_cleanup_data++; 3473 r_dcache_fsm = DCACHE_IDLE; 3474 } 3475 3476 // TLB update and invalidate same PTE 3477 if ( r_dcache_inval_tlb_rsp ) 3478 { 3479 r_dcache_inval_tlb_rsp = false; 3480 r_dcache_fsm = DCACHE_IDLE; 3481 } 3631 dcache_tlb.update(r_dcache_pte_update,r_dcache_miss_buf[1],dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2))); 3632 r_dcache_fsm = DCACHE_IDLE; 3482 3633 break; 3483 3634 } … … 3510 3661 } 3511 3662 if (clean) break; 3663 set = 0; 3512 3664 } 3513 3665 … … 3579 3731 } 3580 3732 if (clean) break; 3733 set = 0; 3581 3734 } 3582 3735 … … 3874 4027 { 3875 4028 r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK; 3876 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 3877 r_dcache_tlb_ptba_read = true; 3878 r_dcache_tlb_read_req = true; 3879 r_dcache_tlb_first_req = true; 3880 r_dcache_fsm = DCACHE_TLB1_READ; 4029 data_t ptba; 4030 if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba)) 4031 { 4032 r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 4033 r_dcache_tlb_ll_dirty_req = true; 4034 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 4035 4036 } 4037 else 4038 { 4039 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 4040 r_dcache_tlb_ptba_read = true; 4041 r_dcache_tlb_read_req = true; 4042 r_dcache_tlb_first_req = true; 4043 r_dcache_fsm = DCACHE_TLB1_READ; 4044 } 3881 4045 } 3882 4046 } … … 3906 4070 { 3907 4071 r_dcache_fsm = DCACHE_IDLE; 4072 if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false; 3908 4073 r_dcache_inval_tlb_rsp = false; 3909 4074 break; 3910 4075 } 3911 4076 dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save); 3912 r_dcache_fsm = DCACHE_WRITE_REQ; 3913 drsp.valid = true; 3914 drsp.rdata = 0; 4077 if ( r_dcache_sc_updt_dirty ) 4078 { 4079 r_dcache_sc_updt_dirty = false; 4080 r_dcache_unc_req = true; 4081 r_dcache_fsm = DCACHE_UNC_WAIT; 4082 m_cpt_unc_read++; 4083 } 4084 else 4085 { 4086 r_dcache_fsm = DCACHE_WRITE_REQ; 4087 drsp.valid = true; 4088 drsp.rdata = 0; 4089 } 3915 4090 break; 3916 4091 } … … 4093 4268 ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT ) || 4094 4269 ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT ) || 4095 ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT )||4270 ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT_SEL ) || 4096 4271 ( r_dcache_fsm_save.read() == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_SC_DIRTY_WAIT ) || 4097 4272 ( r_dcache_fsm_save.read() == DCACHE_WRITE_DIRTY )) && … … 4111 4286 ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT ) || 4112 4287 ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT ) || 4113 ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT )||4288 ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT_SEL ) || 4114 4289 ( r_dcache_fsm_save.read() == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_SC_DIRTY_WAIT ) || 4115 4290 ( r_dcache_fsm_save.read() == DCACHE_WRITE_DIRTY )) && … … 5099 5274 << "p_vci_tgt.reop:" << p_vci_tgt.reop 5100 5275 << std::endl; 5101 5102 5276 #endif 5103 5277 }
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