Changeset 140 for trunk/modules/vci_cc_xcache_wrapper_v4/caba
- Timestamp:
- Mar 9, 2011, 4:11:43 PM (14 years ago)
- Location:
- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_xcache_wrapper_v4.h (modified) (12 diffs)
-
src/vci_cc_xcache_wrapper_v4.cpp (modified) (118 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r134 r140 31 31 32 32 #include <inttypes.h> 33 #include <fstream> 33 34 #include <systemc> 34 35 #include <queue> … … 71 72 * 4 - one access with round robin priority 72 73 * 74 * CC_XCACHE_WRAPPER_MULTI_CACHE : 75 * 1 - icache static partitionnement 76 * 2 - icache dedicated 77 * 73 78 * CC_XCACHE_WRAPPER_STOP_SIMULATION : 74 79 * stop simulation if processor is stall after a long time … … 81 86 * Number of cycle before to prinf debug message 82 87 * 83 * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 84 * Print transaction between the cpu and the cache 88 * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 89 * Print transaction between : 90 * - the cpu and the cache (icache and dcache) 91 * - vci 92 * - cleanup 93 * - coherency 85 94 */ 86 95 87 96 // implementation 88 97 #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM 89 #define CC_XCACHE_WRAPPER_SELECT_VICTIM 098 #define CC_XCACHE_WRAPPER_SELECT_VICTIM 1 90 99 #endif 91 100 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP 92 #define CC_XCACHE_WRAPPER_FIFO_RSP 0101 #define CC_XCACHE_WRAPPER_FIFO_RSP 1 93 102 #endif 94 103 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 95 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1104 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 96 105 #endif 97 106 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 98 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1107 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 99 108 #endif 100 109 #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 101 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 0110 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 2 102 111 #endif 103 112 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 104 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 2 113 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 4 114 #endif 115 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE 116 #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 105 117 #endif 106 118 // debugging 107 119 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION 108 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1120 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 109 121 #endif 110 122 #ifndef CC_XCACHE_WRAPPER_DEBUG 111 #define CC_XCACHE_WRAPPER_DEBUG 0123 #define CC_XCACHE_WRAPPER_DEBUG 0 112 124 #endif 113 125 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 114 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 200000 115 #endif 116 #ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 117 #define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 0 126 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 949900 127 #endif 128 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 129 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 130 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" 131 #endif 132 133 // don't change 134 #if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 135 #undef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 136 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 0 118 137 #endif 119 138 … … 204 223 enum cleanup_fsm_state_e { 205 224 CLEANUP_IDLE, 206 CLEANUP_DCACHE, 207 CLEANUP_ICACHE, 225 CLEANUP_REQ, 226 CLEANUP_RSP_DCACHE, 227 CLEANUP_RSP_ICACHE, 208 228 }; 209 229 … … 231 251 sc_in<bool> p_clk; 232 252 sc_in<bool> p_resetn; 233 sc_in<bool> p_irq[iss_t::n_irq];253 sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq]; 234 254 soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; 235 255 soclib::caba::VciInitiator<vci_param> p_vci_ini_c; … … 241 261 const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; 242 262 const soclib::common::Segment m_segment; 243 iss_t m_iss;263 iss_t ** m_iss; //[m_nb_cpu] 244 264 const uint32_t m_srcid_rw; 245 265 const uint32_t m_srcid_c; 246 266 267 const size_t m_nb_cpu; 268 const size_t m_nb_icache; 269 const size_t m_nb_dcache; 270 const size_t m_nb_cache; 247 271 const size_t m_dcache_ways; 248 272 const size_t m_dcache_words; … … 258 282 bool m_stop_simulation; 259 283 uint32_t m_stop_simulation_nb_frz_cycles_max; 260 uint32_t m_stop_simulation_nb_frz_cycles;284 uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu] 261 285 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 262 286 263 287 // REGISTERS 264 sc_signal<int> r_dcache_fsm; 265 sc_signal<int> r_dcache_fsm_save; 266 sc_signal<addr_40> r_dcache_addr_save; 267 sc_signal<data_t> r_dcache_wdata_save; 268 sc_signal<data_t> r_dcache_rdata_save; 269 sc_signal<int> r_dcache_type_save; 270 sc_signal<be_t> r_dcache_be_save; 271 sc_signal<bool> r_dcache_cached_save; 272 sc_signal<bool> r_dcache_cleanup_req; 273 sc_signal<addr_40> r_dcache_cleanup_line; 274 sc_signal<bool> r_dcache_miss_req; 275 sc_signal<size_t> r_dcache_miss_way; 276 sc_signal<size_t> r_dcache_miss_set; 277 sc_signal<bool> r_dcache_unc_req; 278 sc_signal<bool> r_dcache_sc_req; 279 sc_signal<bool> r_dcache_inval_rsp; 280 sc_signal<size_t> r_dcache_update_addr; 281 sc_signal<data_64> r_dcache_ll_data; 282 sc_signal<addr_40> r_dcache_ll_addr; 283 sc_signal<bool> r_dcache_ll_valid; 284 sc_signal<bool> r_dcache_previous_unc; 285 286 sc_signal<int> r_icache_fsm; 287 sc_signal<int> r_icache_fsm_save; 288 sc_signal<addr_40> r_icache_addr_save; 289 sc_signal<bool> r_icache_miss_req; 290 sc_signal<size_t> r_icache_miss_way; 291 sc_signal<size_t> r_icache_miss_set; 292 sc_signal<bool> r_icache_unc_req; 293 sc_signal<bool> r_icache_cleanup_req; 294 sc_signal<addr_40> r_icache_cleanup_line; 295 sc_signal<bool> r_icache_inval_rsp; 296 sc_signal<size_t> r_icache_update_addr; 288 sc_signal<uint32_t> r_cpu_prior; 289 sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache] 290 sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache] 291 sc_signal<bool> * r_dcache_sync;//[m_nb_dcache] 292 293 sc_signal<int> * r_dcache_fsm; //[m_nb_dcache] 294 sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache] 295 sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache] 296 sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache] 297 sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache] 298 sc_signal<int> * r_dcache_type_save; //[m_nb_dcache] 299 sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache] 300 sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache] 301 sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache] 302 sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache] 303 sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache] 304 sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache] 305 sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache] 306 sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache] 307 sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache] 308 sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache] 309 sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache] 310 sc_signal<data_64> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] 311 sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] 312 sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] 313 sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache] 314 sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache] 315 316 sc_signal<int> * r_icache_fsm; //[m_nb_icache] 317 sc_signal<int> * r_icache_fsm_save; //[m_nb_icache] 318 sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache] 319 sc_signal<bool> * r_icache_miss_req; //[m_nb_icache] 320 sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache] 321 sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache] 322 sc_signal<bool> * r_icache_unc_req; //[m_nb_icache] 323 sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache] 324 sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache] 325 sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache] 326 sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache] 327 sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache] 297 328 298 329 sc_signal<int> r_vci_cmd_fsm; … … 301 332 sc_signal<size_t> r_vci_cmd_cpt; 302 333 sc_signal<bool> r_vci_cmd_dcache_prior; 303 334 sc_signal<uint32_t> r_vci_cmd_num_cache; 335 304 336 sc_signal<int> r_vci_rsp_fsm; 305 sc_signal<bool> r_vci_rsp_ins_error;306 sc_signal<bool> r_vci_rsp_data_error;307 337 sc_signal<size_t> r_vci_rsp_cpt; 308 sc_signal<bool> r_vci_rsp_ack; 338 bool s_vci_rsp_ack; 339 sc_signal<uint32_t> r_vci_rsp_num_cache; 340 sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache] 341 sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] 309 342 310 343 #if CC_XCACHE_WRAPPER_FIFO_RSP 311 std::queue<data_t> r_icache_miss_buf;312 std::queue<data_t> r_dcache_miss_buf;344 std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache] 345 std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache] 313 346 #else 314 bool *r_icache_miss_val; //[m_icache_words] 315 data_t *r_icache_miss_buf; //[m_icache_words] 316 bool *r_dcache_miss_val; //[m_dcache_words] 317 data_t *r_dcache_miss_buf; //[m_dcache_words] 318 #endif 319 sc_signal<bool> r_icache_buf_unc_valid; 320 321 data_t *r_tgt_buf; //[m_cache_words] 322 be_t *r_tgt_be; //[m_cache_words] 347 bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words] 348 data_t ** r_icache_miss_buf; //[m_nb_icache][m_icache_words] 349 bool ** r_dcache_miss_val; //[m_nb_dcache][m_dcache_words] 350 data_t ** r_dcache_miss_buf; //[m_nb_dcache][m_dcache_words] 351 #endif 352 data_t * r_tgt_buf; //[m_cache_words] 353 be_t * r_tgt_be; //[m_cache_words] 323 354 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 324 355 sc_signal<uint32_t> r_cache_word; … … 326 357 327 358 sc_signal<int> r_vci_tgt_fsm; 328 sc_signal<addr_40> r_tgt_addr; 359 sc_signal<addr_40> r_tgt_iaddr; 360 sc_signal<addr_40> r_tgt_daddr; 329 361 sc_signal<size_t> r_tgt_word; 330 362 sc_signal<bool> r_tgt_update; … … 335 367 sc_signal<size_t> r_tgt_trdid; 336 368 //sc_signal<size_t> r_tgt_plen; 337 sc_signal<bool> r_tgt_icache_req; 338 sc_signal<bool> r_tgt_dcache_req; 339 sc_signal<bool> r_tgt_icache_rsp; 340 sc_signal<bool> r_tgt_dcache_rsp; 369 sc_signal<uint32_t> r_tgt_num_cache; 370 sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache] 371 sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache] 372 sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache] 373 sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache] 341 374 342 375 sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network 343 344 MultiWriteBuffer<addr_40> r_wbuf; 345 GenericCache<vci_addr_t> r_icache; 346 GenericCache<vci_addr_t> r_dcache; 347 348 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 349 std::ofstream log_dcache_transaction_file; 376 sc_signal<uint32_t> r_cleanup_num_cache; 377 sc_signal<bool> r_cleanup_icache; 378 379 MultiWriteBuffer<addr_40>** r_wbuf; 380 GenericCache<vci_addr_t> ** r_icache; 381 GenericCache<vci_addr_t> ** r_dcache; 382 383 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 384 std::ofstream * log_transaction_file_icache; //[m_nb_cpu] 385 std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] 386 std::ofstream log_transaction_file_cmd; 387 std::ofstream log_transaction_file_tgt; 388 std::ofstream log_transaction_file_cleanup; 350 389 #endif 351 390 352 391 // Activity counters 353 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 354 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 355 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 356 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 357 358 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 359 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 360 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 361 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 362 363 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 364 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 365 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 366 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 367 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 368 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 369 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 370 371 uint32_t m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 372 uint32_t m_cpt_total_cycles; // total number of cycles 373 374 uint32_t m_cpt_data_read; // number of data read 375 uint32_t m_cpt_data_read_miss; // number of data read miss 376 uint32_t m_cpt_data_read_uncached; // number of data read uncached 377 uint32_t m_cpt_data_write; // number of data write 378 uint32_t m_cpt_data_write_miss; // number of data write miss 379 uint32_t m_cpt_data_write_uncached; // number of data write uncached 380 uint32_t m_cpt_ins_miss; // * number of instruction miss 381 382 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 383 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 384 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 385 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 386 387 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 388 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 389 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 390 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 391 392 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 393 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 394 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 395 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 396 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 392 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 393 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 394 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 395 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 396 397 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 398 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 399 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 400 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 401 402 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 403 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 404 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 405 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 406 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 407 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 408 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 409 410 uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 411 uint32_t m_cpt_total_cycles; // total number of cycles 412 413 uint32_t m_cpt_data_read; // number of data read 414 uint32_t m_cpt_data_read_miss; // number of data read miss 415 uint32_t m_cpt_data_read_uncached; // number of data read uncached 416 uint32_t m_cpt_data_write; // number of data write 417 uint32_t m_cpt_data_write_miss; // number of data write miss 418 uint32_t m_cpt_data_write_uncached; // number of data write uncached 419 uint32_t m_cpt_ins_miss; // * number of instruction miss 420 421 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 422 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 423 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 424 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 425 426 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 427 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 428 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 429 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 430 431 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 432 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 433 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 434 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 435 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 436 437 uint32_t * m_cpt_icache_access; //[m_nb_icache] 438 uint32_t * m_cpt_dcache_access; //[m_nb_dcache] 439 440 uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] 441 uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] 442 uint32_t * m_cpt_fsm_cmd; 443 uint32_t * m_cpt_fsm_rsp; 444 uint32_t * m_cpt_fsm_tgt; 445 uint32_t * m_cpt_fsm_cleanup; 446 447 // Non blocking multi-cache 448 typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] 449 typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] 450 bool * ireq_cached ; //[m_nb_icache] 451 uint32_t * ireq_num_cpu; //[m_nb_dcache] 452 typename iss_t::DataRequest * dreq ; //[m_nb_dcache] 453 typename iss_t::DataResponse * drsp ; //[m_nb_dcache] 454 bool * dreq_cached ; //[m_nb_dcache] 455 uint32_t * dreq_num_cpu; //[m_nb_dcache] 456 457 const uint32_t m_num_cache_LSB; 458 const uint32_t m_num_cache_MSB; 459 addr_40 m_num_cache_LSB_mask; 460 addr_40 m_num_cache_mask; 397 461 398 462 protected: … … 409 473 const soclib::common::IntTab &initiator_index_c, 410 474 const soclib::common::IntTab &target_index, 475 size_t nb_cpu, 476 size_t nb_cache, 411 477 size_t icache_ways, 412 478 size_t icache_sets, … … 435 501 void genMoore(); 436 502 437 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); 503 uint32_t get_num_cache (addr_40 & addr); 504 uint32_t get_num_cache_only(addr_40 addr); 505 void set_num_cache (addr_40 & addr, uint32_t num_cache); 506 addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache); 507 508 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); 438 509 soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); 439 510 }; -
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
r134 r140 55 55 /////////////////////////////////////////////////////////////////////////////// 56 56 57 #include <cassert>58 57 #include <iomanip> 59 58 #include "arithmetics.h" 59 #include "size.h" 60 60 #include "../include/vci_cc_xcache_wrapper_v4.h" 61 61 62 // =====[ DEBUG ]==================================== 63 64 #define ASSERT_VERBOSE 65 #define ASSERT_NCYCLES m_cpt_total_cycles 66 67 #include "debug.h" 68 62 69 #if CC_XCACHE_WRAPPER_DEBUG 63 # define PRINTF(msg...) do { if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) printf(msg); } while (0);70 # define PRINTF(msg...) PRINTF_COND(m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN,msg) 64 71 #else 65 72 # define PRINTF(msg...) 66 73 #endif 67 74 68 # define ASSERT(cond,msg) assert ((cond) and msg); 69 75 // =====[ FIFO_RSP ]================================= 76 77 // FIXME : une FIFO avec le numéro du cache ! 70 78 #if CC_XCACHE_WRAPPER_FIFO_RSP 71 # define CACHE_MISS_BUF_ALLOC 72 # define CACHE_MISS_BUF_DEALLOC 73 # define CACHE_MISS_BUF_RESET(c) while (r_##c##cache_miss_buf.size()>0) {r_##c##cache_miss_buf.pop();} 74 # define CACHE_MISS_BUF_REQ_INIT(c) 75 # define CACHE_MISS_BUF_RSP_VAL(c,n) (r_##c##cache_miss_buf.size()>0) 76 # define CACHE_MISS_BUF_RSP_ACK(c) (r_##c##cache_miss_buf.size()<2) 77 # define CACHE_MISS_BUF_RSP_DATA(c,n) r_##c##cache_miss_buf.front() 78 # define CACHE_MISS_BUF_RSP_POP(c) do { r_##c##cache_miss_buf.pop();} while (0) 79 # define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do { r_##c##cache_miss_buf.push(d);} while (0) 80 # define CACHE_MISS_BUF_RSP_PRINT(c) do { PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size());} while (0) 79 # define CACHE_MISS_BUF_ALLOC do { \ 80 r_icache_miss_buf = new std::queue<data_t> [m_nb_icache]; \ 81 r_dcache_miss_buf = new std::queue<data_t> [m_nb_dcache]; \ 82 } while (0) 83 # define CACHE_MISS_BUF_DEALLOC do { \ 84 delete [] r_icache_miss_buf; \ 85 delete [] r_dcache_miss_buf; \ 86 } while (0) 87 # define CACHE_MISS_BUF_RESET(c) do { \ 88 for (uint32_t x=0; x<m_nb_##c##cache; ++x) { \ 89 while (r_##c##cache_miss_buf[x].size()>0) { \ 90 r_##c##cache_miss_buf[x].pop(); \ 91 } \ 92 } \ 93 } while (0) 94 # define CACHE_MISS_BUF_REQ_INIT(c,x) 95 # define CACHE_MISS_BUF_RSP_VAL(c,x,n) (r_##c##cache_miss_buf[x].size()>0) 96 # define CACHE_MISS_BUF_RSP_ACK(c,x) (r_##c##cache_miss_buf[x].size()<2) 97 # define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf[x].front() 98 # define CACHE_MISS_BUF_RSP_POP(c,x) do { \ 99 r_##c##cache_miss_buf[x].pop(); \ 100 } while (0) 101 # define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ 102 r_##c##cache_miss_buf[x].push(d); \ 103 } while (0) 104 # define CACHE_MISS_BUF_RSP_PRINT(c) do { \ 105 for (uint32_t x=0; x<m_nb_##c##cache; ++x) { \ 106 PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf[x].size()); \ 107 } \ 108 } while (0) 109 #else 110 # define CACHE_MISS_BUF_ALLOC do { \ 111 r_icache_miss_val = new bool * [m_nb_icache]; \ 112 r_icache_miss_buf = new data_t * [m_nb_icache]; \ 113 for (uint32_t x=0; x<m_nb_icache;++x) { \ 114 r_icache_miss_val [x] = new bool [m_icache_words]; \ 115 r_icache_miss_buf [x] = new data_t [m_icache_words]; \ 116 } \ 117 r_dcache_miss_val = new bool * [m_nb_dcache]; \ 118 r_dcache_miss_buf = new data_t * [m_nb_dcache]; \ 119 for (uint32_t x=0; x<m_nb_dcache;++x) { \ 120 r_dcache_miss_val [x] = new bool [m_dcache_words]; \ 121 r_dcache_miss_buf [x] = new data_t [m_dcache_words]; \ 122 } \ 123 } while (0) 124 # define CACHE_MISS_BUF_DEALLOC do { \ 125 for (uint32_t x=0; x<m_nb_icache;++x) { \ 126 delete [] r_icache_miss_val[x]; \ 127 delete [] r_icache_miss_buf[x]; \ 128 } \ 129 delete [] r_icache_miss_val; \ 130 delete [] r_icache_miss_buf; \ 131 for (uint32_t x=0; x<m_nb_dcache;++x) { \ 132 delete [] r_dcache_miss_val[x]; \ 133 delete [] r_dcache_miss_buf[x]; \ 134 } \ 135 delete [] r_dcache_miss_val; \ 136 delete [] r_dcache_miss_buf; \ 137 } while (0) 138 # define CACHE_MISS_BUF_RESET(c) 139 # define CACHE_MISS_BUF_REQ_INIT(c,x) do { \ 140 for (uint32_t i=0; i<m_##c##cache_words;++i) \ 141 r_##c##cache_miss_val[x][i] = false; \ 142 } while (0) 143 # define CACHE_MISS_BUF_RSP_VAL(c,x,n) r_##c##cache_miss_val[x][n] 144 # define CACHE_MISS_BUF_RSP_ACK(c,x) true 145 # define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf[x][n] 146 # define CACHE_MISS_BUF_RSP_POP(c,x) 147 # define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ 148 r_##c##cache_miss_val[x][n] = true; \ 149 r_##c##cache_miss_buf[x][n] = d; \ 150 } while (0) 151 # define CACHE_MISS_BUF_RSP_PRINT(c) do { \ 152 for (uint32_t x=0; x<m_nb_##c##cache;++x) \ 153 for (uint32_t i=0; i<m_##c##cache_words;++i) \ 154 PRINTF("%d %x |",r_##c##cache_miss_val[x][i],r_##c##cache_miss_buf[x][i]); PRINTF("\n"); \ 155 } while (0) 156 #endif 157 158 // =====[ MULTI_CACHE ]============================== 159 160 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 161 # define get_num_icache( addr,num_cpu) get_num_cache (addr) 162 # define get_num_icache_only(addr,num_cpu) get_num_cache_only(addr) 163 # define set_num_icache( addr,num_cache) set_num_cache (addr,num_cache) 164 # define set_num_icache_only(addr,num_cache) set_num_cache_only(addr,num_cache) 165 # define get_num_dcache( addr) get_num_cache (addr) 166 # define get_num_dcache_only(addr) get_num_cache_only(addr) 167 # define set_num_dcache( addr,num_cache) set_num_cache (addr,num_cache) 168 # define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache) 169 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 170 # define get_num_icache( addr,num_cpu) num_cpu 171 # define get_num_icache_only(addr,num_cpu) num_cpu 172 # define set_num_icache( addr,num_cache) do {} while (0) 173 # define set_num_icache_only(addr,num_cache) addr 174 # define get_num_dcache( addr) get_num_cache (addr) 175 # define get_num_dcache_only(addr) get_num_cache_only(addr) 176 # define set_num_dcache( addr,num_cache) set_num_cache (addr,num_cache) 177 # define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache) 81 178 #else 82 # define CACHE_MISS_BUF_ALLOC do { \ 83 r_icache_miss_val = new bool [m_icache_words]; \ 84 r_icache_miss_buf = new data_t[m_icache_words]; \ 85 r_dcache_miss_val = new bool [m_dcache_words]; \ 86 r_dcache_miss_buf = new data_t[m_dcache_words]; \ 87 } while (0) 88 # define CACHE_MISS_BUF_DEALLOC do { \ 89 delete [] r_icache_miss_val; \ 90 delete [] r_icache_miss_buf; \ 91 delete [] r_dcache_miss_val; \ 92 delete [] r_dcache_miss_buf; \ 93 } while (0) 94 # define CACHE_MISS_BUF_RESET(c) 95 # define CACHE_MISS_BUF_REQ_INIT(c) do {for (uint32_t i=0; i<m_##c##cache_words;++i) r_##c##cache_miss_val[i] = false;} while (0) 96 # define CACHE_MISS_BUF_RSP_VAL(c,n) r_##c##cache_miss_val[n] 97 # define CACHE_MISS_BUF_RSP_ACK(c) true 98 # define CACHE_MISS_BUF_RSP_DATA(c,n) r_##c##cache_miss_buf[n] 99 # define CACHE_MISS_BUF_RSP_POP(c) 100 # define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do {r_##c##cache_miss_val[n] = true; r_##c##cache_miss_buf[n] = d;} while (0) 101 # define CACHE_MISS_BUF_RSP_PRINT(c) do {for (uint32_t i=0; i<m_##c##cache_words;++i) PRINTF("%d %x |",r_##c##cache_miss_val[i],r_##c##cache_miss_buf[i]); PRINTF("\n");} while (0) 179 #error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE" 102 180 #endif 103 181 … … 170 248 const char *cleanup_fsm_state_str[] = { 171 249 "CLEANUP_IDLE", 172 "CLEANUP_DCACHE", 173 "CLEANUP_ICACHE", 250 "CLEANUP_REQ", 251 "CLEANUP_RSP_DCACHE", 252 "CLEANUP_RSP_ICACHE", 174 253 }; 175 254 } … … 189 268 const soclib::common::IntTab &initiator_index_c, 190 269 const soclib::common::IntTab &target_index, 270 size_t nb_cpu, 271 size_t nb_dcache, 191 272 size_t icache_ways, 192 273 size_t icache_sets, … … 210 291 m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()), 211 292 m_segment(mtc.getSegment(target_index)), 212 m_iss(this->name(), proc_id),213 293 m_srcid_rw(mtp.indexForId(initiator_index_rw)), 214 294 m_srcid_c(mtc.indexForId(initiator_index_c)), 215 295 296 m_nb_cpu(nb_cpu), 297 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 298 m_nb_icache(nb_dcache), 299 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 300 m_nb_icache(m_nb_cpu), 301 #endif 302 m_nb_dcache(nb_dcache), 303 m_nb_cache((m_nb_dcache>m_nb_icache)?m_nb_dcache:m_nb_icache), 216 304 m_dcache_ways(dcache_ways), 217 305 m_dcache_words(dcache_words), 218 m_dcache_words_shift(uint32_log2(dcache_words)+ 2),306 m_dcache_words_shift(uint32_log2(dcache_words)+uint32_log2(sizeof(data_t))), 219 307 m_dcache_yzmask((~0)<<m_dcache_words_shift), 220 308 m_icache_ways(icache_ways), 221 309 m_icache_words(icache_words), 222 m_icache_words_shift(uint32_log2(icache_words)+ 2),310 m_icache_words_shift(uint32_log2(icache_words)+uint32_log2(sizeof(data_t))), 223 311 m_icache_yzmask((~0)<<m_icache_words_shift), 224 312 m_cache_words((dcache_words)?dcache_words:icache_words), 225 313 226 r_dcache_fsm("r_dcache_fsm"), 227 r_dcache_fsm_save("r_dcache_fsm_save"), 228 r_dcache_addr_save("r_dcache_addr_save"), 229 r_dcache_wdata_save("r_dcache_wdata_save"), 230 r_dcache_rdata_save("r_dcache_rdata_save"), 231 r_dcache_type_save("r_dcache_type_save"), 232 r_dcache_be_save("r_dcache_be_save"), 233 r_dcache_cached_save("r_dcache_cached_save"), 234 r_dcache_cleanup_req("r_dcache_cleanup_req"), 235 r_dcache_cleanup_line("r_dcache_cleanup_line"), 236 r_dcache_miss_req("r_dcache_miss_req"), 237 r_dcache_miss_way("r_dcache_miss_way"), 238 r_dcache_miss_set("r_dcache_miss_set"), 239 r_dcache_unc_req("r_dcache_unc_req"), 240 r_dcache_sc_req("r_dcache_sc_req"), 241 r_dcache_inval_rsp("r_dcache_inval_rsp"), 242 r_dcache_update_addr("r_dcache_update_addr"), 243 r_dcache_ll_data("r_dcache_ll_data"), 244 r_dcache_ll_addr("r_dcache_ll_addr"), 245 r_dcache_ll_valid("r_dcache_ll_valid"), 246 r_dcache_previous_unc("r_dcache_previous_unc"), 247 248 r_icache_fsm("r_icache_fsm"), 249 r_icache_fsm_save("r_icache_fsm_save"), 250 r_icache_addr_save("r_icache_addr_save"), 251 r_icache_miss_req("r_icache_miss_req"), 252 r_icache_miss_way("r_icache_miss_way"), 253 r_icache_miss_set("r_icache_miss_set"), 254 r_icache_unc_req("r_icache_unc_req"), 255 r_icache_cleanup_req("r_icache_cleanup_req"), 256 r_icache_cleanup_line("r_icache_cleanup_line"), 257 r_icache_inval_rsp("r_icache_inval_rsp"), 258 r_icache_update_addr("r_icache_update_addr"), 314 r_cpu_prior("r_cpu_prior"), 259 315 260 316 r_vci_cmd_fsm("r_vci_cmd_fsm"), … … 263 319 r_vci_cmd_cpt("r_vci_cmd_cpt"), 264 320 r_vci_cmd_dcache_prior("r_vci_cmd_dcache_prior"), 321 r_vci_cmd_num_cache("r_vci_cmd_num_cache"), 265 322 266 323 r_vci_rsp_fsm("r_vci_rsp_fsm"), 267 r_vci_rsp_ins_error("r_vci_rsp_ins_error"),268 r_vci_rsp_data_error("r_vci_rsp_data_error"),269 324 r_vci_rsp_cpt("r_vci_rsp_cpt"), 270 r_vci_rsp_ack("r_vci_rsp_ack"), 271 272 r_icache_buf_unc_valid("r_icache_buf_unc_valid"), 325 //s_vci_rsp_ack("s_vci_rsp_ack"), 326 r_vci_rsp_num_cache("r_vci_rsp_num_cache"), 273 327 274 328 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 277 331 278 332 r_vci_tgt_fsm("r_vci_tgt_fsm"), 279 r_tgt_addr("r_tgt_addr"), 333 r_tgt_iaddr("r_tgt_iaddr"), 334 r_tgt_daddr("r_tgt_daddr"), 280 335 r_tgt_word("r_tgt_word"), 281 336 r_tgt_update("r_tgt_update"), … … 286 341 r_tgt_trdid("r_tgt_trdid"), 287 342 // r_tgt_plen("r_tgt_plen"), 288 r_tgt_icache_req("r_tgt_icache_req"), 289 r_tgt_dcache_req("r_tgt_dcache_req"), 290 r_tgt_icache_rsp("r_tgt_icache_rsp"), 291 r_tgt_dcache_rsp("r_tgt_dcache_rsp"), 343 r_tgt_num_cache("r_tgt_num_cache"), 292 344 293 345 r_cleanup_fsm("r_cleanup_fsm"), 294 295 r_wbuf("r_wbuf", wbuf_nwords, wbuf_nlines, wbuf_timeout, dcache_words), 296 r_icache("icache", icache_ways, icache_sets, icache_words), 297 r_dcache("dcache", dcache_ways, dcache_sets, dcache_words) 346 r_cleanup_num_cache("r_cleanup_num_cache"), 347 r_cleanup_icache("r_cleanup_icache"), 348 349 m_num_cache_LSB(uint32_log2(icache_words) + uint32_log2(sizeof(data_t))), 350 m_num_cache_MSB(uint32_log2(nb_dcache) + m_num_cache_LSB) 298 351 { 299 352 // Size of word is 32 bits 300 ASSERT( (icache_words*vci_param::B) < (1<<vci_param::K), 301 "I need more PLEN bits"); 302 303 ASSERT( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= wbuf_nlines), 304 "I need more TRDID bits"); 305 353 ASSERT((icache_words*vci_param::B) < (1<<vci_param::K), 354 "Need more PLEN bits."); 355 356 ASSERT((vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines/m_nb_dcache)), 357 "Need more TRDID bits."); 358 359 ASSERT(uint32_log2(nb_dcache) <= (1<<vci_param::P), 360 "Need more PKTID bits."); 361 362 ASSERT(IS_POW_OF_2(m_nb_dcache), 363 "nb_dcache must be a power of 2."); 364 365 ASSERT(IS_POW_OF_2(m_nb_cpu) and (m_nb_cpu <= m_nb_dcache) and (m_nb_cpu > 0), 366 "nb cpu must be a multiple of nb cache."); 367 368 ASSERT(IS_POW_OF_2(m_icache_ways) and (m_nb_icache <= m_icache_ways), 369 "nb icache ways must be a multiple of nb cache."); 370 371 ASSERT(IS_POW_OF_2(m_dcache_ways) and (m_nb_dcache <= m_dcache_ways), 372 "nb dcache ways must be a multiple of nb cache."); 373 374 ASSERT(icache_words == dcache_words, 375 "icache_words must be equal at dcache_words."); 376 377 ASSERT(IS_POW_OF_2(wbuf_nlines) and (m_nb_dcache <= wbuf_nlines), 378 "wbuf_nlines must be a multiple of nb cache."); 379 380 // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE 381 ASSERT((m_nb_dcache == 1) or (dcache_words >= 16), 382 "When multi cache is activated, need 4 bits (16 word) to the cache set ."); 383 384 p_irq = new sc_in<bool> * [m_nb_cpu]; 385 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 386 p_irq [num_cpu] = new sc_in<bool> [iss_t::n_irq]; 387 388 m_iss = new iss_t * [m_nb_cpu]; 389 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 390 { 391 std::ostringstream iss_name(""); 392 iss_name << this->name() << "_" << num_cpu; 393 394 m_iss[num_cpu] = new iss_t (iss_name.str().c_str(), proc_id+num_cpu); 395 } 396 306 397 CACHE_MISS_BUF_ALLOC; 307 398 308 r_tgt_buf = new data_t[m_cache_words]; 309 r_tgt_be = new be_t [m_cache_words]; 399 r_icache_lock = new sc_signal<uint32_t>[m_nb_icache]; 400 r_dcache_lock = new sc_signal<uint32_t>[m_nb_dcache]; 401 r_dcache_sync = new sc_signal<bool> [m_nb_dcache]; 402 403 r_icache_fsm = new sc_signal<int> [m_nb_icache]; 404 r_icache_fsm_save = new sc_signal<int> [m_nb_icache]; 405 r_icache_addr_save = new sc_signal<addr_40> [m_nb_icache]; 406 r_icache_miss_req = new sc_signal<bool> [m_nb_icache]; 407 r_icache_miss_way = new sc_signal<size_t> [m_nb_icache]; 408 r_icache_miss_set = new sc_signal<size_t> [m_nb_icache]; 409 r_icache_unc_req = new sc_signal<bool> [m_nb_icache]; 410 r_icache_cleanup_req = new sc_signal<bool> [m_nb_icache]; 411 r_icache_cleanup_line = new sc_signal<addr_40> [m_nb_icache]; 412 r_icache_inval_rsp = new sc_signal<bool> [m_nb_icache]; 413 r_icache_update_addr = new sc_signal<size_t> [m_nb_icache]; 414 r_icache_buf_unc_valid = new sc_signal<bool> [m_nb_icache]; 415 416 r_dcache_fsm = new sc_signal<int> [m_nb_dcache]; 417 r_dcache_fsm_save = new sc_signal<int> [m_nb_dcache]; 418 r_dcache_addr_save = new sc_signal<addr_40> [m_nb_dcache]; 419 r_dcache_wdata_save = new sc_signal<data_t> [m_nb_dcache]; 420 r_dcache_rdata_save = new sc_signal<data_t> [m_nb_dcache]; 421 r_dcache_type_save = new sc_signal<int> [m_nb_dcache]; 422 r_dcache_be_save = new sc_signal<be_t> [m_nb_dcache]; 423 r_dcache_cached_save = new sc_signal<bool> [m_nb_dcache]; 424 r_dcache_cleanup_req = new sc_signal<bool> [m_nb_dcache]; 425 r_dcache_cleanup_line = new sc_signal<addr_40> [m_nb_dcache]; 426 r_dcache_miss_req = new sc_signal<bool> [m_nb_dcache]; 427 r_dcache_miss_way = new sc_signal<size_t> [m_nb_dcache]; 428 r_dcache_miss_set = new sc_signal<size_t> [m_nb_dcache]; 429 r_dcache_unc_req = new sc_signal<bool> [m_nb_dcache]; 430 r_dcache_sc_req = new sc_signal<bool> [m_nb_dcache]; 431 r_dcache_inval_rsp = new sc_signal<bool> [m_nb_dcache]; 432 r_dcache_update_addr = new sc_signal<size_t> [m_nb_dcache]; 433 r_dcache_previous_unc = new sc_signal<bool> [m_nb_dcache]; 434 435 r_dcache_num_cpu_save = new sc_signal<uint32_t> [m_nb_dcache]; 436 r_dcache_ll_data = new sc_signal<data_64> * [m_nb_dcache]; 437 r_dcache_ll_addr = new sc_signal<addr_40> * [m_nb_dcache]; 438 r_dcache_ll_valid = new sc_signal<bool> * [m_nb_dcache]; 439 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 440 { 441 r_dcache_ll_data [num_cache] = new sc_signal<data_64> [m_nb_cpu]; 442 r_dcache_ll_addr [num_cache] = new sc_signal<addr_40> [m_nb_cpu]; 443 r_dcache_ll_valid [num_cache] = new sc_signal<bool> [m_nb_cpu]; 444 } 445 446 r_tgt_icache_req = new sc_signal<bool> [m_nb_icache]; 447 r_tgt_icache_rsp = new sc_signal<bool> [m_nb_icache]; 448 r_tgt_dcache_req = new sc_signal<bool> [m_nb_dcache]; 449 r_tgt_dcache_rsp = new sc_signal<bool> [m_nb_dcache]; 450 451 r_tgt_buf = new data_t [m_cache_words]; 452 r_tgt_be = new be_t [m_cache_words]; 453 454 r_vci_rsp_ins_error = new sc_signal<bool> [m_nb_icache]; 455 r_vci_rsp_data_error = new sc_signal<bool> [m_nb_dcache]; 456 457 ireq = new typename iss_t::InstructionRequest [m_nb_icache]; 458 irsp = new typename iss_t::InstructionResponse [m_nb_icache]; 459 ireq_cached = new bool [m_nb_icache]; 460 ireq_num_cpu = new uint32_t [m_nb_dcache]; 461 462 dreq = new typename iss_t::DataRequest [m_nb_dcache]; 463 drsp = new typename iss_t::DataResponse [m_nb_dcache]; 464 dreq_cached = new bool [m_nb_dcache]; 465 dreq_num_cpu = new uint32_t [m_nb_dcache]; 466 467 m_cpt_icache_access = new uint32_t [m_nb_icache]; 468 m_cpt_dcache_access = new uint32_t [m_nb_dcache]; 469 470 471 m_cpt_fsm_dcache = new uint32_t * [m_nb_dcache]; 472 m_cpt_fsm_icache = new uint32_t * [m_nb_icache]; 473 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 474 m_cpt_fsm_dcache[num_cache] = new uint32_t [soclib::common::size(dcache_fsm_state_str )]; 475 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 476 m_cpt_fsm_icache[num_cache] = new uint32_t [soclib::common::size(icache_fsm_state_str )]; 477 m_cpt_fsm_cmd = new uint32_t [soclib::common::size(cmd_fsm_state_str )]; 478 m_cpt_fsm_rsp = new uint32_t [soclib::common::size(rsp_fsm_state_str )]; 479 m_cpt_fsm_tgt = new uint32_t [soclib::common::size(tgt_fsm_state_str )]; 480 m_cpt_fsm_cleanup = new uint32_t [soclib::common::size(cleanup_fsm_state_str)]; 481 482 m_cpt_frz_cycles = new uint32_t [m_nb_cpu]; 483 // r_icache_fsm("r_icache_fsm"), 484 // r_icache_fsm_save("r_icache_fsm_save"), 485 // r_icache_addr_save("r_icache_addr_save"), 486 // r_icache_miss_req("r_icache_miss_req"), 487 // r_icache_miss_way("r_icache_miss_way"), 488 // r_icache_miss_set("r_icache_miss_set"), 489 // r_icache_unc_req("r_icache_unc_req"), 490 // r_icache_cleanup_req("r_icache_cleanup_req"), 491 // r_icache_cleanup_line("r_icache_cleanup_line"), 492 // r_icache_inval_rsp("r_icache_inval_rsp"), 493 // r_icache_update_addr("r_icache_update_addr"), 494 // r_icache_buf_unc_valid("r_icache_buf_unc_valid"), 495 496 // r_dcache_fsm("r_dcache_fsm"), 497 // r_dcache_fsm_save("r_dcache_fsm_save"), 498 // r_dcache_addr_save("r_dcache_addr_save"), 499 // r_dcache_wdata_save("r_dcache_wdata_save"), 500 // r_dcache_rdata_save("r_dcache_rdata_save"), 501 // r_dcache_type_save("r_dcache_type_save"), 502 // r_dcache_be_save("r_dcache_be_save"), 503 // r_dcache_cached_save("r_dcache_cached_save"), 504 // r_dcache_cleanup_req("r_dcache_cleanup_req"), 505 // r_dcache_cleanup_line("r_dcache_cleanup_line"), 506 // r_dcache_miss_req("r_dcache_miss_req"), 507 // r_dcache_miss_way("r_dcache_miss_way"), 508 // r_dcache_miss_set("r_dcache_miss_set"), 509 // r_dcache_unc_req("r_dcache_unc_req"), 510 // r_dcache_sc_req("r_dcache_sc_req"), 511 // r_dcache_inval_rsp("r_dcache_inval_rsp"), 512 // r_dcache_update_addr("r_dcache_update_addr"), 513 // r_dcache_ll_data("r_dcache_ll_data"), 514 // r_dcache_ll_addr("r_dcache_ll_addr"), 515 // r_dcache_ll_valid("r_dcache_ll_valid"), 516 // r_dcache_previous_unc("r_dcache_previous_unc"), 517 518 // r_tgt_icache_req("r_tgt_icache_req"), 519 // r_tgt_icache_rsp("r_tgt_icache_rsp"), 520 521 // r_tgt_dcache_req("r_tgt_dcache_req"), 522 // r_tgt_dcache_rsp("r_tgt_dcache_rsp"), 523 524 // r_vci_rsp_ins_error("r_vci_rsp_ins_error"), 525 // r_vci_rsp_data_error("r_vci_rsp_data_error"), 526 527 size_t _icache_ways = icache_ways /m_nb_icache; 528 size_t _icache_sets = icache_sets ; 529 size_t _dcache_ways = dcache_ways /m_nb_dcache; 530 size_t _dcache_sets = dcache_sets ; 531 size_t _icache_words = icache_words; 532 size_t _dcache_words = dcache_words; 533 534 size_t _wbuf_nwords = wbuf_nwords ; 535 size_t _wbuf_nlines = wbuf_nlines /m_nb_dcache; 536 size_t _wbuf_timeout = wbuf_timeout; 537 538 539 std::cout << "<VciCcXCacheWrapperV4> Parameters :" << std::endl; 540 std::cout << " * nb_cpu : " << nb_cpu << std::endl; 541 std::cout << " * nb_cache : " << m_nb_icache << " icache(s), " << m_nb_dcache << " dcache(s)" << std::endl; 542 std::cout << " * icache (total) : " << icache_ways << " way(s), " << icache_sets << " set(s), " << icache_words << " word(s)" << std::endl; 543 std::cout << " * icache (per cache) : " << _icache_ways << " way(s), " << _icache_sets << " set(s), " << _icache_words << " word(s)" << std::endl; 544 std::cout << " * dcache (total) : " << dcache_ways << " way(s), " << dcache_sets << " set(s), " << dcache_words << " word(s)" << std::endl; 545 std::cout << " * dcache (per cache) : " << _dcache_ways << " way(s), " << _dcache_sets << " set(s), " << _dcache_words << " word(s)" << std::endl; 546 std::cout << " * wbuf (total) : " << wbuf_nlines << " line(s), " << wbuf_nwords << " word(s), timeout : " << wbuf_timeout << std::endl; 547 std::cout << " * wbuf (per cache) : " << _wbuf_nlines << " line(s), " << _wbuf_nwords << " word(s), timeout : " << _wbuf_timeout << std::endl; 548 549 r_icache = new GenericCache<vci_addr_t> * [m_nb_icache]; 550 r_dcache = new GenericCache<vci_addr_t> * [m_nb_dcache]; 551 r_wbuf = new MultiWriteBuffer<addr_40> * [m_nb_dcache]; 552 553 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 554 { 555 r_icache [num_cache] = new GenericCache<vci_addr_t> ("icache", _icache_ways, _icache_sets, _icache_words); 556 } 557 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 558 { 559 r_dcache [num_cache] = new GenericCache<vci_addr_t> ("dcache", _dcache_ways, _dcache_sets, _dcache_words); 560 r_wbuf [num_cache] = new MultiWriteBuffer<addr_40> ("r_wbuf", _wbuf_nwords, _wbuf_nlines, _wbuf_timeout, _dcache_words); 561 } 562 563 m_num_cache_LSB_mask = 0; 564 for (uint32_t i=0; i<m_num_cache_LSB; ++i) 565 { 566 m_num_cache_LSB_mask <<= 1; 567 m_num_cache_LSB_mask |= 1; 568 } 569 m_num_cache_mask = 0; 570 for (uint32_t i=0; i<(m_num_cache_MSB-m_num_cache_LSB); ++i) 571 { 572 m_num_cache_mask <<= 1; 573 m_num_cache_mask |= 1; 574 } 310 575 311 576 SC_METHOD(transition); … … 316 581 dont_initialize(); 317 582 sensitive << p_clk.neg(); 318 319 583 320 584 typename iss_t::CacheInfo cache_info; … … 326 590 cache_info.dcache_assoc = dcache_ways; 327 591 cache_info.dcache_n_lines = dcache_sets; 328 m_iss.setCacheInfo(cache_info); 329 592 593 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 594 m_iss[num_cpu]->setCacheInfo(cache_info); 595 330 596 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 331 597 m_stop_simulation = false; 332 m_stop_simulation_nb_frz_cycles = 0; 598 m_stop_simulation_nb_frz_cycles = new uint32_t [m_nb_cpu]; 599 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 600 m_stop_simulation_nb_frz_cycles [num_cpu] = 0; 333 601 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 334 602 335 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 336 std::ostringstream filename(""); 337 filename << "Instruction_flow_" << proc_id << ".log"; 338 339 log_dcache_transaction_file.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 603 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 604 log_transaction_file_icache = new std::ofstream [m_nb_cpu]; 605 log_transaction_file_dcache = new std::ofstream [m_nb_cpu]; 606 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 607 { 608 { 609 std::ostringstream filename(""); 610 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_icache-" << proc_id << "_" << num_cpu << ".log"; 611 log_transaction_file_icache[num_cpu].open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 612 } 613 { 614 std::ostringstream filename(""); 615 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_dcache-" << proc_id << "_" << num_cpu << ".log"; 616 log_transaction_file_dcache[num_cpu].open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 617 } 618 } 619 620 { 621 std::ostringstream filename(""); 622 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_cmd-" << proc_id << ".log"; 623 log_transaction_file_cmd.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 624 } 625 { 626 std::ostringstream filename(""); 627 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_tgt-" << proc_id << ".log"; 628 log_transaction_file_tgt.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 629 } 630 { 631 std::ostringstream filename(""); 632 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_cleanup-" << proc_id << ".log"; 633 log_transaction_file_cleanup.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 634 } 340 635 #endif 341 636 } // end constructor … … 345 640 /////////////////////////////////// 346 641 { 347 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 348 log_dcache_transaction_file.close(); 349 #endif 350 642 delete [] m_stop_simulation_nb_frz_cycles; 643 644 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 645 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 646 { 647 log_transaction_file_dcache[num_cpu].close(); 648 log_transaction_file_icache[num_cpu].close(); 649 } 650 delete [] log_transaction_file_dcache; 651 delete [] log_transaction_file_icache; 652 653 log_transaction_file_cmd .close(); 654 log_transaction_file_tgt .close(); 655 log_transaction_file_cleanup.close(); 656 #endif 657 658 delete [] r_icache_lock ; 659 delete [] r_dcache_lock ; 660 delete [] r_dcache_sync ; 661 662 delete [] r_icache_fsm ; 663 delete [] r_icache_fsm_save ; 664 delete [] r_icache_addr_save ; 665 delete [] r_icache_miss_req ; 666 delete [] r_icache_miss_way ; 667 delete [] r_icache_miss_set ; 668 delete [] r_icache_unc_req ; 669 delete [] r_icache_cleanup_req ; 670 delete [] r_icache_cleanup_line ; 671 delete [] r_icache_inval_rsp ; 672 delete [] r_icache_update_addr ; 673 delete [] r_icache_buf_unc_valid; 674 675 delete [] r_dcache_fsm ; 676 delete [] r_dcache_fsm_save ; 677 delete [] r_dcache_addr_save ; 678 delete [] r_dcache_wdata_save ; 679 delete [] r_dcache_rdata_save ; 680 delete [] r_dcache_type_save ; 681 delete [] r_dcache_be_save ; 682 delete [] r_dcache_cached_save ; 683 delete [] r_dcache_cleanup_req ; 684 delete [] r_dcache_cleanup_line ; 685 delete [] r_dcache_miss_req ; 686 delete [] r_dcache_miss_way ; 687 delete [] r_dcache_miss_set ; 688 delete [] r_dcache_unc_req ; 689 delete [] r_dcache_sc_req ; 690 delete [] r_dcache_inval_rsp ; 691 delete [] r_dcache_update_addr ; 692 delete [] r_dcache_previous_unc ; 693 694 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 695 { 696 delete [] r_dcache_ll_data [num_cache]; 697 delete [] r_dcache_ll_addr [num_cache]; 698 delete [] r_dcache_ll_valid [num_cache]; 699 } 700 delete [] r_dcache_num_cpu_save ; 701 delete [] r_dcache_ll_data ; 702 delete [] r_dcache_ll_addr ; 703 delete [] r_dcache_ll_valid ; 704 705 delete [] r_tgt_icache_req ; 706 delete [] r_tgt_icache_rsp ; 707 delete [] r_tgt_dcache_req ; 708 delete [] r_tgt_dcache_rsp ; 709 710 delete [] r_tgt_be ; 351 711 delete [] r_tgt_buf; 352 delete [] r_tgt_be ; 712 713 delete [] r_vci_rsp_ins_error ; 714 delete [] r_vci_rsp_data_error ; 715 716 delete [] ireq ; 717 delete [] irsp ; 718 delete [] ireq_cached ; 719 delete [] ireq_num_cpu ; 720 delete [] dreq ; 721 delete [] drsp ; 722 delete [] dreq_cached ; 723 delete [] dreq_num_cpu ; 724 725 delete [] m_cpt_frz_cycles; 726 727 delete [] m_cpt_icache_access ; 728 delete [] m_cpt_dcache_access ; 729 730 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 731 delete [] m_cpt_fsm_dcache [num_cache]; 732 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 733 delete [] m_cpt_fsm_icache [num_cache]; 734 735 delete [] m_cpt_fsm_dcache ; 736 delete [] m_cpt_fsm_icache ; 737 delete [] m_cpt_fsm_cmd ; 738 delete [] m_cpt_fsm_rsp ; 739 delete [] m_cpt_fsm_tgt ; 740 delete [] m_cpt_fsm_cleanup; 741 742 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 743 { 744 delete r_icache [num_cache]; 745 } 746 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 747 { 748 delete r_wbuf [num_cache]; 749 delete r_dcache [num_cache]; 750 } 751 delete [] r_wbuf; 752 delete [] r_icache; 753 delete [] r_dcache; 754 353 755 354 756 CACHE_MISS_BUF_DEALLOC; 757 758 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 759 { 760 delete m_iss [num_cpu]; 761 delete [] p_irq [num_cpu]; 762 } 763 delete [] m_iss; 764 delete [] p_irq; 355 765 } 356 766 … … 359 769 //////////////////////// 360 770 { 771 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 361 772 std::cout << "CPU " << m_srcid_rw << " : CPI = " 362 << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;773 << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles[num_cpu]) << std::endl ; 363 774 } 364 775 //////////////////////// … … 366 777 //////////////////////// 367 778 { 368 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);369 370 779 uint32_t m_cpt_data_read_cached = m_cpt_data_read-m_cpt_data_read_uncached; 371 780 uint32_t m_cpt_data_write_cached = m_cpt_data_write-m_cpt_data_write_uncached; 372 781 std::cout << "------------------------------------" << std:: dec << std::endl; 373 782 std::cout << "CPU " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl; 374 std::cout << "- CPI : " << (float)m_cpt_total_cycles/run_cycles << std::endl ; 375 std::cout << "- IPC : " << (float)run_cycles/m_cpt_total_cycles << std::endl ; 783 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 784 { 785 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles[num_cpu]); 786 787 std::cout << "- CPI : [" << num_cpu << "] "<< (float)m_cpt_total_cycles/run_cycles << std::endl ; 788 std::cout << "- IPC : [" << num_cpu << "] "<< (float)run_cycles/m_cpt_total_cycles << std::endl ; 789 } 376 790 std::cout << "- DATA READ * : " << m_cpt_data_read << std::endl ; 377 791 std::cout << " + Uncached : " << m_cpt_data_read_uncached << " (" << (float)m_cpt_data_read_uncached*100.0/(float)m_cpt_data_read << "%)" << std::endl ; … … 404 818 std::cout << " + DCACHE Only : " << (float)m_cpt_cc_inval_dcache *100.0/(float)m_cpt_cc_inval << "%" << std::endl; 405 819 std::cout << " + BROADCAST : " << (float)m_cpt_cc_inval_broadcast*100.0/(float)m_cpt_cc_inval << "%" << std::endl; 820 821 uint32_t m_cpt_icache_access_all = 0; 822 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 823 m_cpt_icache_access_all += m_cpt_icache_access [num_cache]; 824 825 std::cout << "- ICACHE ACCESS : " << m_cpt_icache_access_all << std::endl; 826 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 827 std::cout << " + [" << num_cache << "] : " << m_cpt_icache_access [num_cache] << " (" << (float)m_cpt_icache_access [num_cache]*100.0/(float)m_cpt_icache_access_all << "%)" << std::endl; 828 829 uint32_t m_cpt_dcache_access_all = 0; 830 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 831 m_cpt_dcache_access_all += m_cpt_dcache_access [num_cache]; 832 833 std::cout << "- DCACHE ACCESS : " << m_cpt_dcache_access_all << std::endl; 834 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 835 std::cout << " + [" << num_cache << "] : " << m_cpt_dcache_access [num_cache] << " (" << (float)m_cpt_dcache_access [num_cache]*100.0/(float)m_cpt_dcache_access_all << "%)" << std::endl; 836 837 std::cout << "- DCACHE FSM" << std::endl; 838 for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i) 839 { 840 std::cout << " + " << dcache_fsm_state_str[i] << " :\t "; 841 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 842 std::cout << m_cpt_fsm_dcache [num_cache][i] << ", "; 843 std::cout << std::endl; 844 } 845 std::cout << "- ICACHE FSM" << std::endl; 846 for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i) 847 { 848 std::cout << " + " << icache_fsm_state_str[i] << " :\t "; 849 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 850 std::cout << m_cpt_fsm_icache [num_cache][i] << ", "; 851 std::cout << std::endl; 852 } 853 std::cout << "- CMD FSM" << std::endl; 854 for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str ); ++i) 855 std::cout << " + " << cmd_fsm_state_str[i] << " :\t " << m_cpt_fsm_cmd [i] << std::endl; 856 std::cout << "- RSP FSM" << std::endl; 857 for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str ); ++i) 858 std::cout << " + " << rsp_fsm_state_str[i] << " :\t " << m_cpt_fsm_rsp [i] << std::endl; 859 std::cout << "- TGT FSM" << std::endl; 860 for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str ); ++i) 861 std::cout << " + " << tgt_fsm_state_str[i] << " :\t " << m_cpt_fsm_tgt [i] << std::endl; 862 std::cout << "- CLEANUP FSM" << std::endl; 863 for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str ); ++i) 864 std::cout << " + " << cleanup_fsm_state_str[i] << " :\t " << m_cpt_fsm_cleanup [i] << std::endl; 865 406 866 std::cout << "* : accepted or not by the cache" << std::endl ; 407 867 408 r_wbuf.printStatistics(); 868 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 869 r_wbuf[num_cache]->printStatistics(); 409 870 } 410 871 … … 421 882 typename iss_t::DataRequest dreq; 422 883 423 m_iss.getRequests( ireq, dreq );424 884 std::cout << std::dec << "Proc \"" << name() << "\"" << std::endl; 425 std::cout << ireq << std::endl; 426 std::cout << dreq << std::endl; 427 std::cout << " " << dcache_fsm_state_str[r_dcache_fsm] 428 << " " << icache_fsm_state_str[r_icache_fsm] 429 << " " << cmd_fsm_state_str[r_vci_cmd_fsm] 885 886 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 887 { 888 m_iss[num_cpu]->getRequests( ireq, dreq ); 889 std::cout << ireq << std::endl; 890 std::cout << dreq << std::endl; 891 } 892 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 893 std::cout << " " << icache_fsm_state_str[r_icache_fsm[num_cache]] << std::endl; 894 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 895 std::cout << " " << dcache_fsm_state_str[r_dcache_fsm[num_cache]] << std::endl; 896 897 std::cout << " " << cmd_fsm_state_str[r_vci_cmd_fsm] 430 898 << " " << rsp_fsm_state_str[r_vci_rsp_fsm] 431 899 << " " << tgt_fsm_state_str[r_vci_tgt_fsm] … … 434 902 if(mode & 0x1) 435 903 { 436 r_wbuf.printTrace((mode>>1)&1); 904 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 905 r_wbuf[num_cache]->printTrace((mode>>1)&1); 437 906 } 438 907 if(mode & 0x4) 439 908 { 440 909 std::cout << " Data cache" << std::endl; 441 r_dcache.printTrace(); 910 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 911 r_dcache[num_cache]->printTrace(); 442 912 } 443 913 if(mode & 0x8) 444 914 { 445 915 std::cout << " Instruction cache" << std::endl; 446 r_icache.printTrace(); 916 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 917 r_icache[num_cache]->printTrace(); 447 918 } 448 449 // if(mode & 0x10)450 // {451 // std::cout << " Icache miss buffer : ";452 // CACHE_MISS_BUF_RSP_PRINT(i);453 // std::cout << std::endl;454 455 // std::cout << " Dcache miss buffer : ";456 // CACHE_MISS_BUF_RSP_PRINT(d);457 // std::cout << std::endl;458 // }459 919 } 460 920 … … 465 925 if ( not p_resetn.read() ) { 466 926 467 m_iss.reset(); 927 r_cpu_prior = 0; 928 929 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 930 m_iss[num_cpu]->reset(); 468 931 469 932 // FSM states 470 r_dcache_fsm = DCACHE_IDLE; 471 r_icache_fsm = ICACHE_IDLE; 933 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 934 { 935 r_icache_fsm [num_cache] = ICACHE_IDLE; 936 937 r_icache_lock[num_cache] = m_nb_cpu; 938 } 939 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 940 { 941 r_dcache_fsm [num_cache] = DCACHE_IDLE; 942 943 r_dcache_lock[num_cache] = m_nb_cpu; 944 r_dcache_sync[num_cache] = false; 945 } 946 472 947 r_vci_cmd_fsm = CMD_IDLE; 473 948 r_vci_rsp_fsm = RSP_IDLE; … … 475 950 r_cleanup_fsm = CLEANUP_IDLE; 476 951 952 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 953 { 477 954 // write buffer & caches 478 r_wbuf.reset(); 479 r_icache.reset(); 480 r_dcache.reset(); 955 r_icache[num_cache]->reset(); 481 956 482 957 // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs 483 r_icache_miss_req = false; 484 r_icache_unc_req = false; 485 r_icache_cleanup_req = false; 486 r_dcache_miss_req = false; 487 r_dcache_unc_req = false; 488 r_dcache_sc_req = false; 489 r_dcache_cleanup_req = false; 490 r_dcache_previous_unc= false; 958 r_icache_miss_req [num_cache] = false; 959 r_icache_unc_req [num_cache] = false; 960 r_icache_cleanup_req [num_cache] = false; 961 962 // internal messages in DCACHE et ICACHE FSMs 963 r_icache_inval_rsp [num_cache] = false; 964 965 // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs 966 r_icache_buf_unc_valid [num_cache] = false; 491 967 492 968 // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs 493 r_tgt_icache_req = false; 494 r_tgt_dcache_req = false; 495 r_tgt_icache_rsp = false; 496 r_tgt_dcache_rsp = false; 969 r_tgt_icache_req [num_cache] = false; 970 r_tgt_icache_rsp [num_cache] = false; 971 972 r_vci_rsp_ins_error [num_cache] = false; 973 }// end for num_cache 974 975 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 976 { 977 // write buffer & caches 978 r_wbuf [num_cache]->reset(); 979 r_dcache[num_cache]->reset(); 980 981 // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs 982 r_dcache_miss_req [num_cache] = false; 983 r_dcache_unc_req [num_cache] = false; 984 r_dcache_sc_req [num_cache] = false; 985 r_dcache_cleanup_req [num_cache] = false; 986 r_dcache_previous_unc[num_cache] = false; 987 988 // internal messages in DCACHE et ICACHE FSMs 989 r_dcache_inval_rsp [num_cache] = false; 990 991 // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs 992 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 993 r_dcache_ll_valid [num_cache][num_cpu] = false; 994 995 // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs 996 r_tgt_dcache_req [num_cache] = false; 997 r_tgt_dcache_rsp [num_cache] = false; 998 999 r_vci_rsp_data_error [num_cache] = false; 1000 }// end for num_cache 497 1001 498 1002 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 500 1004 #endif 501 1005 502 503 // internal messages in DCACHE et ICACHE FSMs504 r_icache_inval_rsp = false;505 r_dcache_inval_rsp = false;506 507 // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs508 r_dcache_ll_valid = false;509 r_icache_buf_unc_valid = false;510 511 1006 r_vci_cmd_dcache_prior = false; 512 513 r_vci_rsp_data_error = false;514 r_vci_rsp_ins_error = false;515 1007 516 1008 CACHE_MISS_BUF_RESET(i); … … 535 1027 m_cpt_cc_update_dcache_word_useful = 0; 536 1028 537 m_cpt_frz_cycles = 0; 1029 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 1030 m_cpt_frz_cycles [num_cpu] = 0; 538 1031 m_cpt_total_cycles = 0; 539 1032 … … 563 1056 m_length_write_transaction = 0; 564 1057 1058 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1059 { 1060 m_cpt_icache_access [num_cache] = 0; 1061 1062 for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i) 1063 m_cpt_fsm_icache [num_cache][i] = 0; 1064 } 1065 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1066 { 1067 m_cpt_dcache_access [num_cache] = 0; 1068 1069 for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i) 1070 m_cpt_fsm_dcache [num_cache][i] = 0; 1071 } 1072 1073 for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str ); ++i) 1074 m_cpt_fsm_cmd [i] = 0; 1075 for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str ); ++i) 1076 m_cpt_fsm_rsp [i] = 0; 1077 for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str ); ++i) 1078 m_cpt_fsm_tgt [i] = 0; 1079 for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str); ++i) 1080 m_cpt_fsm_cleanup [i] = 0; 1081 565 1082 return; 566 1083 } … … 569 1086 570 1087 PRINTF("--------------------------------------------\n"); 571 PRINTF(" * CC_XCACHE_WRAPPER \"%s\" - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); 572 PRINTF(" * fsm dcache = %s\n",dcache_fsm_state_str[r_dcache_fsm]); 573 PRINTF(" * fsm icache = %s\n",icache_fsm_state_str[r_icache_fsm]); 574 PRINTF(" * fsm cmd = %s\n",cmd_fsm_state_str[r_vci_cmd_fsm]); 575 PRINTF(" * fsm rsp = %s\n",rsp_fsm_state_str[r_vci_rsp_fsm]); 576 PRINTF(" * fsm tgt = %s\n",tgt_fsm_state_str[r_vci_tgt_fsm]); 577 PRINTF(" * fsm cleanup = %s\n",cleanup_fsm_state_str[r_cleanup_fsm]); 578 PRINTF(" * ll info : %d %llx %llx\n",r_dcache_ll_valid.read(), (uint64_t)r_dcache_ll_addr.read(), (uint64_t)r_dcache_ll_data.read()); 579 PRINTF(" * dcache_previous_unc : %d\n",r_dcache_previous_unc.read()); 1088 PRINTF(" * CC_XCACHE_WRAPPER \"%s\" Transition - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); 1089 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1090 PRINTF(" * fsm dcache = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,dcache_fsm_state_str[r_dcache_fsm[num_cache]],r_dcache_lock[num_cache].read(),(uint64_t)r_dcache_addr_save[num_cache].read(),(uint64_t)set_num_dcache_only(r_dcache_addr_save[num_cache].read(),num_cache)); 1091 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1092 PRINTF(" * fsm icache = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,icache_fsm_state_str[r_icache_fsm[num_cache]],r_icache_lock[num_cache].read(),(uint64_t)r_icache_addr_save[num_cache].read(),(uint64_t)set_num_icache_only(r_icache_addr_save[num_cache].read(),num_cache)); 1093 PRINTF(" * fsm cmd = (%.2d) %s\n",r_vci_cmd_num_cache.read(), cmd_fsm_state_str[r_vci_cmd_fsm]); 1094 PRINTF(" * fsm rsp = (%.2d) %s\n",r_vci_rsp_num_cache.read(), rsp_fsm_state_str[r_vci_rsp_fsm]); 1095 PRINTF(" * fsm tgt = (%.2d) %s - i %llx d %llx\n",r_tgt_num_cache.read(), tgt_fsm_state_str[r_vci_tgt_fsm],(uint64_t)r_tgt_iaddr.read(),(uint64_t)r_tgt_daddr.read()); 1096 //PRINTF(" * fsm tgt = %s - %llx\n",tgt_fsm_state_str[r_vci_tgt_fsm],(uint64_t)r_tgt_addr.read()); 1097 PRINTF(" * fsm cleanup = (%.2d) %s\n",r_cleanup_num_cache.read(), cleanup_fsm_state_str[r_cleanup_fsm]); 1098 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1099 { 1100 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 1101 PRINTF(" * ll info : [%.2d][%.2d] %d %llx (%llx) %llx\n" 1102 ,num_cache 1103 ,num_cpu 1104 , r_dcache_ll_valid [num_cache][num_cpu].read() 1105 ,(uint64_t)r_dcache_ll_addr [num_cache][num_cpu].read() 1106 ,(uint64_t)set_num_dcache_only(r_dcache_ll_addr [num_cache][num_cpu].read(),num_cache) 1107 ,(uint64_t)r_dcache_ll_data [num_cache][num_cpu].read()); 1108 1109 PRINTF(" * dcache_previous_unc : [%.2d] %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); 1110 1111 #if CC_XCACHE_WRAPPER_DEBUG 1112 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1113 r_wbuf[num_cache]->printTrace(1); 1114 #endif 1115 } 580 1116 // CACHE_MISS_BUF_RSP_PRINT(i); 581 1117 // CACHE_MISS_BUF_RSP_PRINT(d); 582 1118 583 #if CC_XCACHE_WRAPPER_DEBUG 584 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 585 { 586 r_wbuf.printTrace(1); 587 } 588 #endif 1119 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1120 m_cpt_fsm_dcache [num_cache][r_dcache_fsm[num_cache]] ++; 1121 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1122 m_cpt_fsm_icache [num_cache][r_icache_fsm[num_cache]] ++; 1123 m_cpt_fsm_cmd [r_vci_cmd_fsm] ++; 1124 m_cpt_fsm_rsp [r_vci_rsp_fsm] ++; 1125 m_cpt_fsm_tgt [r_vci_tgt_fsm] ++; 1126 m_cpt_fsm_cleanup [r_cleanup_fsm] ++; 589 1127 590 1128 m_cpt_total_cycles++; … … 626 1164 if ( p_vci_tgt.cmdval.read() ) 627 1165 { 628 PRINTF(" * <TGT> request\n");1166 PRINTF(" * <TGT> Request\n"); 629 1167 630 1168 addr_40 address = p_vci_tgt.address.read(); … … 634 1172 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 635 1173 std::cout << "coherence request is not a write" << std::endl; 636 std::cout << " oddress = " << std::hex << address << std::dec << std::endl;1174 std::cout << "address = " << std::hex << address << std::dec << std::endl; 637 1175 std::cout << "srcid = " << p_vci_tgt.srcid.read() << std::endl; 638 1176 exit(0); … … 644 1182 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 645 1183 std::cout << "out of segment coherence request" << std::endl; 646 std::cout << " oddress = " << std::hex << address << std::dec << std::endl;1184 std::cout << "address = " << std::hex << address << std::dec << std::endl; 647 1185 std::cout << "srcid = " << p_vci_tgt.srcid.read() << std::endl; 648 1186 exit(0); 649 1187 } 650 1188 651 r_tgt_addr = (((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | 652 ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4; 653 r_tgt_srcid = p_vci_tgt.srcid.read(); 654 r_tgt_trdid = p_vci_tgt.trdid.read(); 655 r_tgt_pktid = p_vci_tgt.pktid.read(); 656 // r_tgt_plen = p_vci_tgt.plen.read(); 1189 addr_40 tgt_addr = ((((addr_40)p_vci_tgt.be.read() & 0x3) << 32) | ((addr_40) p_vci_tgt.wdata.read())) << (addr_40)m_dcache_words_shift; 1190 // * m_dcache_words * 4; 1191 1192 addr_40 tgt_iaddr = tgt_addr; 1193 addr_40 tgt_daddr = tgt_addr; 1194 1195 PRINTF(" * <TGT> srcid : %d\n",(uint32_t)p_vci_tgt.srcid.read()); 1196 PRINTF(" * <TGT> trdid : %d\n",(uint32_t)p_vci_tgt.trdid.read()); 1197 PRINTF(" * <TGT> pktid : %d\n",(uint32_t)p_vci_tgt.pktid.read()); 1198 PRINTF(" * <TGT> address (before) : %llx\n",(uint64_t)tgt_iaddr); 1199 1200 r_tgt_srcid = p_vci_tgt.srcid.read(); 1201 r_tgt_trdid = p_vci_tgt.trdid.read(); 1202 r_tgt_pktid = p_vci_tgt.pktid.read(); 1203 // r_tgt_plen = p_vci_tgt.plen.read(); 657 1204 658 PRINTF(" * <TGT> address : %llx\n",(uint64_t)address); 659 PRINTF(" * <TGT> address : %llx\n",(uint64_t)((((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | 660 ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4)); 661 1205 // BROADCAST 662 1206 if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type 663 1207 { … … 671 1215 // r_tgt_brdcast= true; 672 1216 r_vci_tgt_fsm = TGT_REQ_BROADCAST; 1217 uint32_t tgt_num_cache; 1218 tgt_num_cache = get_num_icache(tgt_iaddr,0); // none effect (else CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1219 tgt_num_cache = get_num_dcache(tgt_daddr); 1220 r_tgt_num_cache = tgt_num_cache; 1221 1222 PRINTF(" * <TGT> REQ_BROADCAST\n"); 1223 PRINTF(" * <TGT> num_cache (data) : %d\n",tgt_num_cache); 1224 673 1225 m_cpt_cc_inval_broadcast++ ; 1226 1227 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 1228 { 1229 log_transaction_file_tgt 1230 << "[" << m_cpt_total_cycles << "] " 1231 << "BROADCAST " 1232 << std::hex 1233 << " L " << std::setw(10) << (uint64_t)tgt_addr 1234 << std::dec 1235 << " - " << tgt_num_cache 1236 << std::endl; 1237 } 1238 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 1239 674 1240 } 675 1241 else // multi-update or multi-invalidate for data type … … 677 1243 uint32_t cell = address - m_segment.baseAddress(); // addr_40 678 1244 // r_tgt_brdcast = false; 1245 679 1246 if (cell == 0) 680 1247 { // invalidate data … … 687 1254 r_tgt_update = false; 688 1255 r_vci_tgt_fsm = TGT_REQ_DCACHE; 1256 uint32_t tgt_num_cache = get_num_dcache(tgt_daddr); // static partionnement 1257 r_tgt_num_cache = tgt_num_cache; 1258 1259 PRINTF(" * <TGT> REQ_DCACHE\n"); 1260 PRINTF(" * <TGT> num_cache : %d\n",tgt_num_cache); 1261 689 1262 m_cpt_cc_inval_dcache++ ; 1263 1264 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 1265 { 1266 log_transaction_file_tgt 1267 << "[" << m_cpt_total_cycles << "] " 1268 << "INVAL DATA " 1269 << std::hex 1270 << " L " << std::setw(10) << (uint64_t)tgt_addr 1271 << std::dec 1272 << " - " << tgt_num_cache 1273 << std::endl; 1274 } 1275 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 1276 690 1277 } 691 1278 else if (cell == 4) // invalidate instruction … … 699 1286 r_tgt_update = false; 700 1287 r_vci_tgt_fsm = TGT_REQ_ICACHE; 1288 uint32_t tgt_num_cpu = p_vci_tgt.pktid.read(); 1289 uint32_t tgt_num_cache = get_num_icache(tgt_iaddr,tgt_num_cpu); 1290 r_tgt_num_cache = tgt_num_cache; 1291 1292 PRINTF(" * <TGT> REQ_ICACHE\n"); 1293 PRINTF(" * <TGT> num_cache : %d\n",tgt_num_cache); 1294 701 1295 m_cpt_cc_inval_icache++ ; 1296 1297 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 1298 { 1299 log_transaction_file_tgt 1300 << "[" << m_cpt_total_cycles << "] " 1301 << "INVAL INS " 1302 << std::hex 1303 << " L " << std::setw(10) << (uint64_t)tgt_addr 1304 << std::dec 1305 << " - " << tgt_num_cache 1306 << std::endl; 1307 } 1308 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 1309 702 1310 } 703 1311 else if ( (cell == 8) or (cell==12) ) // update data or instruction … … 713 1321 m_cpt_cc_update_dcache++; 714 1322 r_tgt_update_data = true; 1323 1324 uint32_t tgt_num_cache = get_num_dcache(tgt_daddr); 1325 r_tgt_num_cache = tgt_num_cache; 1326 1327 PRINTF(" * <TGT> UPDT_WORD DATA\n"); 1328 PRINTF(" * <TGT> num_cache : %d\n",tgt_num_cache); 1329 1330 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 1331 { 1332 log_transaction_file_tgt 1333 << "[" << m_cpt_total_cycles << "] " 1334 << "UPT DATA " 1335 << std::hex 1336 << " L " << std::setw(10) << (uint64_t)tgt_addr 1337 << std::dec 1338 << " - " << tgt_num_cache 1339 << std::endl; 1340 } 1341 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 715 1342 } 716 1343 else … … 718 1345 m_cpt_cc_update_icache++; 719 1346 r_tgt_update_data = false; 1347 1348 uint32_t tgt_num_cpu = p_vci_tgt.pktid.read(); 1349 uint32_t tgt_num_cache = get_num_icache(tgt_iaddr,tgt_num_cpu); 1350 r_tgt_num_cache = tgt_num_cache; 1351 1352 PRINTF(" * <TGT> UPDT_WORD INSTRUCTION\n"); 1353 PRINTF(" * <TGT> num_cache : %d\n",tgt_num_cache); 1354 1355 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 1356 { 1357 log_transaction_file_tgt 1358 << "[" << m_cpt_total_cycles << "] " 1359 << "UPT INS " 1360 << std::hex 1361 << " L " << std::setw(10) << (uint64_t)tgt_addr 1362 << std::dec 1363 << " - " << tgt_num_cache 1364 << std::endl; 1365 } 1366 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 720 1367 } 721 1368 r_tgt_update = true; … … 724 1371 725 1372 } // end if address 1373 1374 r_tgt_iaddr = tgt_iaddr; 1375 r_tgt_daddr = tgt_daddr; 1376 PRINTF(" * <TGT> address (after) : i %llx, d %llx\n",(uint64_t)tgt_iaddr,(uint64_t)tgt_daddr); 1377 726 1378 } // end if cmdval 727 1379 break; … … 739 1391 r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index 740 1392 #ifdef COHERENCE_DEBUG 741 std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_ addr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl;1393 std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_daddr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl; 742 1394 #endif 743 1395 r_vci_tgt_fsm = TGT_UPDT_DATA; … … 789 1441 790 1442 case TGT_REQ_BROADCAST: 791 if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 792 { 793 r_vci_tgt_fsm = TGT_RSP_BROADCAST; 794 r_tgt_icache_req = true; 795 r_tgt_dcache_req = true; 1443 { 1444 bool tgt_icache_req; 1445 1446 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1447 tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read(); 1448 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 1449 tgt_icache_req = false; 1450 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1451 tgt_icache_req |= r_tgt_icache_req[num_cache].read(); 1452 #endif 1453 if (not tgt_icache_req and not r_tgt_dcache_req[r_tgt_num_cache].read()) 1454 { 1455 r_vci_tgt_fsm = TGT_RSP_BROADCAST; 1456 1457 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1458 r_tgt_icache_req[r_tgt_num_cache] = true; 1459 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 1460 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1461 r_tgt_icache_req[ num_cache] = true; 1462 #endif 1463 1464 r_tgt_dcache_req[r_tgt_num_cache] = true; 1465 } 796 1466 } 797 1467 break; … … 799 1469 case TGT_REQ_ICACHE: 800 1470 { 801 if ( not r_tgt_icache_req.read() ) 1471 // Request treated by the icache 1472 if ( not r_tgt_icache_req[r_tgt_num_cache].read() ) 802 1473 { 803 1474 r_vci_tgt_fsm = TGT_RSP_ICACHE; 804 r_tgt_icache_req = true;1475 r_tgt_icache_req[r_tgt_num_cache] = true; 805 1476 } 806 1477 break; … … 808 1479 809 1480 case TGT_REQ_DCACHE: 810 if ( not r_tgt_dcache_req.read() ) 811 { 812 r_vci_tgt_fsm = TGT_RSP_DCACHE; 813 r_tgt_dcache_req = true; 814 } 815 break; 816 1481 { 1482 // Request treated by the dcache 1483 1484 if ( not r_tgt_dcache_req[r_tgt_num_cache].read() ) 1485 { 1486 r_vci_tgt_fsm = TGT_RSP_DCACHE; 1487 r_tgt_dcache_req[r_tgt_num_cache] = true; 1488 } 1489 break; 1490 } 817 1491 case TGT_RSP_BROADCAST: 818 if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 819 { 820 // one response 821 if ( not r_tgt_icache_rsp or not r_tgt_dcache_rsp ) 1492 { 1493 PRINTF(" * <TGT> dcache[%d] : %d - %d\n",(uint32_t)r_tgt_num_cache, (uint32_t)r_tgt_dcache_req[r_tgt_num_cache].read(),(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read()); 1494 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1495 PRINTF(" * <TGT> icache[%d] : %d - %d\n",(uint32_t)num_cache, (uint32_t)r_tgt_icache_req[num_cache].read(),(uint32_t)r_tgt_icache_rsp[num_cache].read()); 1496 1497 bool tgt_icache_req; 1498 1499 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1500 tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read(); 1501 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 1502 tgt_icache_req = false; 1503 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1504 tgt_icache_req |= r_tgt_icache_req[num_cache].read(); 1505 #endif 1506 if (not tgt_icache_req and not r_tgt_dcache_req[r_tgt_num_cache].read()) 822 1507 { 823 if ( p_vci_tgt.rspack.read() ) 1508 bool tgt_icache_rsp; 1509 uint32_t tgt_icache_rsp_num_cache; 1510 1511 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1512 tgt_icache_rsp_num_cache = r_tgt_num_cache; 1513 tgt_icache_rsp = r_tgt_icache_rsp[r_tgt_num_cache].read(); 1514 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 1515 tgt_icache_rsp_num_cache = 0; 1516 for (;tgt_icache_rsp_num_cache<m_nb_icache; ++tgt_icache_rsp_num_cache) 824 1517 { 825 r_vci_tgt_fsm = TGT_IDLE; 826 r_tgt_icache_rsp = false; 827 r_tgt_dcache_rsp = false; 1518 PRINTF(" * <TGT> icache[%d] : %d\n",(uint32_t)tgt_icache_rsp_num_cache, (uint32_t)r_tgt_icache_rsp[tgt_icache_rsp_num_cache].read()); 1519 1520 if (r_tgt_icache_rsp[tgt_icache_rsp_num_cache].read()) 1521 break; 828 1522 } 829 } 830 831 // if data and instruction have the inval line, need two responses 832 if ( r_tgt_icache_rsp and r_tgt_dcache_rsp ) 833 { 834 if ( p_vci_tgt.rspack.read() ) 1523 1524 tgt_icache_rsp = (tgt_icache_rsp_num_cache<m_nb_icache); 1525 #endif 1526 1527 PRINTF(" * <TGT> icache_rsp [%d] : %d\n",tgt_icache_rsp_num_cache,(uint32_t) tgt_icache_rsp); 1528 PRINTF(" * <TGT> dcache_rsp [%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t) r_tgt_dcache_rsp[r_tgt_num_cache]); 1529 1530 if (tgt_icache_rsp or r_tgt_dcache_rsp[r_tgt_num_cache]) 835 1531 { 836 r_tgt_icache_rsp = false; // only reset one for respond the second time 1532 // Have send one response 1533 if ( p_vci_tgt.rspack.read()) 1534 { 1535 // reset dcache if activated 1536 if (r_tgt_dcache_rsp[r_tgt_num_cache]) 1537 r_tgt_dcache_rsp[r_tgt_num_cache] = false; 1538 else 1539 // reset one icache 1540 r_tgt_icache_rsp[tgt_icache_rsp_num_cache] = false; 1541 } 837 1542 } 838 } 839 840 // if there is no need for a response 841 if ( not r_tgt_icache_rsp and not r_tgt_dcache_rsp ) 1543 1544 // // one response 1545 // if ( not r_tgt_icache_rsp[r_tgt_num_cache] or not r_tgt_dcache_rsp[r_tgt_num_cache] ) 1546 // { 1547 // if ( p_vci_tgt.rspack.read() ) 1548 // { 1549 // r_vci_tgt_fsm = TGT_IDLE; 1550 // r_tgt_icache_rsp[r_tgt_num_cache] = false; 1551 // r_tgt_dcache_rsp[r_tgt_num_cache] = false; 1552 // } 1553 // } 1554 1555 // // if data and instruction have the inval line, need two responses 1556 // if ( r_tgt_icache_rsp[r_tgt_num_cache] and r_tgt_dcache_rsp[r_tgt_num_cache] ) 1557 // { 1558 // if ( p_vci_tgt.rspack.read() ) 1559 // { 1560 // r_tgt_icache_rsp[r_tgt_num_cache] = false; // only reset one for respond the second time 1561 // } 1562 // } 1563 1564 PRINTF(" * <TGT> icache_rsp : %d\n",(uint32_t) r_tgt_icache_rsp); 1565 PRINTF(" * <TGT> dcache_rsp[%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read()); 1566 // if there is no need for a response 1567 if (not tgt_icache_rsp and not r_tgt_dcache_rsp[r_tgt_num_cache] ) 1568 { 1569 r_vci_tgt_fsm = TGT_IDLE; 1570 } 1571 1572 } 1573 break; 1574 } 1575 //////////////////// 1576 case TGT_RSP_ICACHE: 1577 { 1578 bool transaction_rsp = (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp[r_tgt_num_cache].read()) and not r_tgt_icache_req[r_tgt_num_cache].read(); 1579 1580 PRINTF(" * <TGT> RSP_ICACHE : transaction : %d ((%d or not %d) and not %d)\n",transaction_rsp 1581 ,(int)p_vci_tgt.rspack.read() 1582 ,(int)r_tgt_icache_rsp[r_tgt_num_cache].read() 1583 ,(int)r_tgt_icache_req[r_tgt_num_cache].read() 1584 ); 1585 1586 if (transaction_rsp) 842 1587 { 843 1588 r_vci_tgt_fsm = TGT_IDLE; 844 } 845 846 } 847 break; 848 //////////////////// 849 case TGT_RSP_ICACHE: 850 { 851 if ( (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp.read()) and not r_tgt_icache_req.read() ) 1589 r_tgt_icache_rsp[r_tgt_num_cache] = false; 1590 } 1591 break; 1592 } 1593 1594 case TGT_RSP_DCACHE: 1595 { 1596 bool transaction_rsp = (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp[r_tgt_num_cache].read()) and not r_tgt_dcache_req[r_tgt_num_cache].read(); 1597 1598 PRINTF(" * <TGT> RSP_DCACHE : transaction : %d\n",transaction_rsp); 1599 1600 if (transaction_rsp) 852 1601 { 853 1602 r_vci_tgt_fsm = TGT_IDLE; 854 r_tgt_ icache_rsp= false;1603 r_tgt_dcache_rsp[r_tgt_num_cache] = false; 855 1604 } 856 1605 break; 857 1606 } 858 859 case TGT_RSP_DCACHE:860 {861 if ( (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp.read()) and not r_tgt_dcache_req.read() )862 {863 r_vci_tgt_fsm = TGT_IDLE;864 r_tgt_dcache_rsp = false;865 }866 break;867 }868 1607 } // end switch TGT_FSM 1608 1609 ///////////////////////////////////////////////////////////////////// 1610 // Interface between CPU and CACHE FSM 1611 /////////////////////////////////////////////////////////////////////// 1612 1613 uint32_t ireq_num_cache [m_nb_cpu]; 1614 uint32_t dreq_num_cache [m_nb_cpu]; 1615 bool have_sync = false; 1616 1617 { 1618 typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER; 1619 typename iss_t::DataRequest _dreq = ISS_DREQ_INITIALIZER; 1620 1621 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1622 { 1623 ireq [num_cache] = _ireq; 1624 //irsp [num_cache] = _irsp; 1625 } 1626 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1627 { 1628 dreq [num_cache] = _dreq; 1629 //drsp [num_cache] = _drsp; 1630 1631 have_sync |= r_dcache_sync [num_cache]; 1632 } 1633 } 1634 1635 for (uint32_t _num_cpu=0; _num_cpu<m_nb_cpu; ++_num_cpu) 1636 { 1637 // round robin priority 1638 uint32_t num_cpu = (r_cpu_prior+_num_cpu)%m_nb_cpu; 1639 1640 typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER; 1641 typename iss_t::DataRequest _dreq = ISS_DREQ_INITIALIZER; 1642 1643 m_iss[num_cpu]->getRequests(_ireq, _dreq); 1644 1645 addr_40 addr; 1646 uint32_t num_cache; 1647 1648 addr = (addr_40)_ireq.addr; 1649 num_cache = get_num_icache(addr,num_cpu); 1650 1651 // test if already used 1652 if (not ireq[num_cache].valid and 1653 (r_icache_lock [num_cache] == m_nb_cpu) or 1654 (r_icache_lock [num_cache] == num_cpu)) 1655 { 1656 bool valid = _ireq.valid; 1657 1658 if (valid) 1659 { 1660 PRINTF(" * <CPU2CACHE> ICACHE : Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache); 1661 ireq_num_cache [num_cpu ] = num_cache; 1662 r_icache_lock [num_cache] = num_cpu; 1663 } 1664 else 1665 { 1666 PRINTF(" * <CPU2CACHE> ICACHE : No Transaction between cpu %d and cache %d : invalid\n",num_cpu,num_cache); 1667 ireq_num_cache [num_cpu] = m_nb_icache; 1668 } 1669 1670 ireq_cached [num_cache] = m_cacheability_table[(vci_addr_t)_ireq.addr]; 1671 ireq_num_cpu [num_cache] = num_cpu; 1672 ireq [num_cache] = _ireq; 1673 ireq [num_cache].addr = addr; 1674 } 1675 else 1676 { 1677 PRINTF(" * <CPU2CACHE> ICACHE : No transaction (cpu %d)\n",num_cpu); 1678 1679 ireq_num_cache [num_cpu] = m_nb_icache; 1680 } 1681 1682 addr = (addr_40)_dreq.addr; 1683 num_cache = get_num_dcache(addr); 1684 1685 // test if already used 1686 if (not dreq[num_cache].valid and 1687 not have_sync and 1688 (r_dcache_lock [num_cache] == m_nb_cpu) or 1689 (r_dcache_lock [num_cache] == num_cpu)) 1690 { 1691 bool valid = _dreq.valid; 1692 1693 if (valid) 1694 { 1695 PRINTF(" * <CPU2CACHE> DCACHE : Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache); 1696 dreq_num_cache [num_cpu ] = num_cache; 1697 r_dcache_lock [num_cache] = num_cpu; 1698 } 1699 else 1700 { 1701 PRINTF(" * <CPU2CACHE> DCACHE : No Transaction between cpu %d and cache %d : invalid\n",num_cpu,num_cache); 1702 dreq_num_cache [num_cpu] = m_nb_dcache; 1703 } 1704 1705 dreq_cached [num_cache] = m_cacheability_table[(vci_addr_t)_dreq.addr]; 1706 dreq_num_cpu [num_cache] = num_cpu; 1707 dreq [num_cache] = _dreq; 1708 dreq [num_cache].addr = addr; 1709 } 1710 else 1711 { 1712 PRINTF(" * <CPU2CACHE> DCACHE : No transaction (cpu %d)\n",num_cpu); 1713 1714 dreq_num_cache [num_cpu] = m_nb_dcache; 1715 } 1716 1717 1718 #if CC_XCACHE_WRAPPER_DEBUG 1719 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1720 { 1721 std::cout << " * <CPU2CACHE> Instruction Request : " << ireq_num_cache[num_cpu] << " - " << _ireq << std::endl 1722 << " * <CPU2CACHE> Data Request : " << dreq_num_cache[num_cpu] << " - " << _dreq << std::endl; 1723 } 1724 #endif 1725 } 1726 1727 // round robin priority 1728 r_cpu_prior = (r_cpu_prior+1)%m_nb_cpu; 869 1729 870 1730 ///////////////////////////////////////////////////////////////////// … … 899 1759 // flip-flop. It is reset by the ICACHE FSM. 900 1760 /////////////////////////////////////////////////////////////////////// 901 902 typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER; 903 typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER; 904 905 typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER; 906 typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER; 907 908 m_iss.getRequests( ireq, dreq ); 909 910 #if CC_XCACHE_WRAPPER_DEBUG 911 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 912 std::cout << " * Instruction Request : " << ireq << std::endl; 913 #endif 914 915 switch(r_icache_fsm) { 1761 1762 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1763 { 1764 typename iss_t::InstructionRequest _ireq = ireq [num_cache]; 1765 typename iss_t::InstructionResponse _irsp = ISS_IRSP_INITIALIZER; 1766 1767 switch(r_icache_fsm[num_cache]) { 916 1768 ///////////////// 917 1769 case ICACHE_IDLE: 918 1770 { 919 if ( r_tgt_icache_req ) { // external request920 if (ireq.valid ) m_cost_ins_miss_frz++;921 r_icache_fsm = ICACHE_CC_CHECK;922 r_icache_fsm_save = r_icache_fsm.read();1771 if ( r_tgt_icache_req[num_cache] ) { // external request 1772 // if ( _ireq.valid ) m_cost_ins_miss_frz++; 1773 r_icache_fsm [num_cache] = ICACHE_CC_CHECK; 1774 r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache]; 923 1775 break; 924 1776 } 925 if ( ireq.valid ) { 926 data_t icache_ins = 0; 927 bool icache_hit = false; 928 bool icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr]; 929 bool icache_cleanup_hit = r_icache_cleanup_req and (((addr_40)ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line.read()); 1777 if ( _ireq.valid ) { 1778 data_t icache_ins = 0; 1779 bool icache_hit = false; 1780 bool icache_cached = ireq_cached [num_cache]; 1781 // uint32_t icache_num_cpu = ireq_num_cpu [num_cache]; 1782 bool icache_cleanup_hit = r_icache_cleanup_req[num_cache] and (((addr_40)_ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line[num_cache].read()); 930 1783 931 1784 // icache_hit & icache_ins evaluation 932 1785 if ( icache_cached ) { 933 icache_hit = r_icache .read((vci_addr_t)ireq.addr, &icache_ins);1786 icache_hit = r_icache[num_cache]->read((vci_addr_t) _ireq.addr, &icache_ins); 934 1787 } else { 935 1788 // if uncache, again in the icache_miss_buf 936 icache_hit = ( r_icache_buf_unc_valid and ((addr_40) ireq.addr == (addr_40)r_icache_addr_save)); 937 icache_ins = CACHE_MISS_BUF_RSP_DATA(i,0); 938 CACHE_MISS_BUF_RSP_POP(i); 1789 icache_hit = (r_icache_buf_unc_valid[num_cache] and ((addr_40) _ireq.addr == (addr_40)r_icache_addr_save[num_cache])); 1790 icache_ins = CACHE_MISS_BUF_RSP_DATA(i,num_cache,0); 1791 1792 if (icache_hit) 1793 CACHE_MISS_BUF_RSP_POP(i,num_cache); 939 1794 } 940 1795 941 PRINTF(" * <ICACHE> hit %d - cached %d - cleanup_hit %d\n",icache_hit, icache_cached, icache_cleanup_hit); 942 943 ASSERT( not (icache_hit and icache_cleanup_hit), 944 "Icache hit and icache_cleanup_hit"); 945 946 if ( not icache_hit and not icache_cleanup_hit) { 947 m_cpt_ins_miss++; 948 m_cost_ins_miss_frz++; 949 r_icache_addr_save = (addr_40) ireq.addr; 950 951 CACHE_MISS_BUF_REQ_INIT(i); 952 953 if ( icache_cached ) { 1796 PRINTF(" * <ICACHE [%d]> hit %d - cached %d - cleanup_hit %d\n",num_cache, icache_hit, icache_cached, icache_cleanup_hit); 1797 1798 // ASSERT( not (icache_hit and icache_cleanup_hit), 1799 // "Icache hit and icache_cleanup_hit"); 1800 1801 if (icache_hit and icache_cleanup_hit) 1802 { 1803 PRINTF(" * <ICACHE [%d]> Warning : icache hit and icache_cleanup_hit\n",num_cache); 1804 icache_hit = false; 1805 } 1806 else 1807 { 1808 if ( not icache_hit and not icache_cleanup_hit) 1809 { 1810 m_cpt_ins_miss++; 1811 m_cost_ins_miss_frz++; 1812 r_icache_addr_save[num_cache] = (addr_40) _ireq.addr; 1813 1814 CACHE_MISS_BUF_REQ_INIT(i,num_cache); 1815 1816 if ( icache_cached ) 1817 { 954 1818 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 955 r_icache_fsm= ICACHE_MISS_VICTIM;1819 r_icache_fsm [num_cache] = ICACHE_MISS_VICTIM; 956 1820 #else 957 r_icache_fsm = ICACHE_MISS_WAIT; 958 #endif 959 r_icache_miss_req = true; 960 961 } else { 962 r_icache_fsm = ICACHE_UNC_WAIT; 963 r_icache_unc_req = true; 1821 r_icache_fsm [num_cache] = ICACHE_MISS_WAIT; 1822 #endif 1823 r_icache_miss_req[num_cache] = true; 1824 1825 } 1826 else 1827 { 1828 r_icache_fsm [num_cache] = ICACHE_UNC_WAIT; 1829 r_icache_unc_req[num_cache] = true; 1830 } 964 1831 } 965 } else { 966 r_icache_buf_unc_valid = false; 1832 else 1833 { 1834 r_icache_buf_unc_valid[num_cache] = false; 1835 } 1836 m_cpt_icache_dir_read += m_icache_ways; 1837 m_cpt_icache_data_read += m_icache_ways; 967 1838 } 968 m_cpt_icache_dir_read += m_icache_ways; 969 m_cpt_icache_data_read += m_icache_ways; 970 irsp.valid = icache_hit; 971 irsp.instruction = icache_ins; 1839 1840 _irsp.valid = icache_hit; 1841 _irsp.instruction = icache_ins; 972 1842 } 973 1843 break; … … 977 1847 case ICACHE_MISS_VICTIM: 978 1848 { 979 if (not r_icache_cleanup_req )1849 if (not r_icache_cleanup_req[num_cache]) 980 1850 { 981 1851 size_t way; 982 1852 size_t set; 983 vci_addr_t addr = (vci_addr_t) r_icache_addr_save .read();1853 vci_addr_t addr = (vci_addr_t) r_icache_addr_save[num_cache].read(); 984 1854 vci_addr_t victim; 985 1855 986 r_icache_cleanup_req = r_icache.victim_select(addr, &victim, &way, &set );987 r_icache_cleanup_line = (addr_40) victim;988 r_icache_miss_way = way;989 r_icache_miss_set = set;1856 r_icache_cleanup_req [num_cache] = r_icache[num_cache]->victim_select(addr, &victim, &way, &set ); 1857 r_icache_cleanup_line[num_cache] = (addr_40) victim; 1858 r_icache_miss_way [num_cache] = way; 1859 r_icache_miss_set [num_cache] = set; 990 1860 991 r_icache_fsm = ICACHE_MISS_WAIT;1861 r_icache_fsm [num_cache] = ICACHE_MISS_WAIT; 992 1862 } 993 1863 break; … … 998 1868 { 999 1869 m_cost_ins_miss_frz++; 1000 if ( r_tgt_icache_req ) { // external request1001 r_icache_fsm = ICACHE_CC_CHECK;1002 r_icache_fsm_save = r_icache_fsm.read();1870 if ( r_tgt_icache_req[num_cache] ) { // external request 1871 r_icache_fsm [num_cache] = ICACHE_CC_CHECK; 1872 r_icache_fsm_save [num_cache] = r_icache_fsm[num_cache].read(); 1003 1873 break; 1004 1874 } 1005 1875 1006 bool val = CACHE_MISS_BUF_RSP_VAL(i, 0);1007 1008 PRINTF(" * <ICACHE > val : %d\n",val);1876 bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,0); 1877 1878 PRINTF(" * <ICACHE [%d]> val : %d\n",num_cache,val); 1009 1879 1010 1880 if (val) 1011 1881 { 1012 PRINTF(" * <ICACHE> r_icache_inval_rsp : %d\n",(int) r_icache_inval_rsp ); 1013 PRINTF(" * <ICACHE> r_vci_rsp_ins_error : %d\n",(int) r_vci_rsp_ins_error ); 1014 PRINTF(" * <ICACHE> r_icache_cleanup_req : %d\n",(int) r_icache_cleanup_req); 1015 1016 // if (not r_icache_inval_rsp ) 1017 // { 1018 // Miss read response and no invalidation 1019 if ( r_vci_rsp_ins_error ) { 1020 r_icache_fsm = ICACHE_ERROR; 1021 } else { 1882 PRINTF(" * <ICACHE [%d]> r_icache_inval_rsp : %d\n",num_cache,(int) r_icache_inval_rsp [num_cache]); 1883 PRINTF(" * <ICACHE [%d]> r_vci_rsp_ins_error : %d\n",num_cache,(int) r_vci_rsp_ins_error [num_cache]); 1884 PRINTF(" * <ICACHE [%d]> r_icache_cleanup_req : %d\n",num_cache,(int) r_icache_cleanup_req[num_cache]); 1885 1886 // Miss read response and no invalidation 1887 if ( r_vci_rsp_ins_error [num_cache]) { 1888 r_icache_fsm[num_cache] = ICACHE_ERROR; 1889 } else { 1022 1890 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM 1023 if (not r_icache_cleanup_req.read()) 1024 #endif 1025 { 1026 r_icache_update_addr = 0; 1027 r_icache_fsm = ICACHE_MISS_UPDT; 1028 } 1891 if (not r_icache_cleanup_req[num_cache].read()) 1892 #endif 1893 { 1894 r_icache_update_addr[num_cache] = 0; 1895 r_icache_fsm [num_cache] = ICACHE_MISS_UPDT; 1029 1896 } 1030 // } 1031 // else 1032 // { 1033 // r_icache_inval_rsp = false; 1034 1035 // // Miss read response and invalidation 1036 // if ( r_vci_rsp_ins_error ) 1037 // r_icache_fsm = ICACHE_ERROR; 1038 // else 1039 // r_icache_fsm = ICACHE_CC_CLEANUP; 1040 // } 1897 } 1041 1898 } 1042 1899 break; … … 1046 1903 { 1047 1904 m_cost_ins_miss_frz++; 1048 if ( r_tgt_icache_req ) { // external request1049 r_icache_fsm = ICACHE_CC_CHECK;1050 r_icache_fsm_save = r_icache_fsm.read();1905 if ( r_tgt_icache_req[num_cache] ) { // external request 1906 r_icache_fsm [num_cache] = ICACHE_CC_CHECK; 1907 r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache].read(); 1051 1908 break; 1052 1909 } 1053 1910 1054 bool ok = CACHE_MISS_BUF_RSP_VAL(i,0); 1911 bool ok = CACHE_MISS_BUF_RSP_VAL(i,num_cache,0); 1912 1913 PRINTF(" * <ICACHE [%d]> ok : %d\n",num_cache,ok); 1914 PRINTF(" * <ICACHE [%d]> error : %d\n",num_cache,(uint32_t)r_vci_rsp_ins_error [num_cache]); 1055 1915 1056 1916 if (ok) 1057 1917 { 1058 if ( r_vci_rsp_ins_error ) {1059 r_icache_fsm = ICACHE_ERROR;1918 if ( r_vci_rsp_ins_error [num_cache]) { 1919 r_icache_fsm[num_cache] = ICACHE_ERROR; 1060 1920 } else { 1061 r_icache_fsm = ICACHE_IDLE;1062 r_icache_buf_unc_valid = true;1921 r_icache_fsm [num_cache] = ICACHE_IDLE; 1922 r_icache_buf_unc_valid[num_cache] = true; 1063 1923 } 1064 1924 } … … 1068 1928 case ICACHE_ERROR: 1069 1929 { 1070 if ( (addr_40) ireq.addr == (addr_40)r_icache_addr_save) {1071 irsp.error = true;1072 irsp.valid = true;1073 } 1074 r_icache_fsm = ICACHE_IDLE;1075 r_vci_rsp_ins_error = false;1930 if ( (addr_40)_ireq.addr == (addr_40)r_icache_addr_save[num_cache] ) { 1931 _irsp.error = true; 1932 _irsp.valid = true; 1933 } 1934 r_icache_fsm [num_cache] = ICACHE_IDLE; 1935 r_vci_rsp_ins_error [num_cache] = false; 1076 1936 break; 1077 1937 } … … 1079 1939 case ICACHE_MISS_UPDT: 1080 1940 { 1081 size_t word = r_icache_update_addr.read();1082 vci_addr_t addr = (vci_addr_t) r_icache_addr_save .read();1941 size_t word = r_icache_update_addr[num_cache].read(); 1942 vci_addr_t addr = (vci_addr_t) r_icache_addr_save [num_cache].read(); 1083 1943 size_t way = 0; 1084 1944 size_t set = 0; 1085 1945 1946 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1947 way = r_icache_miss_way[num_cache].read(); 1948 set = r_icache_miss_set[num_cache].read(); 1949 #else 1086 1950 // need invalid rsp, don't select a victim 1087 if (not r_icache_inval_rsp 1951 if (not r_icache_inval_rsp[num_cache]) 1088 1952 { 1089 #if CC_XCACHE_WRAPPER_SELECT_VICTIM1090 way = r_icache_miss_way.read();1091 set = r_icache_miss_set.read();1092 #else1093 1094 1953 // First word : select an victim ! 1095 1954 if (word == 0) … … 1098 1957 1099 1958 // r_icache_cleanup_req is false because is the transition condition to go in ICACHE_MISS_UPDT state 1100 r_icache_cleanup_req = r_icache.victim_select(addr, &victim, &way, &set );1101 r_icache .victim_update_tag(addr, way, set);1959 r_icache_cleanup_req[num_cache] = r_icache[num_cache]->victim_select(addr, &victim, &way, &set ); 1960 r_icache[num_cache]->victim_update_tag(addr, way, set); 1102 1961 1103 r_icache_cleanup_line = (addr_40) victim;1104 r_icache_miss_way = way;1105 r_icache_miss_set = set;1962 r_icache_cleanup_line[num_cache] = (addr_40) victim; 1963 r_icache_miss_way [num_cache] = way; 1964 r_icache_miss_set [num_cache] = set; 1106 1965 } 1107 1966 else 1108 1967 { 1109 way = r_icache_miss_way .read();1110 set = r_icache_miss_set .read();1968 way = r_icache_miss_way[num_cache].read(); 1969 set = r_icache_miss_set[num_cache].read(); 1111 1970 } 1112 #endif 1113 } 1114 bool val = CACHE_MISS_BUF_RSP_VAL(i, word);1971 } 1972 #endif 1973 bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,word); 1115 1974 1116 1975 if (val) 1117 1976 { 1118 PRINTF(" * <ICACHE > rsp_val : %d/%d\n",(int)r_icache_update_addr,m_icache_words);1119 PRINTF(" * <ICACHE > r_icache_inval_rsp : %d\n",(int)r_icache_inval_rsp);1120 PRINTF(" * <ICACHE > ins : %x\n",(int)CACHE_MISS_BUF_RSP_DATA(i,word));1977 PRINTF(" * <ICACHE [%d]> rsp_val : %d/%d\n",num_cache,(int)r_icache_update_addr[num_cache],m_icache_words); 1978 PRINTF(" * <ICACHE [%d]> r_icache_inval_rsp : %d\n" ,num_cache,(int)r_icache_inval_rsp[num_cache]); 1979 PRINTF(" * <ICACHE [%d]> ins : %x\n" ,num_cache,(int)CACHE_MISS_BUF_RSP_DATA(i,num_cache,word)); 1121 1980 1122 1981 // m_cpt_icache_dir_write++; 1123 1982 // m_cpt_icache_data_write++; 1124 // if ( ireq.valid ) m_cost_ins_miss_frz++;1983 // if ( _ireq.valid ) m_cost_ins_miss_frz++; 1125 1984 1126 1985 // if need invalid rsp, don't modify the cache, but pop the buf_rsp 1127 if (not r_icache_inval_rsp ) 1128 r_icache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,word)); 1129 CACHE_MISS_BUF_RSP_POP(i); 1130 1131 r_icache_update_addr = ++word; 1986 if (not r_icache_inval_rsp[num_cache]) 1987 r_icache[num_cache]->write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,num_cache,word)); 1988 1989 CACHE_MISS_BUF_RSP_POP(i,num_cache); 1990 1991 r_icache_update_addr[num_cache] = ++word; 1132 1992 1133 1993 // if last word, finish the update 1134 1994 if (word >= m_icache_words) 1135 1995 { 1996 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1997 // in all case (inval_rsp or not), update the victim tag 1998 r_icache[num_cache]->victim_update_tag(addr, way, set); 1999 #endif 2000 1136 2001 // Last word : if previous invalid_rsp, can cleanup, else update the TAG 1137 if (r_icache_inval_rsp )2002 if (r_icache_inval_rsp[num_cache]) 1138 2003 { 1139 r_icache_inval_rsp 1140 r_icache_fsm = ICACHE_CC_CLEANUP;2004 r_icache_inval_rsp[num_cache] = false; 2005 r_icache_fsm [num_cache] = ICACHE_CC_CLEANUP; 1141 2006 } 1142 2007 else 1143 2008 { 1144 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1145 r_icache.victim_update_tag(addr, way, set); 1146 #endif 1147 r_icache_fsm = ICACHE_IDLE; 2009 r_icache_fsm [num_cache] = ICACHE_IDLE; 1148 2010 } 1149 2011 } … … 1156 2018 { 1157 2019 // external cache invalidate request 1158 if ( r_tgt_icache_req 2020 if ( r_tgt_icache_req[num_cache]) 1159 2021 { 1160 r_icache_fsm = ICACHE_CC_CHECK;1161 r_icache_fsm_save = r_icache_fsm.read();2022 r_icache_fsm [num_cache] = ICACHE_CC_CHECK; 2023 r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache].read(); 1162 2024 break; 1163 2025 } 1164 2026 // cleanup 1165 if(not r_icache_cleanup_req){ 1166 r_icache_cleanup_req = true; 1167 r_icache_cleanup_line = r_icache_addr_save.read() >> m_icache_words_shift; 1168 r_icache_fsm = ICACHE_IDLE; 2027 if(not r_icache_cleanup_req[num_cache]){ 2028 r_icache_cleanup_req [num_cache] = true; 2029 r_icache_cleanup_line[num_cache] = r_icache_addr_save[num_cache].read() >> m_icache_words_shift; 2030 r_icache_fsm [num_cache] = ICACHE_IDLE; 2031 2032 // FIXME : too many access at the cache in this cycle 2033 m_cpt_icache_dir_read += m_icache_ways; 2034 r_icache[num_cache]->inval((addr_40)r_icache_addr_save[num_cache]); 1169 2035 } 1170 2036 break; … … 1176 2042 m_cpt_icache_dir_read += m_icache_ways; 1177 2043 m_cpt_icache_data_read += m_icache_ways; 1178 addr_40 ad = r_tgt_ addr;2044 addr_40 ad = r_tgt_iaddr; 1179 2045 data_t icache_rdata = 0; 1180 2046 1181 if((r_icache_fsm_save == ICACHE_MISS_WAIT) and 1182 ( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) { 1183 r_icache_inval_rsp = true; 1184 r_tgt_icache_req = false; 2047 PRINTF(" * <ICACHE [%d]> CC_CHECK\n",num_cache); 2048 2049 if((r_icache_fsm_save[num_cache] == ICACHE_MISS_WAIT) and 2050 ((r_icache_addr_save[num_cache].read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) { 2051 PRINTF(" * <ICACHE [%d]> have request, need inval rsp\n",num_cache); 2052 2053 r_icache_inval_rsp[num_cache] = true; 2054 r_tgt_icache_req [num_cache] = false; 1185 2055 if(r_tgt_update){ // Also send a cleanup and answer 1186 r_tgt_icache_rsp = true; 2056 PRINTF(" * <ICACHE [%d]> send a cleanup and answer\n",num_cache); 2057 r_tgt_icache_rsp[num_cache] = true; 1187 2058 } else { // Also send a cleanup but don't answer 1188 r_tgt_icache_rsp = false; 2059 PRINTF(" * <ICACHE [%d]> send a cleanup and but don't answer\n",num_cache); 2060 r_tgt_icache_rsp[num_cache] = false; 1189 2061 } 1190 r_icache_fsm = r_icache_fsm_save;2062 r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache]; 1191 2063 } else { 1192 bool icache_hit = r_icache.read(ad, &icache_rdata); 1193 if ( icache_hit and r_tgt_update ) 2064 bool icache_hit = r_icache[num_cache]->read(ad, &icache_rdata); 2065 2066 PRINTF(" * <ICACHE [%d]> have no request, hit cache : %d\n",num_cache,icache_hit); 2067 2068 if ( icache_hit and r_tgt_update) 1194 2069 { 1195 2070 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 1198 2073 data_t rdata = 0; 1199 2074 1200 r_icache .read(ad+word*4,&rdata);2075 r_icache[num_cache]->read(ad+word*4,&rdata); 1201 2076 r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); 1202 2077 … … 1210 2085 if (word==m_icache_words) 1211 2086 { 1212 r_icache_fsm = ICACHE_CC_UPDT;2087 r_icache_fsm[num_cache] = ICACHE_CC_UPDT; 1213 2088 1214 2089 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT … … 1222 2097 r_cache_word = word; 1223 2098 #else //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1224 r_icache_fsm = ICACHE_CC_UPDT;2099 r_icache_fsm[num_cache] = ICACHE_CC_UPDT; 1225 2100 // complete the line buffer in case of update 1226 2101 for(size_t i=0; i<m_icache_words; i++){ 1227 2102 data_t rdata = 0; 1228 r_icache .read(ad + i*4,&rdata);2103 r_icache[num_cache]->read(ad + i*4,&rdata); 1229 2104 data_t mask = vci_param::be2mask(r_tgt_be[i]); 1230 2105 r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata); 1231 2106 } 1232 2107 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1233 } else if ( icache_hit and not r_tgt_update 1234 r_icache_fsm = ICACHE_CC_INVAL;2108 } else if ( icache_hit and not r_tgt_update) { 2109 r_icache_fsm[num_cache] = ICACHE_CC_INVAL; 1235 2110 } else { // instruction not found (can happen) 1236 r_tgt_icache_req = false;2111 r_tgt_icache_req[num_cache] = false; 1237 2112 if(r_tgt_update){ 1238 r_tgt_icache_rsp = true;2113 r_tgt_icache_rsp[num_cache] = true; 1239 2114 } else { 1240 r_tgt_icache_rsp = false;2115 r_tgt_icache_rsp[num_cache] = false; 1241 2116 } 1242 r_icache_fsm = r_icache_fsm_save;2117 r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache]; 1243 2118 } 1244 2119 } … … 1248 2123 case ICACHE_CC_INVAL: 1249 2124 { 1250 addr_40 ad = r_tgt_addr;1251 if (ireq.valid ) m_cost_ins_miss_frz++;2125 addr_40 ad = r_tgt_iaddr; 2126 // if ( _ireq.valid ) m_cost_ins_miss_frz++; 1252 2127 m_cpt_icache_dir_read += m_icache_ways; 1253 r_tgt_icache_rsp = true;1254 r_icache .inval(ad);1255 r_tgt_icache_req = false;1256 r_icache_fsm = r_icache_fsm_save;2128 r_tgt_icache_rsp[num_cache] = true; 2129 r_icache[num_cache]->inval(ad); 2130 r_tgt_icache_req[num_cache] = false; 2131 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache]; 1257 2132 break; 1258 2133 } … … 1260 2135 case ICACHE_CC_UPDT: 1261 2136 { 1262 addr_40 ad = r_tgt_ addr.read();2137 addr_40 ad = r_tgt_iaddr.read(); 1263 2138 m_cpt_icache_dir_write++; 1264 2139 m_cpt_icache_data_write++; … … 1268 2143 1269 2144 if(r_tgt_be[word]) 1270 r_icache .write(ad+word*4, r_tgt_buf[word]);2145 r_icache[num_cache]->write(ad+word*4, r_tgt_buf[word]); 1271 2146 1272 2147 word ++; … … 1279 2154 if (word==m_icache_words) 1280 2155 { 1281 r_tgt_icache_req = false;1282 r_tgt_icache_rsp = true;1283 r_icache_fsm = r_icache_fsm_save.read();2156 r_tgt_icache_req[num_cache] = false; 2157 r_tgt_icache_rsp[num_cache] = true; 2158 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache].read(); 1284 2159 word = 0; 1285 2160 } … … 1288 2163 data_t* buf = r_tgt_buf; 1289 2164 for(size_t i=0; i<m_icache_words;i++){ 1290 if(r_tgt_be[i]) r_icache .write( ad + i*4, buf[i]);1291 } 1292 r_tgt_icache_req = false;1293 r_tgt_icache_rsp = true;1294 r_icache_fsm = r_icache_fsm_save.read();2165 if(r_tgt_be[i]) r_icache[num_cache]->write( ad + i*4, buf[i]); 2166 } 2167 r_tgt_icache_req [num_cache] = false; 2168 r_tgt_icache_rsp [num_cache] = true; 2169 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache].read(); 1295 2170 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1296 2171 … … 1298 2173 } 1299 2174 1300 } // end switch r_icache_fsm 1301 1302 #if CC_XCACHE_WRAPPER_DEBUG 1303 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1304 std::cout << " * Instruction Response : " << irsp << std::endl; 1305 #endif 2175 }// end switch r_icache_fsm 2176 2177 irsp [num_cache] = _irsp; 2178 if (_ireq.valid and _irsp.valid) 2179 { 2180 PRINTF(" * <CPU2CACHE> Transaction between cpu %d and Icache %d (unlock)\n",r_icache_lock [num_cache].read(),num_cache); 2181 2182 r_icache_lock [num_cache] = m_nb_cpu; 2183 m_cpt_icache_access [num_cache] ++; 2184 } 2185 2186 }// end for num_cache 1306 2187 1307 2188 //////////////////////////////////////////////////////////////////////:///////////// … … 1361 2242 /////////////////////////////////////////////////////////////////////////////////// 1362 2243 1363 #if CC_XCACHE_WRAPPER_DEBUG 1364 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)1365 std::cout << " * Data Request : " << dreq << std::endl;1366 #endif 1367 1368 switch ( r_dcache_fsm 2244 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 2245 { 2246 typename iss_t::DataRequest _dreq = dreq [num_cache]; 2247 typename iss_t::DataResponse _drsp = ISS_DRSP_INITIALIZER; 2248 2249 switch ( r_dcache_fsm[num_cache]) { 1369 2250 1370 2251 ///////////////// 1371 2252 case DCACHE_IDLE: 1372 2253 { 1373 if ( r_tgt_dcache_req 1374 r_dcache_fsm = DCACHE_CC_CHECK;1375 r_dcache_fsm_save = r_dcache_fsm;2254 if ( r_tgt_dcache_req[num_cache]) { // external request 2255 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; 2256 r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache]; 1376 2257 break; 1377 2258 } 1378 2259 1379 if ( dreq.valid ) {1380 PRINTF(" * <DCACHE > Have dreq\n");2260 if ( _dreq.valid ) { 2261 PRINTF(" * <DCACHE [%d]> Have dreq\n",num_cache); 1381 2262 1382 2263 data_t dcache_rdata = 0; 1383 // dcache_cached and dcache_hit don't used with dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} 1384 bool dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr]; 1385 bool dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); 1386 bool dcache_cleanup_hit = r_dcache_cleanup_req and (((addr_40)dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line.read()); 1387 1388 PRINTF(" * <DCACHE> hit %d - cached %d - cleanup_hit %d\n",dcache_hit, dcache_cached, dcache_cleanup_hit); 2264 // dcache_cached and dcache_hit don't used with _dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} 2265 bool dcache_cached = dreq_cached [num_cache]; 2266 uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; 2267 bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); 2268 bool dcache_cleanup_hit = r_dcache_cleanup_req[num_cache] and (((addr_40)_dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line[num_cache].read()); 2269 2270 PRINTF(" * <DCACHE [%d]> hit %d - cached %d - cleanup_hit %d\n",num_cache,dcache_hit, dcache_cached, dcache_cleanup_hit); 1389 2271 1390 2272 m_cpt_dcache_data_read += m_dcache_ways; 1391 2273 m_cpt_dcache_dir_read += m_dcache_ways; 1392 2274 1393 switch( dreq.type ) {2275 switch( _dreq.type ) { 1394 2276 case iss_t::DATA_READ: 1395 2277 case iss_t::DATA_LL: … … 1400 2282 { 1401 2283 // address is in the cache : return the word 1402 r_dcache_fsm = DCACHE_IDLE; 1403 drsp.valid = true; 1404 drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) 2284 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2285 2286 _drsp.valid = true; 2287 _drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) 1405 2288 1406 2289 // if the request is a Load Linked instruction, save request information 1407 if( dreq.type == iss_t::DATA_LL)2290 if(_dreq.type == iss_t::DATA_LL) 1408 2291 { 1409 PRINTF(" * <DCACHE > ll_valid = true\n");1410 1411 r_dcache_ll_valid = true;1412 r_dcache_ll_data = dcache_rdata;1413 r_dcache_ll_addr = (vci_addr_t)dreq.addr;2292 PRINTF(" * <DCACHE [%d]> ll_valid = true\n",num_cache); 2293 2294 r_dcache_ll_valid [num_cache][dcache_num_cpu] = true; 2295 r_dcache_ll_data [num_cache][dcache_num_cpu] = dcache_rdata; 2296 r_dcache_ll_addr [num_cache][dcache_num_cpu] = (vci_addr_t) _dreq.addr; 1414 2297 #ifdef COHERENCE_DEBUG 1415 std::cout << "Value returned for LL at address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;1416 r_dcache .read((vci_addr_t)dreq.addr, &dcache_rdata);1417 std::cout << "Value stored at this address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;2298 std::cout << "Value returned for LL at address : " << std::hex << _dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; 2299 r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); 2300 std::cout << "Value stored at this address : " << std::hex << _dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; 1418 2301 #endif 1419 2302 } … … 1423 2306 if (not dcache_cleanup_hit) 1424 2307 { 1425 CACHE_MISS_BUF_REQ_INIT(d );2308 CACHE_MISS_BUF_REQ_INIT(d,num_cache); 1426 2309 1427 2310 // Miss : send signal at the CMD_FSM (via r_dcache_miss_req or r_dcache_unc_req) … … 1429 2312 m_cpt_data_read_miss++; 1430 2313 m_cost_data_miss_frz++; 1431 r_dcache_miss_req = true;2314 r_dcache_miss_req [num_cache] = true; 1432 2315 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1433 r_dcache_fsm = DCACHE_MISS_VICTIM;2316 r_dcache_fsm [num_cache] = DCACHE_MISS_VICTIM; 1434 2317 #else 1435 r_dcache_fsm = DCACHE_MISS_WAIT;2318 r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT; 1436 2319 #endif 1437 2320 1438 2321 } else { 1439 if (not r_dcache_previous_unc .read()) // strongly order to the uncached access2322 if (not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access 1440 2323 { 1441 r_dcache_previous_unc = true;2324 r_dcache_previous_unc[num_cache] = true; 1442 2325 1443 2326 m_cpt_data_read_uncached++; 1444 2327 m_cost_unc_read_frz++; 1445 r_dcache_unc_req = true;1446 r_dcache_fsm = DCACHE_UNC_WAIT;2328 r_dcache_unc_req[num_cache] = true; 2329 r_dcache_fsm [num_cache] = DCACHE_UNC_WAIT; 1447 2330 } 1448 2331 } … … 1453 2336 case iss_t::DATA_SC: 1454 2337 { 1455 PRINTF(" * <DCACHE > DATA_SC - ll_valid = %d\n",r_dcache_ll_valid.read());1456 1457 if (not r_dcache_previous_unc .read() and not dcache_cleanup_hit) // strongly order to the uncached access2338 PRINTF(" * <DCACHE [%d]> DATA_SC - ll_valid = %d, num_cpu = %d\n",num_cache,r_dcache_ll_valid[num_cache][dcache_num_cpu].read(),dcache_num_cpu); 2339 2340 if (not r_dcache_previous_unc[num_cache].read() and not dcache_cleanup_hit) // strongly order to the uncached access 1458 2341 { 1459 2342 //m_cpt_data_read_unc++; // instruction must read the memory in uncached mode … … 1462 2345 // if previous load linked (with the same address), make a transaction 1463 2346 // else, keep in IDLE state and return 1 (no OK) 1464 if(r_dcache_ll_valid.read() and (r_dcache_ll_addr.read() == (vci_addr_t)dreq.addr)){ 1465 PRINTF(" * <DCACHE> have previous load linked\n"); 2347 if( r_dcache_ll_valid[num_cache][dcache_num_cpu].read() and 2348 (r_dcache_ll_addr [num_cache][dcache_num_cpu].read() == (vci_addr_t)_dreq.addr)){ 2349 PRINTF(" * <DCACHE [%d]> have previous load linked\n",num_cache); 1466 2350 1467 r_dcache_previous_unc = true; 1468 1469 r_dcache_sc_req = true; 1470 1471 CACHE_MISS_BUF_REQ_INIT(d); 1472 1473 r_dcache_fsm = DCACHE_SC_WAIT; 2351 r_dcache_previous_unc[num_cache] = true; 2352 r_dcache_sc_req [num_cache] = true; 2353 2354 CACHE_MISS_BUF_REQ_INIT(d,num_cache); 2355 2356 r_dcache_fsm [num_cache] = DCACHE_SC_WAIT; 1474 2357 } else { 1475 PRINTF(" * <DCACHE > don't have previous load linked\n");2358 PRINTF(" * <DCACHE [%d]> don't have previous load linked\n",num_cache); 1476 2359 1477 drsp.valid = true;1478 drsp.rdata = 1; // SC rsp NOK1479 r_dcache_ll_valid = false;2360 _drsp.valid = true; 2361 _drsp.rdata = 1; // SC rsp NOK 2362 r_dcache_ll_valid[num_cache][dcache_num_cpu] = false; 1480 2363 } 1481 2364 } … … 1486 2369 case iss_t::XTN_WRITE: 1487 2370 { 1488 bool drsp_valid = false;2371 bool valid = false; 1489 2372 // only DCACHE INVALIDATE and SYNC request are supported 1490 switch ( dreq.addr>>2)2373 switch (_dreq.addr>>2) 1491 2374 { 1492 2375 case iss_t::XTN_DCACHE_INVAL : 1493 2376 { 1494 drsp_valid = true;1495 r_dcache_fsm = DCACHE_INVAL;2377 valid = true; 2378 r_dcache_fsm[num_cache] = DCACHE_INVAL; 1496 2379 break; 1497 2380 } … … 1501 2384 // * gain : 1 cycle 1502 2385 // * cost : can be on the critical path 1503 if (r_wbuf.empty()) 2386 2387 bool empty=true; 2388 for (uint32_t i=0; i<m_nb_dcache; ++i) 2389 empty &= r_wbuf[i]->empty(); 2390 2391 if (empty) 1504 2392 { 1505 drsp_valid = true;1506 r_dcache_fsm = DCACHE_IDLE;2393 valid = true; 2394 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1507 2395 } 1508 2396 else 1509 2397 { 1510 drsp_valid = false; 1511 r_dcache_fsm = DCACHE_SYNC; 2398 valid = false; 2399 r_dcache_fsm [num_cache] = DCACHE_SYNC; 2400 r_dcache_sync[num_cache] = true; 1512 2401 } 1513 2402 break; … … 1516 2405 { 1517 2406 // std::cout << "Warning in VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 1518 // std::cout << "Unsupported external access : " << ( dreq.addr>>2) << std::endl;1519 1520 r_dcache_fsm = DCACHE_IDLE;2407 // std::cout << "Unsupported external access : " << (_dreq.addr>>2) << std::endl; 2408 2409 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1521 2410 } 1522 }//end switch ( dreq.addr>>2)1523 1524 drsp.valid = drsp_valid;1525 drsp.rdata = 0;2411 }//end switch (_dreq.addr>>2) 2412 2413 _drsp.valid = valid; 2414 _drsp.rdata = 0; 1526 2415 break; 1527 2416 } 1528 2417 case iss_t::DATA_WRITE: 1529 2418 1530 if (dcache_cached or not r_dcache_previous_unc.read()) // strongly order to the uncached access 2419 PRINTF(" * <DCACHE [%d]> r_dcache_previous_unc : %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); 2420 2421 if (dcache_cached or not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access 1531 2422 { 1532 bool drsp_valid; 1533 1534 drsp_valid = r_wbuf.write((addr_40) dreq.addr, dreq.be, dreq.wdata, dcache_cached); 1535 1536 if (drsp_valid) 2423 bool valid; 2424 addr_40 addr = _dreq.addr; 2425 set_num_dcache(addr,num_cache); 2426 2427 // FIXME : virer le set_num_dcache ! 2428 valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached); 2429 2430 PRINTF(" * <DCACHE [%d]> r_wbuf valid : %d\n",num_cache,valid); 2431 2432 if (valid) 1537 2433 { 1538 2434 m_cpt_data_write++; … … 1540 2436 if (not dcache_cached) 1541 2437 { 1542 r_dcache_previous_unc = true;2438 r_dcache_previous_unc[num_cache] = true; 1543 2439 m_cpt_data_write_uncached++; 1544 2440 } … … 1546 2442 m_cpt_data_write_miss++; 1547 2443 1548 if ( dcache_hit) { 1549 r_dcache_fsm = DCACHE_WRITE_UPDT; 2444 if (dcache_hit) { 2445 // update data cache 2446 r_dcache_fsm[num_cache] = DCACHE_WRITE_UPDT; 1550 2447 } else { 1551 r_dcache_fsm = DCACHE_IDLE; 2448 // write accepted 2449 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1552 2450 } 1553 2451 } 1554 2452 1555 drsp.valid = drsp_valid;1556 drsp.rdata = 0;2453 _drsp.valid = valid; 2454 _drsp.rdata = 0; 1557 2455 } 1558 2456 break; 1559 } // end switch dreq.type 1560 1561 r_dcache_addr_save = (addr_40) dreq.addr; 1562 r_dcache_type_save = dreq.type; 1563 r_dcache_wdata_save = dreq.wdata; 1564 r_dcache_be_save = dreq.be; 1565 r_dcache_rdata_save = dcache_rdata; 1566 r_dcache_cached_save = dcache_cached; 1567 1568 } else { // end if dreq.valid 1569 r_dcache_fsm = DCACHE_IDLE; 2457 } // end switch _dreq.type 2458 2459 r_dcache_addr_save [num_cache] = (addr_40) _dreq.addr; 2460 r_dcache_type_save [num_cache] = _dreq.type; 2461 r_dcache_wdata_save [num_cache] = _dreq.wdata; 2462 r_dcache_be_save [num_cache] = _dreq.be; 2463 r_dcache_rdata_save [num_cache] = dcache_rdata; 2464 r_dcache_cached_save [num_cache] = dcache_cached; 2465 r_dcache_num_cpu_save[num_cache] = dcache_num_cpu; 2466 2467 } else { // end if _dreq.valid 2468 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1570 2469 } 1571 2470 … … 1576 2475 { 1577 2476 m_cpt_dcache_data_write++; 1578 data_t mask = vci_param::be2mask(r_dcache_be_save );1579 data_t wdata = (mask & r_dcache_wdata_save ) | (~mask & r_dcache_rdata_save);1580 vci_addr_t ad = r_dcache_addr_save .read();1581 r_dcache .write(ad, wdata);1582 1583 r_dcache_fsm = DCACHE_IDLE;2477 data_t mask = vci_param::be2mask(r_dcache_be_save[num_cache]); 2478 data_t wdata = (mask & r_dcache_wdata_save[num_cache]) | (~mask & r_dcache_rdata_save[num_cache]); 2479 vci_addr_t ad = r_dcache_addr_save[num_cache].read(); 2480 r_dcache[num_cache]->write(ad, wdata); 2481 2482 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1584 2483 1585 2484 break; … … 1589 2488 case DCACHE_MISS_VICTIM: 1590 2489 { 1591 if (not r_dcache_cleanup_req .read())2490 if (not r_dcache_cleanup_req[num_cache].read()) 1592 2491 { 1593 2492 size_t way; 1594 2493 size_t set; 1595 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save .read();2494 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save[num_cache].read(); 1596 2495 vci_addr_t victim; 2496 bool victim_val = r_dcache[num_cache]->victim_select(addr, &victim, &way, &set ); 1597 2497 1598 r_dcache_cleanup_req = r_dcache.victim_select(addr, &victim, &way, &set ); 1599 r_dcache_cleanup_line = (addr_40) victim; 1600 r_dcache_miss_way = way; 1601 r_dcache_miss_set = set; 1602 1603 r_dcache_fsm = DCACHE_MISS_WAIT; 2498 r_dcache_cleanup_req [num_cache] = victim_val; 2499 r_dcache_cleanup_line [num_cache] = (addr_40) victim; 2500 r_dcache_miss_way [num_cache] = way; 2501 r_dcache_miss_set [num_cache] = set; 2502 2503 PRINTF(" * <DCACHE [%d]> MISS_VICTIM : Victim %d - %llx (way %d, set %d)\n",num_cache,victim_val, (uint64_t)victim, way, set); 2504 2505 r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT; 1604 2506 } 1605 2507 … … 1611 2513 { 1612 2514 1613 if (dreq.valid ) m_cost_data_miss_frz++;1614 if ( r_tgt_dcache_req .read() ) { // external request1615 r_dcache_fsm = DCACHE_CC_CHECK;1616 r_dcache_fsm_save = r_dcache_fsm;2515 // if ( _dreq.valid ) m_cost_data_miss_frz++; 2516 if ( r_tgt_dcache_req[num_cache].read() ) { // external request 2517 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; 2518 r_dcache_fsm_save [num_cache] = r_dcache_fsm[num_cache]; 1617 2519 break; 1618 2520 } 1619 2521 1620 bool val = CACHE_MISS_BUF_RSP_VAL(d, 0);2522 bool val = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0); 1621 2523 if (val) 1622 2524 { 1623 // if (not r_dcache_inval_rsp )1624 // {1625 1626 2525 // Miss read response and no invalidation 1627 if ( r_vci_rsp_data_error)2526 if (r_vci_rsp_data_error[num_cache]) 1628 2527 { 1629 r_dcache_fsm = DCACHE_ERROR;2528 r_dcache_fsm [num_cache] = DCACHE_ERROR; 1630 2529 } 1631 2530 else 1632 2531 { 1633 2532 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM 1634 if (not r_dcache_cleanup_req .read())2533 if (not r_dcache_cleanup_req[num_cache].read()) 1635 2534 #endif 1636 2535 { 1637 r_dcache_update_addr = 0;1638 r_dcache_fsm = DCACHE_MISS_UPDT;2536 r_dcache_update_addr[num_cache] = 0; 2537 r_dcache_fsm [num_cache] = DCACHE_MISS_UPDT; 1639 2538 } 1640 2539 } 1641 // }1642 // else1643 // {1644 // r_dcache_inval_rsp = false;1645 1646 // // Miss read response and invalidation1647 // if ( r_vci_rsp_data_error ) {1648 // r_dcache_fsm = DCACHE_ERROR;1649 // } else {1650 // r_dcache_fsm = DCACHE_CC_CLEANUP;1651 // }1652 // }1653 2540 } 1654 2541 break; … … 1657 2544 case DCACHE_MISS_UPDT: 1658 2545 { 1659 size_t word = r_dcache_update_addr .read();1660 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save .read();2546 size_t word = r_dcache_update_addr[num_cache].read(); 2547 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save[num_cache].read(); 1661 2548 size_t way = 0; 1662 2549 size_t set = 0; 1663 2550 1664 2551 // need invalid rsp, don't select a victim 1665 if (not r_dcache_inval_rsp ) 2552 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 2553 way = r_dcache_miss_way[num_cache].read(); 2554 set = r_dcache_miss_set[num_cache].read(); 2555 #else 2556 if (not r_dcache_inval_rsp[num_cache] ) 1666 2557 { 1667 #if CC_XCACHE_WRAPPER_SELECT_VICTIM1668 way = r_dcache_miss_way.read();1669 set = r_dcache_miss_set.read();1670 #else1671 2558 // First word : select an victim ! 1672 2559 if (word == 0) … … 1675 2562 1676 2563 // r_dcache_cleanup_req is false (condition to enter in DCACHE_MISS_UPDT 1677 r_dcache_cleanup_req = r_dcache.victim_select(addr, &victim, &way, &set );1678 r_dcache .victim_update_tag(addr, way, set);1679 r_dcache_cleanup_line = (addr_40) victim;1680 1681 r_dcache_miss_way 1682 r_dcache_miss_set 2564 r_dcache_cleanup_req [num_cache] = r_dcache[num_cache]->victim_select(addr, &victim, &way, &set ); 2565 r_dcache[num_cache]->victim_update_tag(addr, way, set); 2566 r_dcache_cleanup_line[num_cache] = (addr_40) victim; 2567 2568 r_dcache_miss_way [num_cache] = way; 2569 r_dcache_miss_set [num_cache] = set; 1683 2570 } 1684 2571 else 1685 2572 { 1686 way = r_dcache_miss_way .read();1687 set = r_dcache_miss_set .read();2573 way = r_dcache_miss_way[num_cache].read(); 2574 set = r_dcache_miss_set[num_cache].read(); 1688 2575 } 1689 #endif 1690 } 1691 1692 bool val = CACHE_MISS_BUF_RSP_VAL(d,word); 1693 if (val) 2576 } 2577 #endif 2578 2579 PRINTF(" * <DCACHE [%d]> MISS_UPDT : Victim way %d, set %d\n",num_cache, way, set); 2580 2581 if (CACHE_MISS_BUF_RSP_VAL(d,num_cache,word)) 1694 2582 { 1695 2583 // m_cpt_dcache_dir_write++; 1696 // if ( ireq.valid ) m_cost_data_miss_frz++;2584 // if ( _dreq.valid ) m_cost_data_miss_frz++; 1697 2585 1698 2586 // if need invalid rsp, don't modify the cache, but pop the buf_rsp 1699 if (not r_dcache_inval_rsp ) 2587 // (power save) 2588 if (not r_dcache_inval_rsp[num_cache]) 1700 2589 { 1701 r_dcache .write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,word));2590 r_dcache[num_cache]->write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,num_cache,word)); 1702 2591 m_cpt_dcache_data_write++; 1703 2592 } 1704 2593 1705 CACHE_MISS_BUF_RSP_POP(d );1706 r_dcache_update_addr = ++word;2594 CACHE_MISS_BUF_RSP_POP(d,num_cache); 2595 r_dcache_update_addr[num_cache] = ++word; 1707 2596 1708 2597 // if last word, finish the update 1709 2598 if (word >= m_dcache_words) 1710 2599 { 2600 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 2601 // in all case (inval_rsp or not), update the victim tag 2602 // because victim is already cleanup 2603 r_dcache[num_cache]->victim_update_tag(addr, way, set); 2604 #endif 2605 1711 2606 // Last word : if previous invalid_rsp, can cleanup, else update the TAG 1712 if (r_dcache_inval_rsp )2607 if (r_dcache_inval_rsp[num_cache]) 1713 2608 { 1714 r_dcache_inval_rsp 1715 r_dcache_fsm = DCACHE_CC_CLEANUP;2609 r_dcache_inval_rsp[num_cache] = false; 2610 r_dcache_fsm [num_cache] = DCACHE_CC_CLEANUP; 1716 2611 } 1717 2612 else 1718 2613 { 1719 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1720 r_dcache.victim_update_tag(addr, way, set); 1721 #endif 1722 r_dcache_fsm = DCACHE_IDLE; 2614 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1723 2615 } 1724 2616 } … … 1730 2622 case DCACHE_UNC_WAIT: 1731 2623 { 1732 if (dreq.valid ) m_cost_unc_read_frz++;1733 if ( r_tgt_dcache_req ) { // external request1734 r_dcache_fsm = DCACHE_CC_CHECK;1735 r_dcache_fsm_save = r_dcache_fsm;2624 // if ( _dreq.valid ) m_cost_unc_read_frz++; 2625 if ( r_tgt_dcache_req[num_cache] ) { // external request 2626 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; 2627 r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache]; 1736 2628 break; 1737 2629 } 1738 2630 1739 bool ok = CACHE_MISS_BUF_RSP_VAL(d, 0);2631 bool ok = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0); 1740 2632 1741 2633 if (ok) { 1742 if ( r_vci_rsp_data_error) {1743 r_dcache_fsm = DCACHE_ERROR;2634 if (r_vci_rsp_data_error[num_cache]) { 2635 r_dcache_fsm[num_cache] = DCACHE_ERROR; 1744 2636 } else { 1745 data_t rdata = CACHE_MISS_BUF_RSP_DATA(d, 0);1746 CACHE_MISS_BUF_RSP_POP(d );1747 1748 if( dreq.type == iss_t::DATA_LL){1749 PRINTF(" * <DCACHE > ll_valid = true\n");1750 1751 r_dcache_ll_valid = true;1752 r_dcache_ll_data = rdata;1753 r_dcache_ll_addr = (vci_addr_t)dreq.addr;2637 data_t rdata = CACHE_MISS_BUF_RSP_DATA(d,num_cache,0); 2638 CACHE_MISS_BUF_RSP_POP(d,num_cache); 2639 2640 if(_dreq.type == iss_t::DATA_LL){ 2641 PRINTF(" * <DCACHE [%d]> ll_valid = true\n",num_cache); 2642 2643 r_dcache_ll_valid [num_cache][r_dcache_num_cpu_save[num_cache]] = true; 2644 r_dcache_ll_data [num_cache][r_dcache_num_cpu_save[num_cache]] = rdata; 2645 r_dcache_ll_addr [num_cache][r_dcache_num_cpu_save[num_cache]] = (vci_addr_t) _dreq.addr; 1754 2646 } 1755 r_dcache_fsm = DCACHE_IDLE; 1756 drsp.valid = true; 1757 drsp.rdata = rdata; 2647 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2648 2649 _drsp.valid = true; 2650 _drsp.rdata = rdata; 1758 2651 } 1759 2652 } … … 1763 2656 case DCACHE_SC_WAIT: 1764 2657 { 1765 if (dreq.valid ) m_cost_unc_read_frz++;1766 if ( r_tgt_dcache_req ) { // external request1767 r_dcache_fsm = DCACHE_CC_CHECK;1768 r_dcache_fsm_save = r_dcache_fsm;2658 // if ( _dreq.valid ) m_cost_unc_read_frz++; 2659 if ( r_tgt_dcache_req[num_cache] ) { // external request 2660 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; 2661 r_dcache_fsm_save [num_cache] = r_dcache_fsm [num_cache]; 1769 2662 break; 1770 2663 } 1771 2664 1772 bool ok = CACHE_MISS_BUF_RSP_VAL(d, 0);2665 bool ok = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0); 1773 2666 1774 2667 if (ok) { 1775 if ( r_vci_rsp_data_error) {1776 r_dcache_fsm = DCACHE_ERROR;2668 if (r_vci_rsp_data_error[num_cache]) { 2669 r_dcache_fsm [num_cache] = DCACHE_ERROR; 1777 2670 } else { 1778 r_dcache_fsm = DCACHE_IDLE; 1779 drsp.valid = true; 1780 drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,0); 1781 CACHE_MISS_BUF_RSP_POP(d); 1782 r_dcache_ll_valid = false; 2671 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2672 2673 _drsp.valid = true; 2674 _drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,num_cache,0); 2675 CACHE_MISS_BUF_RSP_POP(d,num_cache); 2676 r_dcache_ll_valid [num_cache][r_dcache_num_cpu_save[num_cache]] = false; 1783 2677 } 1784 2678 } … … 1789 2683 case DCACHE_ERROR: 1790 2684 { 1791 r_dcache_fsm = DCACHE_IDLE; 1792 r_vci_rsp_data_error = false; 1793 drsp.error = true; 1794 drsp.valid = true; 2685 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2686 2687 r_vci_rsp_data_error[num_cache] = false; 2688 _drsp.error = true; 2689 _drsp.valid = true; 1795 2690 break; 1796 2691 } … … 1798 2693 case DCACHE_INVAL: 1799 2694 { 1800 if ( r_tgt_dcache_req .read() ) { // external request1801 r_dcache_fsm = DCACHE_CC_CHECK;1802 r_dcache_fsm_save = r_dcache_fsm;2695 if ( r_tgt_dcache_req[num_cache].read() ) { // external request 2696 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; 2697 r_dcache_fsm_save [num_cache] = r_dcache_fsm [num_cache]; 1803 2698 break; 1804 2699 } 1805 if( not r_dcache_cleanup_req .read() ){2700 if( not r_dcache_cleanup_req [num_cache].read() ){ 1806 2701 m_cpt_dcache_dir_read += m_dcache_ways; 1807 vci_addr_t ad = r_dcache_addr_save .read();1808 r_dcache_cleanup_req = r_dcache.inval(ad);1809 r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift;1810 1811 r_dcache_fsm = DCACHE_IDLE;2702 vci_addr_t ad = r_dcache_addr_save [num_cache].read(); 2703 r_dcache_cleanup_req [num_cache] = r_dcache[num_cache]->inval(ad); 2704 r_dcache_cleanup_line [num_cache] = r_dcache_addr_save [num_cache].read() >> m_dcache_words_shift; 2705 2706 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1812 2707 } 1813 2708 break; … … 1815 2710 case DCACHE_SYNC : 1816 2711 { 1817 if ( r_tgt_dcache_req ) { // external request1818 r_dcache_fsm = DCACHE_CC_CHECK;1819 r_dcache_fsm_save = r_dcache_fsm;2712 if ( r_tgt_dcache_req[num_cache] ) { // external request 2713 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; 2714 r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache]; 1820 2715 break; 1821 2716 } 1822 2717 1823 if (r_wbuf.empty()) 1824 { 1825 drsp.valid = true; // end, can accept the sync request 1826 r_dcache_fsm = DCACHE_IDLE; 1827 } 2718 bool empty=true; 2719 for (uint32_t i=0; i<m_nb_dcache; ++i) 2720 empty &= r_wbuf[i]->empty(); 2721 2722 if (empty) 2723 { 2724 _drsp.valid = true; // end, can accept the sync request 2725 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2726 r_dcache_sync[num_cache] = false; 2727 } 1828 2728 break; 1829 2729 } … … 1831 2731 case DCACHE_CC_CHECK: // read directory in case of invalidate or update request 1832 2732 { 1833 addr_40 ad = r_tgt_ addr;2733 addr_40 ad = r_tgt_daddr; 1834 2734 data_t dcache_rdata = 0; 1835 2735 1836 if((r_dcache_fsm_save == DCACHE_MISS_WAIT) and 1837 ( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { 1838 r_dcache_inval_rsp = true; 1839 r_tgt_dcache_req = false; 2736 PRINTF(" * <DCACHE [%d]> CC_CHECK\n",num_cache); 2737 2738 if((r_dcache_fsm_save[num_cache] == DCACHE_MISS_WAIT) and 2739 ((r_dcache_addr_save[num_cache].read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { 2740 PRINTF(" * <DCACHE [%d]> have request, need inval rsp\n",num_cache); 2741 2742 r_dcache_inval_rsp[num_cache] = true; 2743 r_tgt_dcache_req [num_cache] = false; 1840 2744 if(r_tgt_update){ // Also send a cleanup and answer 1841 r_tgt_dcache_rsp = true; 2745 PRINTF(" * <DCACHE [%d]> send a cleanup and answer\n",num_cache); 2746 r_tgt_dcache_rsp[num_cache] = true; 1842 2747 } else { // Also send a cleanup but don't answer 1843 r_tgt_dcache_rsp = false; 2748 PRINTF(" * <DCACHE [%d]> send a cleanup and but don't answer\n",num_cache); 2749 r_tgt_dcache_rsp[num_cache] = false; 1844 2750 } 1845 r_dcache_fsm = r_dcache_fsm_save;2751 r_dcache_fsm[num_cache] = r_dcache_fsm_save[num_cache]; 1846 2752 } else { 1847 bool dcache_hit = r_dcache.read(ad, &dcache_rdata); 2753 bool dcache_hit = r_dcache[num_cache]->read(ad, &dcache_rdata); 2754 2755 PRINTF(" * <DCACHE [%d]> have no request, hit cache : %d, update : %d\n",num_cache,dcache_hit,(uint32_t)r_tgt_update); 1848 2756 1849 2757 m_cpt_dcache_data_read += m_dcache_ways; … … 1860 2768 data_t rdata = 0; 1861 2769 1862 r_dcache .read(ad+word*4,&rdata);2770 r_dcache[num_cache]->read(ad+word*4,&rdata); 1863 2771 1864 2772 r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); … … 1873 2781 if (word==m_dcache_words) 1874 2782 { 1875 r_dcache_fsm = DCACHE_CC_UPDT;2783 r_dcache_fsm[num_cache] = DCACHE_CC_UPDT; 1876 2784 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1877 2785 for (word=0; word<m_dcache_words; ++word) … … 1887 2795 for(size_t i=0; i<m_dcache_words; i++){ 1888 2796 data_t rdata = 0; 1889 r_dcache .read(ad + i*4,&rdata);2797 r_dcache[num_cache]->read(ad + i*4,&rdata); 1890 2798 data_t mask = vci_param::be2mask(r_tgt_be[i]); 1891 2799 r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata); 1892 2800 } 1893 r_dcache_fsm = DCACHE_CC_UPDT;2801 r_dcache_fsm[num_cache] = DCACHE_CC_UPDT; 1894 2802 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1895 2803 } else if ( dcache_hit and not r_tgt_update ) { 1896 r_dcache_fsm = DCACHE_CC_INVAL;2804 r_dcache_fsm[num_cache] = DCACHE_CC_INVAL; 1897 2805 } else { 1898 2806 if(r_tgt_update){ 1899 r_tgt_dcache_rsp = true;2807 r_tgt_dcache_rsp[num_cache] = true; 1900 2808 } else { 1901 r_tgt_dcache_rsp = false;2809 r_tgt_dcache_rsp[num_cache] = false; 1902 2810 } 1903 r_tgt_dcache_req = false;1904 r_dcache_fsm = r_dcache_fsm_save;2811 r_tgt_dcache_req[num_cache] = false; 2812 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; 1905 2813 } 1906 2814 } … … 1910 2818 case DCACHE_CC_UPDT: // update directory and data cache 1911 2819 { 1912 addr_40 ad = r_tgt_ addr;2820 addr_40 ad = r_tgt_daddr; 1913 2821 1914 2822 m_cpt_dcache_dir_write++; … … 1923 2831 1924 2832 if(r_tgt_be[word]) 1925 r_dcache .write(ad+word*4, r_tgt_buf[word]);2833 r_dcache[num_cache]->write(ad+word*4, r_tgt_buf[word]); 1926 2834 # ifdef COHERENCE_DEBUG 1927 2835 std::cout << " address " << std::hex << ad+word*4 << " data " << std::dec << r_tgt_buf[word] << std::endl; 1928 2836 data_t rdata = 0xAAAAAAAA; 1929 r_dcache .read(ad+word*4,&rdata);2837 r_dcache[num_cache]->read(ad+word*4,&rdata); 1930 2838 std::cout << "data written " << rdata << std::endl; 1931 2839 # endif … … 1940 2848 if (word==m_dcache_words) 1941 2849 { 1942 r_tgt_dcache_req = false;1943 r_tgt_dcache_rsp = true;1944 r_dcache_fsm = r_dcache_fsm_save;2850 r_tgt_dcache_req[num_cache] = false; 2851 r_tgt_dcache_rsp[num_cache] = true; 2852 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; 1945 2853 word = 0; 1946 2854 } … … 1950 2858 for(size_t i=0; i<m_dcache_words; i++){ 1951 2859 if(r_tgt_be[i]) { 1952 r_dcache .write( ad + i*4, buf[i]);2860 r_dcache[num_cache]->write( ad + i*4, buf[i]); 1953 2861 # ifdef COHERENCE_DEBUG 1954 2862 std::cout << " address " << std::hex << ad+i*4 << " data " << std::dec << buf[i] << std::endl; 1955 2863 data_t rdata = 0xAAAAAAAA; 1956 r_dcache .read(ad + i*4,&rdata);2864 r_dcache[num_cache]->read(ad + i*4,&rdata); 1957 2865 std::cout << "data written " << rdata << std::endl; 1958 2866 # endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1959 2867 } 1960 2868 } 1961 r_tgt_dcache_req = false;1962 r_tgt_dcache_rsp = true;1963 r_dcache_fsm = r_dcache_fsm_save;2869 r_tgt_dcache_req[num_cache] = false; 2870 r_tgt_dcache_rsp[num_cache] = true; 2871 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; 1964 2872 #endif 1965 2873 break; … … 1968 2876 case DCACHE_CC_INVAL: // invalidate a cache line 1969 2877 { 1970 addr_40 ad = r_tgt_ addr;1971 r_tgt_dcache_rsp = true;1972 r_dcache .inval(ad);1973 r_tgt_dcache_req = false;1974 r_dcache_fsm = r_dcache_fsm_save;2878 addr_40 ad = r_tgt_daddr; 2879 r_tgt_dcache_rsp[num_cache] = true; 2880 r_dcache [num_cache]->inval(ad); 2881 r_tgt_dcache_req[num_cache] = false; 2882 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; 1975 2883 break; 1976 2884 } … … 1979 2887 { 1980 2888 // external cache invalidate request 1981 if ( r_tgt_dcache_req )2889 if ( r_tgt_dcache_req[num_cache] ) 1982 2890 { 1983 r_dcache_fsm = DCACHE_CC_CHECK;1984 r_dcache_fsm_save = r_dcache_fsm;2891 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; 2892 r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache]; 1985 2893 break; 1986 2894 } 1987 2895 // cleanup 1988 if(not r_dcache_cleanup_req){ 1989 r_dcache_cleanup_req = true; 1990 r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift; 1991 r_dcache_fsm = DCACHE_IDLE; 2896 if(not r_dcache_cleanup_req[num_cache]){ 2897 r_dcache_cleanup_req [num_cache] = true; 2898 r_dcache_cleanup_line [num_cache] = r_dcache_addr_save[num_cache].read() >> m_dcache_words_shift; 2899 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2900 2901 // FIXME : too many access at the cache in this cycle 2902 m_cpt_dcache_dir_read += m_dcache_ways; 2903 r_dcache[num_cache]->inval((addr_40)r_dcache_addr_save[num_cache]); 1992 2904 } 1993 2905 break; … … 1999 2911 // The update() method must be called at each cycle to update the internal state. 2000 2912 // All pending write requests must be locked in case of SYNC 2001 bool wbuf_flush=(r_dcache_fsm == DCACHE_SYNC); 2913 2914 // bool have_sync=(r_dcache_fsm[num_cache] == DCACHE_SYNC); 2002 2915 #if (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==1) 2003 r_wbuf .update_multi_scan (wbuf_flush);2916 r_wbuf[num_cache]->update_multi_scan (have_sync); 2004 2917 #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==2) 2005 r_wbuf .update_round_robin_scan(wbuf_flush);2918 r_wbuf[num_cache]->update_round_robin_scan(have_sync); 2006 2919 #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==3) 2007 r_wbuf .update_one_scan (wbuf_flush);2920 r_wbuf[num_cache]->update_one_scan (have_sync); 2008 2921 #else 2009 r_wbuf.update (wbuf_flush); 2922 r_wbuf[num_cache]->update (have_sync); 2923 #endif 2924 2925 drsp [num_cache] = _drsp; 2926 if (_dreq.valid and _drsp.valid) 2927 { 2928 PRINTF(" * <CPU2CACHE> Transaction between cpu %d and Dcache %d (unlock)\n",r_dcache_lock [num_cache].read(),num_cache); 2929 2930 r_dcache_lock [num_cache] = m_nb_cpu; 2931 m_cpt_dcache_access [num_cache] ++; 2932 } 2933 2934 }// end for num_cache 2935 2936 /////////// execute one iss cycle ///////////////////////////////////////////// 2937 2938 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 2939 { 2940 // Test if the resquest is accepted 2941 typename iss_t::InstructionResponse _irsp = ISS_IRSP_INITIALIZER; 2942 typename iss_t::DataResponse _drsp = ISS_DRSP_INITIALIZER; 2943 2944 if (ireq_num_cache[num_cpu]<m_nb_icache) 2945 _irsp = irsp[ireq_num_cache[num_cpu]]; 2946 if (dreq_num_cache[num_cpu]<m_nb_dcache) 2947 _drsp = drsp[dreq_num_cache[num_cpu]]; 2948 2949 #if CC_XCACHE_WRAPPER_STOP_SIMULATION or CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2950 typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER; 2951 typename iss_t::DataRequest _dreq = ISS_DREQ_INITIALIZER; 2952 2953 if (ireq_num_cache[num_cpu]<m_nb_icache) 2954 _ireq = ireq[ireq_num_cache[num_cpu]]; 2955 if (dreq_num_cache[num_cpu]<m_nb_dcache) 2956 _dreq = dreq[dreq_num_cache[num_cpu]]; 2010 2957 #endif 2011 2958 2012 2959 #if CC_XCACHE_WRAPPER_DEBUG 2013 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 2014 std::cout << " * Data Response : " << drsp << std::endl; 2015 #endif 2016 2017 /////////// execute one iss cycle ///////////////////////////////////////////// 2018 { 2019 uint32_t it = 0; 2020 for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 2021 if(p_irq[i].read()) it |= (1<<i); 2022 m_iss.executeNCycles(1, irsp, drsp, it); 2023 } 2024 2025 if ( (ireq.valid and not irsp.valid) or 2026 (dreq.valid and not drsp.valid)) 2027 { 2028 m_cpt_frz_cycles++; 2960 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 2961 { 2962 2963 std::cout << " * CPU : " << num_cpu << std::endl 2964 << " * Instruction Cache : " << ireq_num_cache[num_cpu] << ", valid : " << (ireq_num_cache[num_cpu]<m_nb_icache) << std::endl 2965 << " * Instruction Request : " << _ireq << std::endl 2966 << " * Instruction Response : " << _irsp << std::endl 2967 << " * Data Cache : " << dreq_num_cache[num_cpu] << ", valid : " << (dreq_num_cache[num_cpu]<m_nb_dcache) << std::endl 2968 << " * Data Request : " << _dreq << std::endl 2969 << " * Data Response : " << _drsp << std::endl; 2970 } 2971 #endif 2972 2973 if ((_ireq.valid and not _irsp.valid) or 2974 (_dreq.valid and not _drsp.valid)) 2975 { 2976 m_cpt_frz_cycles [num_cpu]++; 2029 2977 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 2030 m_stop_simulation_nb_frz_cycles ++; 2978 m_stop_simulation_nb_frz_cycles [num_cpu]++; 2979 2980 if (m_stop_simulation and (m_stop_simulation_nb_frz_cycles [num_cpu]>= m_stop_simulation_nb_frz_cycles_max)) 2981 { 2982 std::cout << std::dec << "CC_XCACHE_WRAPPER \"" << name() << "\" (" << num_cpu << ") : cycle " << m_cpt_total_cycles << ", the cpu is frozen since " << m_stop_simulation_nb_frz_cycles [num_cpu]<< " cycles." << std::endl; 2983 ASSERT(false,"CPU : anormal activity"); // exit 2984 } 2985 } 2986 else 2987 { 2988 m_stop_simulation_nb_frz_cycles [num_cpu] = 0; // reinit counter 2989 #endif //CC_XCACHE_WRAPPER_STOP_SIMULATION 2990 } 2031 2991 2032 if (m_stop_simulation and (m_stop_simulation_nb_frz_cycles >= m_stop_simulation_nb_frz_cycles_max)) 2992 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2993 if (_ireq.valid and _irsp.valid) 2033 2994 { 2034 std::cout << std::dec << "CC_XCACHE_WRAPPER \"" << name() << "\" : cycle " << m_cpt_total_cycles << ", the cpu is frozen since " << m_stop_simulation_nb_frz_cycles << " cycles." << std::endl; 2035 ASSERT(false,"CPU : anormal activity"); // exit 2995 log_transaction_file_icache [num_cpu] 2996 << "[" << m_cpt_total_cycles << "]" 2997 << std::hex 2998 << " @ " << std::setw(8) << (uint32_t)_ireq.addr 2999 << " (" << std::setw(8) << (uint32_t)set_num_icache_only(_ireq.addr,ireq_num_cache[num_cpu]) 3000 << " - L " << std::setw(8) <<((uint32_t)set_num_icache_only(_ireq.addr,ireq_num_cache[num_cpu])&m_icache_yzmask) << ")" 3001 << " I " << std::setw(8) << (uint32_t)_irsp.instruction 3002 << " error " << (uint32_t)_irsp.error 3003 << std::dec 3004 << std::endl; 2036 3005 } 2037 } 2038 else 2039 { 2040 m_stop_simulation_nb_frz_cycles = 0; // reinit counter 2041 #endif //CC_XCACHE_WRAPPER_STOP_SIMULATION 2042 } 2043 2044 2045 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 2046 if (dreq.valid and drsp.valid) 2047 { 2048 log_dcache_transaction_file 2049 << "[" << m_cpt_total_cycles << "]" 2050 << std::hex 2051 << " @ " << std::setw(8) << (uint32_t)dreq.addr 2052 << " be " << std::setw(1) << (uint32_t)dreq.be 2053 << " W " << std::setw(8) << (uint32_t)dreq.wdata 2054 << " R " << std::setw(8) << (uint32_t)drsp.rdata 2055 << " error " << (uint32_t)drsp.error 2056 << std::dec 2057 << " " << type_str(dreq.type); 2058 2059 if ((dreq.type == iss_t::XTN_READ) or 2060 (dreq.type == iss_t::XTN_WRITE)) 2061 //log_dcache_transaction_file << xtn_str(dreq.addr>>2); 2062 switch (dreq.addr>>2) 2063 { 2064 case iss_t::XTN_DCACHE_INVAL : log_dcache_transaction_file << " INVAL"; break; 2065 case iss_t::XTN_SYNC : log_dcache_transaction_file << " SYNC"; break; 2066 default : log_dcache_transaction_file << " invalid"; break; 2067 } 2068 2069 log_dcache_transaction_file << std::endl; 2070 2071 // printf("[%d] @ %.8x be %.1x W %.8x R %.8x error %d - %s" 2072 // ,(uint32_t)m_cpt_total_cycles 2073 // ,(uint32_t)dreq.addr 2074 // ,(uint32_t)dreq.be 2075 // ,(uint32_t)dreq.wdata 2076 // ,(uint32_t)drsp.rdata 2077 // ,(uint32_t)drsp.error 2078 // ,type_str(dreq.type)); 2079 // if ((dreq.type == iss_t::XTN_READ) or 2080 // (dreq.type == iss_t::XTN_WRITE)) 2081 // // printf(" %s",xtn_str(dreq.addr>>2)); 2082 // switch (dreq.addr>>2) 2083 // { 2084 // case iss_t::XTN_DCACHE_INVAL : printf(" INVAL"); break; 2085 // case iss_t::XTN_SYNC : printf(" SYNC"); break; 2086 // default : printf(" invalid"); break; 2087 // } 2088 // printf("\n"); 2089 } 2090 #endif //CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 3006 3007 if (_dreq.valid and _drsp.valid) 3008 { 3009 log_transaction_file_dcache [num_cpu] 3010 << "[" << m_cpt_total_cycles << "]" 3011 << std::hex 3012 << " @ " << std::setw(8) << (uint32_t)_dreq.addr 3013 << " (" << std::setw(8) << (uint32_t)set_num_dcache_only(_dreq.addr,dreq_num_cache[num_cpu]) 3014 << " - L " << std::setw(8) <<((uint32_t)set_num_dcache_only(_dreq.addr,dreq_num_cache[num_cpu])&m_dcache_yzmask) << ")" 3015 << " be " << std::setw(1) << (uint32_t)_dreq.be 3016 << " W " << std::setw(8) << (uint32_t)_dreq.wdata 3017 << " R " << std::setw(8) << (uint32_t)_drsp.rdata 3018 << " error " << (uint32_t)_drsp.error 3019 << std::dec 3020 << " " << type_str(_dreq.type); 3021 3022 if ((_dreq.type == iss_t::XTN_READ) or 3023 (_dreq.type == iss_t::XTN_WRITE)) 3024 //log_transaction_file_dcache [num_cpu] << xtn_str(_dreq.addr>>2); 3025 switch (_dreq.addr>>2) 3026 { 3027 case iss_t::XTN_DCACHE_INVAL : log_transaction_file_dcache [num_cpu]<< " INVAL"; break; 3028 case iss_t::XTN_SYNC : log_transaction_file_dcache [num_cpu]<< " SYNC"; break; 3029 default : log_transaction_file_dcache [num_cpu]<< " invalid"; break; 3030 } 3031 3032 log_transaction_file_dcache [num_cpu]<< std::endl; 3033 } 3034 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3035 3036 { 3037 uint32_t it = 0; 3038 for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 3039 if(p_irq[num_cpu][i].read()) it |= (1<<i); 3040 3041 m_iss[num_cpu]->executeNCycles(1, _irsp, _drsp, it); 3042 } 3043 }//end num_cpu 2091 3044 2092 3045 //////////////////////////////////////////////////////////////////////////// … … 2113 3066 2114 3067 case CLEANUP_IDLE: 2115 { 2116 if ( p_vci_ini_c.cmdack ) 2117 { 2118 if (r_dcache_cleanup_req) r_cleanup_fsm = CLEANUP_DCACHE; 2119 else if (r_icache_cleanup_req) r_cleanup_fsm = CLEANUP_ICACHE; 3068 { 3069 uint32_t num_cache = 0; 3070 bool cleanup_dcache_req = false; 3071 bool cleanup_icache_req = false; 3072 3073 // dcache is prior 3074 for (uint32_t i=0; i<m_nb_dcache; ++i) 3075 { 3076 PRINTF(" * <CLEANUP> dcache_cleanup_req : [%d] %d\n",i,(int)r_dcache_cleanup_req[i]); 3077 cleanup_dcache_req |= r_dcache_cleanup_req[i]; 3078 if (cleanup_dcache_req) 3079 { 3080 PRINTF(" * <CLEANUP> ... find\n"); 3081 num_cache=i; 3082 break; 3083 } 3084 } 3085 3086 if (not cleanup_dcache_req) 3087 for (uint32_t i=0; i<m_nb_icache; ++i) 3088 { 3089 PRINTF(" * <CLEANUP> icache_cleanup_req : [%d] %d\n",i,(int)r_icache_cleanup_req[i]); 3090 3091 cleanup_icache_req |= r_icache_cleanup_req[i]; 3092 if (cleanup_icache_req) 3093 { 3094 PRINTF(" * <CLEANUP> ... find\n"); 3095 num_cache=i; 3096 break; 3097 } 3098 } 3099 3100 PRINTF(" * <CLEANUP> cleanup_icache_req : %d\n",cleanup_icache_req); 3101 PRINTF(" * <CLEANUP> cleanup_dcache_req : %d\n",cleanup_dcache_req); 3102 PRINTF(" * <CLEANUP> num_cache : %d\n",num_cache); 3103 3104 if (cleanup_icache_req or cleanup_dcache_req) 3105 { 3106 r_cleanup_fsm = CLEANUP_REQ; 3107 r_cleanup_icache = cleanup_icache_req; 3108 r_cleanup_num_cache = num_cache; 3109 3110 PRINTF(" * <CLEANUP> address : %llx\n",((cleanup_icache_req)?((uint64_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((uint64_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache)))); 3111 3112 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3113 log_transaction_file_cleanup 3114 << "[" << m_cpt_total_cycles << "] " 3115 << ((cleanup_icache_req)?("icache "):("dcache ")) 3116 << num_cache << " : " 3117 << std::hex 3118 << " L " << std::setw(10) << ((cleanup_icache_req)?((uint64_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((uint64_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache))) 3119 // << " (" << std::setw(10) << addr << ")" 3120 << std::dec 3121 << std::endl; 3122 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3123 2120 3124 } 2121 3125 break; 2122 3126 } 2123 case CLEANUP_DCACHE: 3127 case CLEANUP_REQ: 3128 { 3129 if ( p_vci_ini_c.cmdack ) 3130 { 3131 if (r_cleanup_icache) 3132 r_cleanup_fsm = CLEANUP_RSP_ICACHE; 3133 else 3134 r_cleanup_fsm = CLEANUP_RSP_DCACHE; 3135 } 3136 break; 3137 } 3138 case CLEANUP_RSP_DCACHE: 2124 3139 { 2125 3140 if ( p_vci_ini_c.rspval ) 2126 3141 { 2127 3142 PRINTF(" * <CLEANUP> rerror : %d (%d)\n",(uint32_t)p_vci_ini_c.rerror.read(),0x2 & ( (1 << vci_param::E) - 1)); 3143 PRINTF(" * <CLEANUP> rpktid : %d, r_cleanup_num_cache : %d\n",(uint32_t)p_vci_ini_c.rpktid.read(), (uint32_t)r_cleanup_num_cache); 2128 3144 2129 3145 ASSERT(p_vci_ini_c.reop and (p_vci_ini_c.rtrdid.read() == TYPE_DATA_CLEANUP), 2130 3146 "illegal response packet received for a cleanup transaction"); 2131 3147 ASSERT(p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL, 2132 3148 "error signaled in a cleanup response" ); 2133 3149 ASSERT(p_vci_ini_c.rpktid.read() == (sc_dt::sc_uint<vci_param::P>)r_cleanup_num_cache, 3150 "invalid pktid in a cleanup response"); 3151 2134 3152 r_cleanup_fsm = CLEANUP_IDLE; 2135 r_dcache_cleanup_req = false;2136 // m_cpt_cc_cleanup_data++; TODO3153 r_dcache_cleanup_req[r_cleanup_num_cache] = false; 3154 // m_cpt_cc_cleanup_data++; 2137 3155 } 2138 3156 break; 2139 3157 } 2140 case CLEANUP_ ICACHE:3158 case CLEANUP_RSP_ICACHE: 2141 3159 { 2142 3160 if ( p_vci_ini_c.rspval ) … … 2150 3168 2151 3169 r_cleanup_fsm = CLEANUP_IDLE; 2152 r_icache_cleanup_req = false;2153 // m_cpt_cc_cleanup_ins++; TODO3170 r_icache_cleanup_req[r_cleanup_num_cache] = false; 3171 // m_cpt_cc_cleanup_ins++; 2154 3172 } 2155 3173 break; … … 2195 3213 // if (r_vci_rsp_fsm != RSP_IDLE) break; 2196 3214 2197 size_t min; 2198 size_t max; 2199 3215 size_t wbuf_min = 0; 3216 size_t wbuf_max = 0; 3217 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3218 addr_40 wbuf_addr = 0; 3219 size_t wbuf_index = 0; 3220 #endif 2200 3221 r_vci_cmd_cpt = 0; 2201 3222 … … 2204 3225 // multi_write_buffer access is conditionnal with dcache_miss_req and icache_miss_req 2205 3226 2206 #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) 2207 // 1) two access authorized 2208 bool dcache_miss_req = r_dcache_miss_req; 2209 bool icache_miss_req = r_icache_miss_req; 2210 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) 2211 // 2) one access with static priority (dcache prior) 2212 bool dcache_miss_req = r_dcache_miss_req; // dcache prior 2213 bool icache_miss_req = not dcache_miss_req and r_icache_miss_req; 3227 bool dcache_miss_req = false; 3228 bool icache_miss_req = false; 3229 uint32_t dcache_miss_num_cache = 0; 3230 uint32_t icache_miss_num_cache = 0; 3231 addr_40 addr = 0; 3232 3233 { 3234 for (; dcache_miss_num_cache<m_nb_dcache; ++dcache_miss_num_cache) 3235 { 3236 dcache_miss_req = r_dcache_miss_req[dcache_miss_num_cache]; 3237 if (dcache_miss_req) 3238 break; 3239 } 3240 for (; icache_miss_num_cache<m_nb_icache; ++icache_miss_num_cache) 3241 { 3242 icache_miss_req = r_icache_miss_req[icache_miss_num_cache]; 3243 if (icache_miss_req) 3244 break; 3245 } 3246 3247 PRINTF(" * <CMD> icache_miss_req (before) : %d\n",icache_miss_req); 3248 PRINTF(" * <CMD> dcache_miss_req (before) : %d\n",dcache_miss_req); 3249 3250 // #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) 3251 // // 1) two access authorized 3252 // dcache_miss_req = r_dcache_miss_req[cache_miss_num_cache]; 3253 // icache_miss_req = r_icache_miss_req[cache_miss_num_cache]; 3254 // #el 3255 #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) 3256 // 2) one access with static priority (dcache prior) 3257 icache_miss_req &= not dcache_miss_req; 2214 3258 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==3) 2215 // 3) one access with static priority (icache prior) 2216 bool icache_miss_req = r_icache_miss_req; 2217 bool dcache_miss_req = not icache_miss_req and r_dcache_miss_req; // dcache prior 3259 // 3) one access with static priority (icache prior) 3260 dcache_miss_req &= not icache_miss_req; 2218 3261 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) 2219 // 4) one access with round robin priority2220 bool dcache_miss_req = ((r_dcache_miss_req and not r_icache_miss_req) or // only dcache2221 (r_dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior2222 bool icache_miss_req = not dcache_miss_req and r_icache_miss_req;3262 // 4) one access with round robin priority 3263 dcache_miss_req = ((dcache_miss_req and not icache_miss_req) or // only dcache 3264 (dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior 3265 icache_miss_req &= not dcache_miss_req; 2223 3266 #else 2224 3267 #error "Invalid value to CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY" 2225 3268 #endif 3269 3270 PRINTF(" * <CMD> icache_miss_req (after ) : %d\n",icache_miss_req); 3271 PRINTF(" * <CMD> dcache_miss_req (after ) : %d\n",dcache_miss_req); 3272 3273 PRINTF(" * <CMD> icache_miss_num_cache : %d\n",icache_miss_num_cache); 3274 PRINTF(" * <CMD> dcache_miss_num_cache : %d\n",dcache_miss_num_cache); 3275 3276 if (icache_miss_req or dcache_miss_req) 3277 { 3278 addr = (icache_miss_req)?r_icache_addr_save[icache_miss_num_cache].read():r_dcache_addr_save[dcache_miss_num_cache].read(); 3279 3280 PRINTF(" * <CMD> addr : %llx\n",(uint64_t)addr); 3281 3282 if (icache_miss_req) 3283 { 3284 // FIXME : 3285 // si wbuf contient des addresses partionné, set_num_icache puis get_num_dcache 3286 // dcache_miss_num_cache = icache_miss_num_cache; 3287 set_num_icache(addr,icache_miss_num_cache); 3288 // get_num_dcache(addr,dcache_miss_num_cache); 3289 } 3290 else 3291 set_num_dcache(addr,dcache_miss_num_cache); 3292 3293 PRINTF(" * <CMD> addr : %llx\n",(uint64_t)addr); 3294 } 3295 } 3296 3297 uint32_t dcache_unc_num_cache = 0; 3298 for (; dcache_unc_num_cache<m_nb_dcache; ++dcache_unc_num_cache) 3299 if (r_dcache_unc_req[dcache_unc_num_cache]) 3300 break; 3301 uint32_t icache_unc_num_cache = 0; 3302 for (; icache_unc_num_cache<m_nb_icache; ++icache_unc_num_cache) 3303 if (r_icache_unc_req[icache_unc_num_cache]) 3304 break; 3305 uint32_t dcache_sc_num_cache = 0; 3306 for (; dcache_sc_num_cache<m_nb_dcache; ++dcache_sc_num_cache) 3307 if (r_dcache_sc_req[dcache_sc_num_cache]) 3308 break; 3309 uint32_t dcache_write_num_cache = 0; 3310 for (; dcache_write_num_cache<m_nb_dcache; ++dcache_write_num_cache) 3311 { 3312 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3313 if ( r_wbuf[dcache_write_num_cache]->debug_rok(&wbuf_min, &wbuf_max, &wbuf_addr, &wbuf_index)) 3314 break; 3315 #else 3316 if ( r_wbuf[dcache_write_num_cache]->rok(&wbuf_min, &wbuf_max)) 3317 break; 3318 #endif 3319 } 3320 2226 3321 // 1 - Data Read 2227 if (dcache_miss_req and r_wbuf .miss(r_dcache_addr_save))3322 if (dcache_miss_req and r_wbuf[dcache_miss_num_cache]->miss(addr)) 2228 3323 { 2229 r_vci_cmd_fsm = CMD_DATA_MISS; 2230 r_dcache_miss_req = false; 3324 r_vci_cmd_fsm = CMD_DATA_MISS; 3325 r_vci_cmd_num_cache = dcache_miss_num_cache; 3326 r_dcache_miss_req[dcache_miss_num_cache] = false; 2231 3327 m_cpt_dmiss_transaction++; 3328 3329 3330 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3331 { 3332 log_transaction_file_cmd 3333 << "[" << m_cpt_total_cycles << "] " 3334 << "CMD DATA MISS " 3335 << "(" << dcache_miss_num_cache << ") " 3336 << std::hex 3337 << " @ " << std::setw(10) << (uint64_t)addr 3338 << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")" 3339 << std::dec 3340 << std::endl; 3341 } 3342 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3343 2232 3344 } 2233 3345 2234 3346 // 2 - Data Read Uncachable 2235 else if ( r_dcache_unc_req )3347 else if (dcache_unc_num_cache < m_nb_dcache) // have r_dcache_unc_req 2236 3348 { 2237 r_vci_cmd_fsm = CMD_DATA_UNC; 2238 r_dcache_unc_req = false; 2239 // m_cpt_data_unc_transaction++; 3349 r_vci_cmd_fsm = CMD_DATA_UNC; 3350 r_vci_cmd_num_cache = dcache_unc_num_cache; 3351 r_dcache_unc_req[dcache_unc_num_cache] = false; 3352 // m_cpt_data_unc_transaction++; 3353 3354 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3355 { 3356 addr_40 addr = (addr_40) r_dcache_addr_save[dcache_unc_num_cache].read() & ~0x3; 3357 set_num_dcache(addr,dcache_unc_num_cache); 3358 3359 log_transaction_file_cmd 3360 << "[" << m_cpt_total_cycles << "] " 3361 << "CMD DATA UNC " 3362 << "(" << dcache_unc_num_cache << ") " 3363 << std::hex 3364 << " @ " << std::setw(10) << (uint64_t)addr 3365 << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")" 3366 << std::dec 3367 << std::endl; 3368 } 3369 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2240 3370 } 2241 3371 2242 3372 // 3 - Instruction Miss 2243 else if (icache_miss_req and r_wbuf.miss(r_icache_addr_save)) 3373 else if (icache_miss_req and r_wbuf[icache_miss_num_cache]->miss(addr)) 3374 //else if (icache_miss_req and r_wbuf[dcache_miss_num_cache]->miss(addr)) 2244 3375 { 2245 r_vci_cmd_fsm = CMD_INS_MISS; 2246 r_icache_miss_req = false; 3376 r_vci_cmd_fsm = CMD_INS_MISS; 3377 r_vci_cmd_num_cache = icache_miss_num_cache; 3378 r_icache_miss_req[icache_miss_num_cache] = false; 2247 3379 m_cpt_imiss_transaction++; 3380 3381 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3382 { 3383 log_transaction_file_cmd 3384 << "[" << m_cpt_total_cycles << "] " 3385 << "CMD INS MISS " 3386 << "(" << icache_miss_num_cache << ") " 3387 << std::hex 3388 << " @ " << std::setw(10) << (uint64_t)addr 3389 << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_icache_yzmask) << ")" 3390 << std::dec 3391 << std::endl; 3392 } 3393 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2248 3394 } 2249 3395 2250 3396 // 4 - Instruction Uncachable 2251 else if ( r_icache_unc_req )3397 else if (icache_unc_num_cache < m_nb_icache) // have r_icache_unc_req 2252 3398 { 2253 r_vci_cmd_fsm = CMD_INS_UNC; 2254 r_icache_unc_req = false; 3399 r_vci_cmd_fsm = CMD_INS_UNC; 3400 r_vci_cmd_num_cache = icache_unc_num_cache; 3401 r_icache_unc_req[icache_unc_num_cache] = false; 2255 3402 // m_cpt_ins_unc_transaction++; 3403 3404 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3405 { 3406 addr_40 addr = (addr_40) r_icache_addr_save[icache_unc_num_cache].read() & ~0x3; 3407 set_num_dcache(addr,icache_unc_num_cache); 3408 3409 log_transaction_file_cmd 3410 << "[" << m_cpt_total_cycles << "] " 3411 << "CMD INS UNC " 3412 << "(" << icache_unc_num_cache << ") " 3413 << std::hex 3414 << " @ " << std::setw(10) << (uint64_t)addr 3415 << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_icache_yzmask) << ")" 3416 << std::dec 3417 << std::endl; 3418 } 3419 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2256 3420 } 2257 3421 2258 3422 // 5 - Data Write 2259 else if ( r_wbuf.rok(&min, &max) )3423 else if (dcache_write_num_cache < m_nb_dcache) // have r_wbuf.rok(&wbuf_min, &wbuf_max) 2260 3424 { 2261 r_vci_cmd_fsm = CMD_DATA_WRITE; 2262 r_vci_cmd_cpt = min; 2263 r_vci_cmd_min = min; 2264 r_vci_cmd_max = max; 3425 r_vci_cmd_num_cache = dcache_write_num_cache; 3426 r_vci_cmd_fsm = CMD_DATA_WRITE; 3427 r_vci_cmd_cpt = wbuf_min; 3428 r_vci_cmd_min = wbuf_min; 3429 r_vci_cmd_max = wbuf_max; 2265 3430 m_cpt_data_write_transaction++; 2266 m_length_write_transaction += (max-min+1); 3431 m_length_write_transaction += (wbuf_max-wbuf_min+1); 3432 3433 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3434 { 3435 addr_40 addr = (addr_40) wbuf_addr&~0x3; 3436 3437 log_transaction_file_cmd 3438 << "[" << m_cpt_total_cycles << "] " 3439 << "CMD DATA WRITE " 3440 << "(" << dcache_write_num_cache << ") " 3441 << std::hex 3442 << " @ " << std::setw(10) << (uint64_t)addr 3443 << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")" 3444 << " [" << wbuf_min << ":" << wbuf_max << "]" 3445 << " {" << wbuf_index << "}" 3446 << std::dec 3447 << std::endl; 3448 } 3449 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2267 3450 } 2268 3451 2269 3452 // 6 - Data Store Conditionnal 2270 else if ( r_dcache_sc_req )3453 else if (dcache_sc_num_cache < m_nb_dcache) // have r_dcache_sc_req 2271 3454 { 2272 r_vci_cmd_fsm = CMD_DATA_SC; 2273 r_vci_cmd_max = 1; 3455 r_vci_cmd_fsm = CMD_DATA_SC; 3456 r_vci_cmd_num_cache = dcache_sc_num_cache; 3457 r_vci_cmd_max = 1; 2274 3458 m_cpt_unc_transaction++; 2275 r_dcache_sc_req = false; 3459 r_dcache_sc_req[dcache_sc_num_cache] = false; 3460 3461 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3462 { 3463 addr_40 addr = (addr_40) r_dcache_addr_save[dcache_sc_num_cache].read() & ~0x3; 3464 set_num_dcache(addr,dcache_sc_num_cache); 3465 3466 log_transaction_file_cmd 3467 << "[" << m_cpt_total_cycles << "] " 3468 << "CMD DATA SC " 3469 << "(" << dcache_sc_num_cache << ") " 3470 << std::hex 3471 << " @ " << std::setw(10) << (uint64_t)addr 3472 << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")" 3473 << std::dec 3474 << std::endl; 3475 } 3476 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2276 3477 } 2277 3478 … … 2283 3484 if (r_vci_cmd_cpt == r_vci_cmd_max) { 2284 3485 r_vci_cmd_fsm = CMD_IDLE ; 2285 r_wbuf .sent() ;3486 r_wbuf[r_vci_cmd_num_cache]->sent() ; 2286 3487 } 2287 3488 } … … 2339 3540 if( p_vci_ini_rw.rspval.read() ) 2340 3541 { 2341 PRINTF(" * <RSP> have rsp - trdid : %x\n",(uint32_t)p_vci_ini_rw.rtrdid.read()); 3542 PRINTF(" * <RSP> have rsp - trdid : %x - num_cache : %d\n",(uint32_t)p_vci_ini_rw.rtrdid.read(),(uint32_t)p_vci_ini_rw.rpktid.read()); 3543 3544 ASSERT(p_vci_ini_rw.rpktid.read() <= (1<<vci_param::P), 3545 "invalid pktid in a cleanup response"); 2342 3546 2343 3547 r_vci_rsp_cpt = 0; 2344 3548 2345 3549 if ((p_vci_ini_rw.rtrdid.read()>>(vci_param::T-1)) != 0 ) 3550 { 2346 3551 r_vci_rsp_fsm = RSP_DATA_WRITE; 3552 3553 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3554 { 3555 log_transaction_file_cmd 3556 << "[" << m_cpt_total_cycles << "] " 3557 << "RSP DATA WRITE " 3558 << "(" << p_vci_ini_rw.rpktid.read() << ") " 3559 << "{" << (p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1))) << "}" 3560 << std::endl; 3561 } 3562 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3563 } 2347 3564 else 2348 3565 { 2349 3566 switch (p_vci_ini_rw.rtrdid.read()) 2350 3567 { 2351 case TYPE_INS_MISS : r_vci_rsp_fsm = RSP_INS_MISS; break; 2352 case TYPE_INS_UNC : r_vci_rsp_fsm = RSP_INS_UNC; break; 2353 case TYPE_DATA_MISS : r_vci_rsp_fsm = RSP_DATA_MISS; break; 2354 case TYPE_DATA_UNC : r_vci_rsp_fsm = RSP_DATA_UNC; break; 2355 case TYPE_DATA_SC : r_vci_rsp_fsm = RSP_DATA_SC; break; 3568 case TYPE_INS_MISS : 3569 { 3570 r_vci_rsp_fsm = RSP_INS_MISS; 3571 3572 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3573 { 3574 log_transaction_file_cmd 3575 << "[" << m_cpt_total_cycles << "] " 3576 << "RSP INS MISS " 3577 << "(" << p_vci_ini_rw.rpktid.read() << ") " 3578 << std::endl; 3579 } 3580 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3581 3582 break; 3583 } 3584 case TYPE_INS_UNC : 3585 { 3586 r_vci_rsp_fsm = RSP_INS_UNC; 3587 3588 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3589 { 3590 log_transaction_file_cmd 3591 << "[" << m_cpt_total_cycles << "] " 3592 << "RSP INS UNC " 3593 << "(" << p_vci_ini_rw.rpktid.read() << ") " 3594 << std::endl; 3595 } 3596 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3597 3598 break; 3599 } 3600 case TYPE_DATA_MISS : 3601 { 3602 r_vci_rsp_fsm = RSP_DATA_MISS; 3603 3604 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3605 { 3606 log_transaction_file_cmd 3607 << "[" << m_cpt_total_cycles << "] " 3608 << "RSP DATA MISS " 3609 << "(" << p_vci_ini_rw.rpktid.read() << ") " 3610 << std::endl; 3611 } 3612 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3613 3614 break; 3615 } 3616 case TYPE_DATA_UNC : 3617 { 3618 r_vci_rsp_fsm = RSP_DATA_UNC; 3619 3620 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3621 { 3622 log_transaction_file_cmd 3623 << "[" << m_cpt_total_cycles << "] " 3624 << "RSP DATA UNC " 3625 << "(" << p_vci_ini_rw.rpktid.read() << ") " 3626 << std::endl; 3627 } 3628 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3629 3630 break; 3631 } 3632 case TYPE_DATA_SC : 3633 { 3634 r_vci_rsp_fsm = RSP_DATA_SC; 3635 3636 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3637 { 3638 log_transaction_file_cmd 3639 << "[" << m_cpt_total_cycles << "] " 3640 << "RSP DATA SC " 3641 << "(" << p_vci_ini_rw.rpktid.read() << ") " 3642 << std::endl; 3643 } 3644 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3645 3646 break; 3647 } 2356 3648 default : 2357 3649 { … … 2360 3652 } 2361 3653 } 3654 3655 r_vci_rsp_num_cache = p_vci_ini_rw.rpktid.read(); 2362 3656 } 2363 3657 break; … … 2366 3660 2367 3661 m_cost_imiss_transaction++; 2368 PRINTF(" * <RSP> rspval/ack : %d - %d\n",(uint32_t)p_vci_ini_rw.rspval.read(), (uint32_t) r_vci_rsp_ack);2369 2370 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)3662 PRINTF(" * <RSP> rspval/ack : %d - %d\n",(uint32_t)p_vci_ini_rw.rspval.read(), (uint32_t)s_vci_rsp_ack); 3663 3664 if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) 2371 3665 { 2372 3666 PRINTF(" * <RSP> have rsp - r_vci_rsp_cpt : %d/%d\n",(uint32_t)r_vci_rsp_cpt.read(),(uint32_t)m_icache_words); … … 2376 3670 "The VCI response packet for instruction miss is too long" ); 2377 3671 r_vci_rsp_cpt = r_vci_rsp_cpt + 1; 2378 CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_ cpt,(data_t)p_vci_ini_rw.rdata.read());3672 CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_num_cache,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read()); 2379 3673 if ( p_vci_ini_rw.reop.read() ) 2380 3674 { … … 2383 3677 ASSERT( ((r_vci_rsp_cpt == m_icache_words - 1) or 2384 3678 p_vci_ini_rw.rerror.read() or 2385 (r_vci_rsp_ins_error .read()&0x1)),3679 (r_vci_rsp_ins_error[r_vci_rsp_num_cache].read()&0x1)), 2386 3680 "The VCI response packet for instruction miss is too short"); 2387 3681 r_vci_rsp_cpt = 0; … … 2389 3683 2390 3684 } 2391 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;3685 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error[r_vci_rsp_num_cache] = true; 2392 3686 } 2393 3687 break; … … 2396 3690 2397 3691 m_cost_imiss_transaction++; 2398 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)3692 if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) 2399 3693 { 2400 3694 ASSERT(p_vci_ini_rw.reop.read(), 2401 3695 "illegal VCI response packet for uncached instruction"); 2402 3696 2403 CACHE_MISS_BUF_RSP_PUSH(i, 0,(data_t)p_vci_ini_rw.rdata.read());3697 CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read()); 2404 3698 2405 3699 r_vci_rsp_fsm = RSP_IDLE; 2406 3700 2407 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;3701 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error[r_vci_rsp_num_cache] = true; 2408 3702 } 2409 3703 break; … … 2412 3706 2413 3707 m_cost_dmiss_transaction++; 2414 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)3708 if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) 2415 3709 { 2416 3710 PRINTF(" * <RSP> have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read()); … … 2420 3714 r_vci_rsp_cpt = r_vci_rsp_cpt + 1; 2421 3715 2422 CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_ cpt,(data_t)p_vci_ini_rw.rdata.read());3716 CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read()); 2423 3717 2424 3718 if ( p_vci_ini_rw.reop.read() ) { 2425 3719 ASSERT( ((r_vci_rsp_cpt == m_dcache_words - 1) 2426 3720 or (p_vci_ini_rw.rerror.read()&0x1) 2427 or r_vci_rsp_data_error .read()),3721 or r_vci_rsp_data_error[r_vci_rsp_num_cache].read()), 2428 3722 "illegal VCI response packet for data read miss"); 2429 3723 r_vci_rsp_cpt = 0; 2430 3724 r_vci_rsp_fsm = RSP_IDLE; 2431 3725 } 2432 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;3726 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true; 2433 3727 } 2434 3728 break; 2435 3729 2436 3730 case RSP_DATA_WRITE: 2437 2438 3731 m_cost_write_transaction++; 2439 3732 if (p_vci_ini_rw.rspval.read()) … … 2444 3737 "A VCI response packet must contain one flit for a write transaction"); 2445 3738 r_vci_rsp_fsm = RSP_IDLE; 2446 bool cached = r_wbuf .completed(p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1)));3739 bool cached = r_wbuf[r_vci_rsp_num_cache]->completed(p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1))); 2447 3740 2448 3741 PRINTF(" * <RSP> cached : %d\n",cached); 2449 3742 2450 3743 if (not cached) 2451 r_dcache_previous_unc = false; 2452 2453 if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) m_iss.setWriteBerr(); 3744 r_dcache_previous_unc[r_vci_rsp_num_cache] = false; 3745 3746 // FIXME : r_vci_rsp_num_cache != num_cpu ! -> pktid 3747 if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) m_iss[r_vci_rsp_num_cache]->setWriteBerr(); 2454 3748 } 2455 3749 break; … … 2457 3751 case RSP_DATA_UNC: 2458 3752 m_cost_unc_transaction++; 2459 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)3753 if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) 2460 3754 { 2461 3755 ASSERT(p_vci_ini_rw.reop.read(), 2462 3756 "illegal VCI response packet for data read uncached"); 2463 3757 2464 CACHE_MISS_BUF_RSP_PUSH(d, 0,(data_t)p_vci_ini_rw.rdata.read());3758 CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read()); 2465 3759 2466 3760 r_vci_rsp_fsm = RSP_IDLE; 2467 r_dcache_previous_unc = false;2468 2469 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;3761 r_dcache_previous_unc[r_vci_rsp_num_cache] = false; 3762 3763 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true; 2470 3764 } 2471 3765 break; … … 2473 3767 case RSP_DATA_SC: 2474 3768 m_cost_unc_transaction++; 2475 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)3769 if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) 2476 3770 { 2477 3771 ASSERT(p_vci_ini_rw.reop.read(), 2478 3772 "illegal VCI response packet for data SC"); 2479 3773 2480 CACHE_MISS_BUF_RSP_PUSH(d, 0,(data_t)p_vci_ini_rw.rdata.read());3774 CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read()); 2481 3775 2482 3776 r_vci_rsp_fsm = RSP_IDLE; 2483 r_dcache_previous_unc = false;2484 2485 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;3777 r_dcache_previous_unc[r_vci_rsp_num_cache] = false; 3778 3779 if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true; 2486 3780 } 2487 3781 break; … … 2489 3783 } // end switch r_vci_rsp_fsm 2490 3784 2491 3785 } // end transition() 2492 3786 2493 3787 ////////////////////////////////////////////////////////////////////////////////// … … 2495 3789 ////////////////////////////////////////////////////////////////////////////////// 2496 3790 { 3791 PRINTF("--------------------------------------------\n"); 3792 PRINTF(" * CC_XCACHE_WRAPPER \"%s\" genMoore - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); 2497 3793 2498 3794 // VCI initiator response 2499 3795 switch ( r_cleanup_fsm.read() ) { 2500 2501 3796 case CLEANUP_IDLE: 2502 3797 p_vci_ini_c.rspack = false; 2503 p_vci_ini_c.cmdval = r_icache_cleanup_req || r_dcache_cleanup_req; 2504 if ( r_dcache_cleanup_req ) 2505 { 2506 p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words << 2); 2507 p_vci_ini_c.trdid = TYPE_DATA_CLEANUP; 3798 p_vci_ini_c.cmdval = false; 3799 p_vci_ini_c.address = 0; 3800 p_vci_ini_c.wdata = 0; 3801 p_vci_ini_c.be = 0; 3802 p_vci_ini_c.plen = 0; 3803 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 3804 p_vci_ini_c.trdid = 0; 3805 p_vci_ini_c.pktid = 0; 3806 p_vci_ini_c.srcid = 0; 3807 p_vci_ini_c.cons = false; 3808 p_vci_ini_c.wrap = false; 3809 p_vci_ini_c.contig = false; 3810 p_vci_ini_c.clen = 0; 3811 p_vci_ini_c.cfixed = false; 3812 p_vci_ini_c.eop = false; 3813 break; 3814 3815 case CLEANUP_REQ: 3816 { 3817 addr_40 addr; 3818 if (r_cleanup_icache) 3819 { 3820 addr = r_icache_cleanup_line[r_cleanup_num_cache].read()<<m_icache_words_shift; 3821 set_num_icache(addr,r_cleanup_num_cache); 3822 3823 PRINTF(" * <CLEANUP> icache : %llx\n",(uint64_t)addr); 2508 3824 } 2509 3825 else 2510 3826 { 2511 p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words << 2); 2512 p_vci_ini_c.trdid = TYPE_INS_CLEANUP; 2513 } 2514 p_vci_ini_c.wdata = 0; 2515 p_vci_ini_c.be = 0xF; 2516 p_vci_ini_c.plen = 4; 2517 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 2518 p_vci_ini_c.pktid = 0; 2519 p_vci_ini_c.srcid = m_srcid_c; 2520 p_vci_ini_c.cons = false; 2521 p_vci_ini_c.wrap = false; 2522 p_vci_ini_c.contig = false; 2523 p_vci_ini_c.clen = 0; 2524 p_vci_ini_c.cfixed = false; 2525 p_vci_ini_c.eop = true; 3827 addr = r_dcache_cleanup_line[r_cleanup_num_cache].read()<<m_dcache_words_shift; 3828 set_num_dcache(addr,r_cleanup_num_cache); 3829 3830 PRINTF(" * <CLEANUP> dcache : %llx\n",(uint64_t)addr); 3831 } 3832 3833 p_vci_ini_c.rspack = false; 3834 p_vci_ini_c.cmdval = true; 3835 p_vci_ini_c.address = addr; 3836 p_vci_ini_c.wdata = 0; 3837 p_vci_ini_c.be = 0xF; 3838 p_vci_ini_c.plen = 4; 3839 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 3840 p_vci_ini_c.trdid = (r_cleanup_icache)?TYPE_INS_CLEANUP:TYPE_DATA_CLEANUP; 3841 p_vci_ini_c.pktid = (sc_dt::sc_uint<vci_param::P>)r_cleanup_num_cache; 3842 p_vci_ini_c.srcid = m_srcid_c; 3843 p_vci_ini_c.cons = false; 3844 p_vci_ini_c.wrap = false; 3845 p_vci_ini_c.contig = false; 3846 p_vci_ini_c.clen = 0; 3847 p_vci_ini_c.cfixed = false; 3848 p_vci_ini_c.eop = true; 3849 2526 3850 break; 2527 2528 case CLEANUP_DCACHE: 3851 } 3852 3853 case CLEANUP_RSP_DCACHE: 2529 3854 p_vci_ini_c.rspack = true; 2530 3855 p_vci_ini_c.cmdval = false; … … 2545 3870 break; 2546 3871 2547 case CLEANUP_ ICACHE:3872 case CLEANUP_RSP_ICACHE: 2548 3873 p_vci_ini_c.rspack = true; 2549 3874 p_vci_ini_c.cmdval = false; … … 2568 3893 2569 3894 switch (r_vci_cmd_fsm.read() ) { 2570 2571 3895 case CMD_IDLE: 3896 { 2572 3897 p_vci_ini_rw.cmdval = false; 2573 3898 p_vci_ini_rw.address = 0; … … 2587 3912 2588 3913 break; 2589 3914 } 2590 3915 case CMD_DATA_UNC: 3916 { 2591 3917 p_vci_ini_rw.cmdval = true; 2592 p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3; 2593 switch( r_dcache_type_save ) { 3918 3919 addr_40 addr = (addr_40) r_dcache_addr_save[r_vci_cmd_num_cache].read() & ~0x3; 3920 set_num_dcache(addr,r_vci_cmd_num_cache); 3921 3922 PRINTF(" * <CMD> DATA_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); 3923 3924 p_vci_ini_rw.address = addr; 3925 switch( r_dcache_type_save[r_vci_cmd_num_cache] ) { 2594 3926 case iss_t::DATA_READ: 2595 3927 p_vci_ini_rw.wdata = 0; 2596 p_vci_ini_rw.be = r_dcache_be_save .read();3928 p_vci_ini_rw.be = r_dcache_be_save[r_vci_cmd_num_cache].read(); 2597 3929 p_vci_ini_rw.cmd = vci_param::CMD_READ; 2598 3930 break; … … 2607 3939 p_vci_ini_rw.plen = 4; 2608 3940 p_vci_ini_rw.trdid = TYPE_DATA_UNC; // data cache uncached read 2609 p_vci_ini_rw.pktid = 0;3941 p_vci_ini_rw.pktid = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache; 2610 3942 p_vci_ini_rw.srcid = m_srcid_rw; 2611 3943 p_vci_ini_rw.cons = false; … … 2617 3949 2618 3950 break; 2619 3951 } 2620 3952 case CMD_DATA_SC: 3953 { 2621 3954 p_vci_ini_rw.cmdval = true; 2622 p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3; 3955 3956 addr_40 addr = (addr_40) r_dcache_addr_save[r_vci_cmd_num_cache].read() & ~0x3; 3957 set_num_dcache(addr,r_vci_cmd_num_cache); 3958 3959 PRINTF(" * <CMD> DATA_SC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); 3960 3961 p_vci_ini_rw.address = addr; 2623 3962 if(r_vci_cmd_max.read() == 3){ 2624 3963 ASSERT(false, "Not handled yet"); … … 2626 3965 switch(r_vci_cmd_cpt.read()){ 2627 3966 case 0: 2628 p_vci_ini_rw.wdata = (uint32_t)(r_dcache_ll_data .read() & 0xFFFFFFFF);3967 p_vci_ini_rw.wdata = (uint32_t)(r_dcache_ll_data[r_vci_cmd_num_cache][r_dcache_num_cpu_save[r_vci_cmd_num_cache]].read() & 0xFFFFFFFF); 2629 3968 break; 2630 3969 case 1: 2631 p_vci_ini_rw.wdata = r_dcache_wdata_save .read();3970 p_vci_ini_rw.wdata = r_dcache_wdata_save[r_vci_cmd_num_cache].read(); 2632 3971 break; 2633 3972 } … … 2637 3976 p_vci_ini_rw.plen = 4*(r_vci_cmd_max.read()+1); 2638 3977 p_vci_ini_rw.trdid = TYPE_DATA_SC; // data cache uncached read 2639 p_vci_ini_rw.pktid = 0;3978 p_vci_ini_rw.pktid = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache; 2640 3979 p_vci_ini_rw.srcid = m_srcid_rw; 2641 3980 p_vci_ini_rw.cons = true; … … 2647 3986 2648 3987 break; 2649 3988 } 2650 3989 case CMD_DATA_WRITE: 3990 { 2651 3991 p_vci_ini_rw.cmdval = true; 2652 p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt)&~0x3; 2653 p_vci_ini_rw.wdata = r_wbuf.getData(r_vci_cmd_cpt); 2654 p_vci_ini_rw.be = r_wbuf.getBe(r_vci_cmd_cpt); 3992 3993 addr_40 addr = (addr_40) r_wbuf[r_vci_cmd_num_cache]->getAddress(r_vci_cmd_cpt)&~0x3; 3994 3995 PRINTF(" * <CMD> DATA_WRITE : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); 3996 3997 p_vci_ini_rw.address = addr; 3998 p_vci_ini_rw.wdata = r_wbuf[r_vci_cmd_num_cache]->getData(r_vci_cmd_cpt); 3999 p_vci_ini_rw.be = r_wbuf[r_vci_cmd_num_cache]->getBe(r_vci_cmd_cpt); 2655 4000 p_vci_ini_rw.plen = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2; 2656 4001 p_vci_ini_rw.cmd = vci_param::CMD_WRITE; 2657 p_vci_ini_rw.trdid = r_wbuf .getIndex() + (1<<(vci_param::T-1));2658 p_vci_ini_rw.pktid = 0;4002 p_vci_ini_rw.trdid = r_wbuf[r_vci_cmd_num_cache]->getIndex() + (1<<(vci_param::T-1)); 4003 p_vci_ini_rw.pktid = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache; 2659 4004 p_vci_ini_rw.srcid = m_srcid_rw; 2660 4005 p_vci_ini_rw.cons = false; … … 2666 4011 2667 4012 break; 2668 4013 } 2669 4014 case CMD_DATA_MISS: 4015 { 2670 4016 p_vci_ini_rw.cmdval = true; 2671 p_vci_ini_rw.address = r_dcache_addr_save.read() & (addr_40) m_dcache_yzmask; 4017 4018 addr_40 addr = r_dcache_addr_save[r_vci_cmd_num_cache].read() & (addr_40) m_dcache_yzmask; 4019 set_num_dcache(addr,r_vci_cmd_num_cache); 4020 4021 PRINTF(" * <CMD> DATA_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); 4022 4023 p_vci_ini_rw.address = addr; 2672 4024 p_vci_ini_rw.be = 0xF; 2673 4025 p_vci_ini_rw.plen = m_dcache_words << 2; 2674 4026 p_vci_ini_rw.cmd = vci_param::CMD_READ; 2675 4027 p_vci_ini_rw.trdid = TYPE_DATA_MISS; // data cache cached read 2676 p_vci_ini_rw.pktid = 0;4028 p_vci_ini_rw.pktid = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache; 2677 4029 p_vci_ini_rw.srcid = m_srcid_rw; 2678 4030 p_vci_ini_rw.cons = false; … … 2684 4036 2685 4037 break; 2686 4038 } 2687 4039 case CMD_INS_MISS: 4040 { 2688 4041 p_vci_ini_rw.cmdval = true; 2689 p_vci_ini_rw.address = r_icache_addr_save.read() & (addr_40) m_icache_yzmask; 4042 4043 addr_40 addr = r_icache_addr_save[r_vci_cmd_num_cache].read() & (addr_40) m_icache_yzmask; 4044 set_num_icache(addr,r_vci_cmd_num_cache); 4045 4046 PRINTF(" * <CMD> INS_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); 4047 4048 p_vci_ini_rw.address = addr; 2690 4049 p_vci_ini_rw.be = 0xF; 2691 4050 p_vci_ini_rw.plen = m_icache_words << 2; 2692 4051 p_vci_ini_rw.cmd = vci_param::CMD_READ; 2693 4052 p_vci_ini_rw.trdid = TYPE_INS_MISS; // ins cache cached read 2694 p_vci_ini_rw.pktid = 0;4053 p_vci_ini_rw.pktid = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache; 2695 4054 p_vci_ini_rw.srcid = m_srcid_rw; 2696 4055 p_vci_ini_rw.cons = false; … … 2702 4061 2703 4062 break; 2704 4063 } 2705 4064 case CMD_INS_UNC: 4065 { 2706 4066 p_vci_ini_rw.cmdval = true; 2707 p_vci_ini_rw.address = r_icache_addr_save.read() & ~0x3; 4067 4068 addr_40 addr = r_icache_addr_save[r_vci_cmd_num_cache].read() & ~0x3; 4069 set_num_icache(addr,r_vci_cmd_num_cache); 4070 4071 PRINTF(" * <CMD> INS_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); 4072 4073 p_vci_ini_rw.address = addr; 2708 4074 p_vci_ini_rw.be = 0xF; 2709 4075 p_vci_ini_rw.plen = 4; 2710 4076 p_vci_ini_rw.cmd = vci_param::CMD_READ; 2711 4077 p_vci_ini_rw.trdid = TYPE_INS_UNC; // ins cache uncached read 2712 p_vci_ini_rw.pktid = 0;4078 p_vci_ini_rw.pktid = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache; 2713 4079 p_vci_ini_rw.srcid = m_srcid_rw; 2714 4080 p_vci_ini_rw.cons = false; … … 2720 4086 2721 4087 break; 2722 4088 } 2723 4089 } // end switch r_vci_cmd_fsm 2724 4090 2725 bool ack; 2726 2727 switch (r_vci_rsp_fsm.read() ) { 2728 case RSP_IDLE : ack = false; break; 2729 case RSP_DATA_WRITE : ack = true; break; 2730 case RSP_INS_MISS : 2731 case RSP_INS_UNC : ack = CACHE_MISS_BUF_RSP_ACK(i); break; 2732 case RSP_DATA_MISS : 2733 case RSP_DATA_UNC : 2734 case RSP_DATA_SC : ack = CACHE_MISS_BUF_RSP_ACK(d); break; 2735 } // end switch r_vci_cmd_fsm 2736 2737 r_vci_rsp_ack = ack; 2738 p_vci_ini_rw.rspack = ack; 2739 4091 { 4092 bool ack; 4093 4094 switch (r_vci_rsp_fsm.read() ) { 4095 case RSP_DATA_WRITE : ack = true; break; 4096 case RSP_INS_MISS : 4097 case RSP_INS_UNC : ack = CACHE_MISS_BUF_RSP_ACK(i,r_vci_rsp_num_cache); break; 4098 case RSP_DATA_MISS : 4099 case RSP_DATA_UNC : 4100 case RSP_DATA_SC : ack = CACHE_MISS_BUF_RSP_ACK(d,r_vci_rsp_num_cache); break; 4101 4102 case RSP_IDLE : 4103 default : ack = false; break; 4104 4105 } // end switch r_vci_cmd_fsm 4106 4107 s_vci_rsp_ack = ack; 4108 p_vci_ini_rw.rspack = ack; 4109 4110 PRINTF(" * <RSP> rspack : %d\n", ack); 4111 } 4112 2740 4113 // VCI_TGT 4114 4115 // PRINTF(" * <TGT> srcid : %d\n", r_tgt_srcid.read()); 2741 4116 2742 4117 switch ( r_vci_tgt_fsm.read() ) { … … 2750 4125 2751 4126 case TGT_RSP_BROADCAST: 2752 p_vci_tgt.cmdack = false; 2753 p_vci_tgt.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() and ( r_tgt_icache_rsp | r_tgt_dcache_rsp ); 2754 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 2755 p_vci_tgt.rpktid = r_tgt_pktid.read(); 2756 p_vci_tgt.rtrdid = r_tgt_trdid.read(); 2757 p_vci_tgt.rdata = 0; 2758 p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK 2759 p_vci_tgt.reop = true; 2760 break; 2761 4127 { 4128 bool tgt_icache_req; 4129 bool tgt_icache_rsp; 4130 4131 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 4132 tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read(); 4133 tgt_icache_rsp = r_tgt_icache_rsp[r_tgt_num_cache].read(); 4134 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 4135 tgt_icache_req = false; 4136 tgt_icache_rsp = false; 4137 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 4138 { 4139 tgt_icache_req |= r_tgt_icache_req[num_cache].read(); 4140 tgt_icache_rsp |= r_tgt_icache_rsp[num_cache].read(); 4141 } 4142 #endif 4143 4144 bool rspval = ((not tgt_icache_req and not r_tgt_dcache_req[r_tgt_num_cache].read()) 4145 and (tgt_icache_rsp | r_tgt_dcache_rsp[r_tgt_num_cache])); 4146 4147 PRINTF(" * <TGT> RSP_BROADCAST : rspval : %d (i %d %d, d %d %d)\n",rspval,tgt_icache_req,tgt_icache_rsp, r_tgt_dcache_req[r_tgt_num_cache].read(), r_tgt_dcache_rsp[r_tgt_num_cache].read()); 4148 4149 p_vci_tgt.cmdack = false; 4150 p_vci_tgt.rspval = rspval; 4151 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 4152 p_vci_tgt.rpktid = r_tgt_pktid.read(); 4153 p_vci_tgt.rtrdid = r_tgt_trdid.read(); 4154 p_vci_tgt.rdata = 0; 4155 p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK 4156 p_vci_tgt.reop = true; 4157 break; 4158 } 2762 4159 case TGT_RSP_ICACHE: 2763 p_vci_tgt.cmdack = false; 2764 p_vci_tgt.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read(); 2765 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 2766 p_vci_tgt.rpktid = r_tgt_pktid.read(); 2767 p_vci_tgt.rtrdid = r_tgt_trdid.read(); 2768 p_vci_tgt.rdata = 0; 2769 p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK 2770 p_vci_tgt.reop = true; 2771 break; 2772 4160 { 4161 bool rspval = not r_tgt_icache_req[r_tgt_num_cache].read() and r_tgt_icache_rsp[r_tgt_num_cache].read(); 4162 4163 PRINTF(" * <TGT> RSP_ICACHE : rspval : %d\n",rspval); 4164 4165 p_vci_tgt.cmdack = false; 4166 p_vci_tgt.rspval = rspval; 4167 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 4168 p_vci_tgt.rpktid = r_tgt_pktid.read(); 4169 p_vci_tgt.rtrdid = r_tgt_trdid.read(); 4170 p_vci_tgt.rdata = 0; 4171 p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK 4172 p_vci_tgt.reop = true; 4173 break; 4174 } 2773 4175 case TGT_RSP_DCACHE: 2774 p_vci_tgt.cmdack = false; 2775 p_vci_tgt.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read(); 2776 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 2777 p_vci_tgt.rpktid = r_tgt_pktid.read(); 2778 p_vci_tgt.rtrdid = r_tgt_trdid.read(); 2779 p_vci_tgt.rdata = 0; 2780 p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK 2781 p_vci_tgt.reop = true; 2782 break; 2783 4176 { 4177 bool rspval = not r_tgt_dcache_req[r_tgt_num_cache].read() and r_tgt_dcache_rsp[r_tgt_num_cache].read(); 4178 4179 PRINTF(" * <TGT> RSP_DCACHE : rspval : %d\n",rspval); 4180 4181 p_vci_tgt.cmdack = false; 4182 p_vci_tgt.rspval = rspval; 4183 p_vci_tgt.rsrcid = r_tgt_srcid.read(); 4184 p_vci_tgt.rpktid = r_tgt_pktid.read(); 4185 p_vci_tgt.rtrdid = r_tgt_trdid.read(); 4186 p_vci_tgt.rdata = 0; 4187 p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK 4188 p_vci_tgt.reop = true; 4189 break; 4190 } 2784 4191 case TGT_REQ_BROADCAST: 2785 4192 case TGT_REQ_ICACHE: … … 2814 4221 } 2815 4222 4223 ////////////////////////////////////////////////////////////////////////////////// 4224 tmpl(uint32_t)::get_num_cache(addr_40 & addr) 4225 ////////////////////////////////////////////////////////////////////////////////// 4226 { 4227 uint32_t num_cache = get_num_cache_only(addr); 4228 4229 addr = ((addr&m_num_cache_LSB_mask) | // keep LSB 4230 ((addr>>m_num_cache_MSB)<<m_num_cache_LSB)); // set MSB 4231 4232 return num_cache; 4233 } 4234 4235 ////////////////////////////////////////////////////////////////////////////////// 4236 tmpl(uint32_t)::get_num_cache_only(addr_40 addr) 4237 ////////////////////////////////////////////////////////////////////////////////// 4238 { 4239 return (addr>>m_num_cache_LSB)&m_num_cache_mask; 4240 } 4241 4242 ////////////////////////////////////////////////////////////////////////////////// 4243 tmpl(void)::set_num_cache(addr_40 & addr, uint32_t num_cache) 4244 ////////////////////////////////////////////////////////////////////////////////// 4245 { 4246 addr = ((addr&m_num_cache_LSB_mask) | // keep LSB 4247 ((addr_40)num_cache << m_num_cache_LSB) | 4248 ((addr>>m_num_cache_LSB)<<m_num_cache_MSB)); // set MSB 4249 } 4250 4251 ////////////////////////////////////////////////////////////////////////////////// 4252 // fixme : mettre le type addr_40 4253 tmpl(sc_dt::sc_uint<40>)::set_num_cache_only(addr_40 addr, uint32_t num_cache) 4254 ////////////////////////////////////////////////////////////////////////////////// 4255 { 4256 return ((addr&m_num_cache_LSB_mask) | // keep LSB 4257 ((addr_40)num_cache << m_num_cache_LSB) | 4258 ((addr>>m_num_cache_LSB)<<m_num_cache_MSB)); // set MSB 4259 } 4260 4261 2816 4262 }} // end namespace 2817 4263
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