- Timestamp:
- Mar 16, 2011, 2:23:15 PM (14 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r140 r141 244 244 size_t nsets, 245 245 size_t nwords, 246 size_t heap_size) 246 size_t heap_size, 247 size_t transaction_tab_lines, 248 size_t update_tab_lines) 247 249 248 250 : soclib::caba::BaseModule(name), … … 265 267 m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)), 266 268 m_coherence_table( mtc.getCoherenceTable<vci_addr_t>() ), 267 m_transaction_tab( TRANSACTION_TAB_LINES, nwords ), 268 m_update_tab( UPDATE_TAB_LINES ), 269 m_transaction_tab_lines(transaction_tab_lines), 270 m_transaction_tab( transaction_tab_lines, nwords ), 271 m_update_tab_lines( update_tab_lines), 272 m_update_tab( update_tab_lines ), 269 273 m_cache_directory( nways, nsets, nwords, vci_param::N ), 270 274 m_heap_directory( m_heap_size ), … … 338 342 assert(nwords); 339 343 assert(nways); 340 assert(nsets <= 1024);341 assert(nwords <= 32);342 assert(nways <= 32);343 344 344 345 // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum … … 383 384 384 385 // Allocation for IXR_RSP FSM 385 r_ixr_rsp_to_xram_rsp_rok = new sc_signal<bool>[ TRANSACTION_TAB_LINES];386 r_ixr_rsp_to_xram_rsp_rok = new sc_signal<bool>[m_transaction_tab_lines]; 386 387 387 388 // Allocation for XRAM_RSP FSM … … 441 442 std::cout << "----------------------------------" << std::dec << std::endl; 442 443 std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl 443 << "- READ RATE = " << (double)m_cpt_read/m_cpt_cycles << std::endl 444 << "- READ MISS RATE = " << (double)m_cpt_read_miss/m_cpt_read << std::endl 445 << "- WRITE RATE = " << (double)m_cpt_write/m_cpt_cycles << std::endl 446 << "- WRITE MISS RATE = " << (double)m_cpt_write_miss/m_cpt_write << std::endl 447 << "- WRITE BURST LENGTH = " << (double)m_cpt_write_cells/m_cpt_write << std::endl 448 << "- UPDATE RATE = " << (double)m_cpt_update/m_cpt_cycles << std::endl 449 << "- UPDATE ARITY = " << (double)m_cpt_update_mult/m_cpt_update << std::endl 450 << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl 451 << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl 452 << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl 453 << "- SAVE DIRTY RATE = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl 454 << "- CLEANUP RATE = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl 455 << "- LL RATE = " << (double)m_cpt_ll/m_cpt_cycles << std::endl 456 << "- SC RATE = " << (double)m_cpt_sc/m_cpt_cycles << std::endl; 444 << "- READ RATE = " << (double)m_cpt_read/m_cpt_cycles << std::endl 445 << "- READ TOTAL = " << m_cpt_read << std::endl 446 << "- READ MISS RATE = " << (double)m_cpt_read_miss/m_cpt_read << std::endl 447 << "- WRITE RATE = " << (double)m_cpt_write/m_cpt_cycles << std::endl 448 << "- WRITE TOTAL = " << m_cpt_write << std::endl 449 << "- WRITE MISS RATE = " << (double)m_cpt_write_miss/m_cpt_write << std::endl 450 << "- WRITE BURST LENGTH = " << (double)m_cpt_write_cells/m_cpt_write << std::endl 451 << "- WRITE BURST TOTAL = " << m_cpt_write_cells << std::endl 452 << "- REQUESTS TRT FULL = " << m_cpt_trt_full << std::endl 453 << "- READ TRT BLOKED HIT = " << m_cpt_trt_rb << std::endl 454 << "- UPDATE RATE = " << (double)m_cpt_update/m_cpt_cycles << std::endl 455 << "- UPDATE ARITY = " << (double)m_cpt_update_mult/m_cpt_update << std::endl 456 << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl 457 << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl 458 << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl 459 << "- SAVE DIRTY RATE = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl 460 << "- CLEANUP RATE = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl 461 << "- LL RATE = " << (double)m_cpt_ll/m_cpt_cycles << std::endl 462 << "- SC RATE = " << (double)m_cpt_sc/m_cpt_cycles << std::endl; 457 463 } 458 464 … … 567 573 #endif 568 574 569 for(size_t i=0; i< TRANSACTION_TAB_LINES; i++){575 for(size_t i=0; i<m_transaction_tab_lines ; i++){ 570 576 r_ixr_rsp_to_xram_rsp_rok[i] = false; 571 577 } … … 602 608 m_cpt_ll = 0; 603 609 m_cpt_sc = 0; 610 m_cpt_trt_full = 0; 611 m_cpt_trt_rb = 0; 604 612 605 613 return; … … 721 729 if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) { 722 730 cmd_read_fifo_put = true; 723 if ( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE; 724 else r_tgt_cmd_fsm = TGT_CMD_READ_EOP; 731 if ( p_vci_tgt.eop ) { 732 m_cpt_read++; 733 r_tgt_cmd_fsm = TGT_CMD_IDLE; 734 } else r_tgt_cmd_fsm = TGT_CMD_READ_EOP; 725 735 } 726 736 break; … … 730 740 { 731 741 if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){ 742 m_cpt_read++; 732 743 r_tgt_cmd_fsm = TGT_CMD_IDLE; 733 744 } … … 881 892 PRINTF(" * <MEM_CACHE.READ> Request from %d.%d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint32_t)m_cmd_read_pktid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read()); 882 893 883 m_cpt_read++;884 894 r_read_fsm = READ_DIR_LOCK; 885 895 } … … 922 932 } else { 923 933 r_read_fsm = READ_TRT_LOCK; 924 m_cpt_read_miss++;925 934 } 926 935 } … … 1162 1171 bool wok = !m_transaction_tab.full(index); 1163 1172 if( hit_read || !wok || hit_write ) { // missing line already requested or no space 1173 if(!wok) 1174 m_cpt_trt_full++; 1175 if(hit_read || hit_write) 1176 m_cpt_trt_rb++; 1164 1177 r_read_fsm = READ_IDLE; 1165 1178 } else { // missing line is requested to the XRAM 1179 m_cpt_read_miss++; 1166 1180 r_read_trt_index = index; 1167 1181 r_read_fsm = READ_TRT_SET; … … 1324 1338 } else { 1325 1339 r_write_fsm = WRITE_TRT_LOCK; 1326 m_cpt_write_miss++;1327 1340 } 1328 1341 } … … 1594 1607 r_write_trt_index = hit_index; 1595 1608 r_write_fsm = WRITE_TRT_DATA; 1609 m_cpt_write_miss++; 1596 1610 } else if ( wok && !hit_write ) { // set a new entry in TRT 1597 1611 r_write_trt_index = wok_index; 1598 1612 r_write_fsm = WRITE_TRT_SET; 1613 m_cpt_write_miss++; 1599 1614 } else { // wait an empty entry in TRT 1600 1615 r_write_fsm = WRITE_WAIT; 1616 m_cpt_trt_full++; 1601 1617 } 1602 1618 } … … 2040 2056 { 2041 2057 size_t ptr = r_xram_rsp_trt_index.read(); 2042 size_t lines = TRANSACTION_TAB_LINES;2058 size_t lines = m_transaction_tab_lines; 2043 2059 for(size_t i=0; i<lines; i++){ 2044 2060 size_t index=(i+ptr+1)%lines; … … 4859 4875 4860 4876 // Local Variables: 4861 // tab-width: 44862 // c-basic-offset: 44877 // tab-width: 2 4878 // c-basic-offset: 2 4863 4879 // c-file-offsets:((innamespace . 0)(inline-open . 0)) 4864 4880 // indent-tabs-mode: nil
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