Changeset 143 for trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
- Timestamp:
- Mar 28, 2011, 6:46:33 PM (14 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r140 r143 43 43 44 44 /* 45 * CC_XCACHE_WRAPPER_SELECT_VICTIM :46 * The selection and the update of cache (after a read miss)47 * are separated in two step48 * Also, the cleanup can be send in parallel at the read miss.49 *50 45 * CC_XCACHE_WRAPPER_FIFO_RSP 51 46 * Two simple fifo (each 2x32 depth) receive the cache line from 52 47 * RAM. Instead of two buffers (m_icache_words and m_dcache_words) 48 * 1 - nb_icache+nb_dcache simple fifo 49 * 2 - 2 simple fifo 50 * else - two buffers (m_icache_words and m_dcache_words) 53 51 * 54 52 * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 67 65 * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 68 66 * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req 69 * 1 - two access authorized70 * 2 - one access with static priority ( dcache prior)71 * 3 - one access with static priority (icache prior)72 * 4 - one access with round robin priority67 * 1 - one access with static priority (dcache prior) 68 * 2 - one access with static priority (icache prior) 69 * 3 - one access with round robin priority 70 * 4 - two access authorized 73 71 * 74 72 * CC_XCACHE_WRAPPER_MULTI_CACHE : … … 95 93 96 94 // implementation 97 #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM98 #define CC_XCACHE_WRAPPER_SELECT_VICTIM 199 #endif100 95 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP 101 96 #define CC_XCACHE_WRAPPER_FIFO_RSP 1 … … 111 106 #endif 112 107 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 113 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 4108 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3 114 109 #endif 115 110 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE 116 111 #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 117 #endif 112 // if multi_cache : 113 // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 114 // <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1 115 #endif 116 118 117 // debugging 118 #ifndef CC_XCACHE_WRAPPER_VERBOSE 119 #define CC_XCACHE_WRAPPER_VERBOSE 1 120 #endif 119 121 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION 120 122 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 … … 124 126 #endif 125 127 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 126 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 949900128 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1500 127 129 #endif 128 130 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION … … 158 160 DCACHE_IDLE, 159 161 DCACHE_WRITE_UPDT, 160 #if CC_XCACHE_WRAPPER_SELECT_VICTIM161 162 DCACHE_MISS_VICTIM, 162 #endif163 163 DCACHE_MISS_WAIT, 164 164 DCACHE_MISS_UPDT, … … 176 176 enum icache_fsm_state_e { 177 177 ICACHE_IDLE, 178 #if CC_XCACHE_WRAPPER_SELECT_VICTIM179 178 ICACHE_MISS_VICTIM, 180 #endif181 179 ICACHE_MISS_WAIT, 182 180 ICACHE_MISS_UPDT, … … 341 339 sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] 342 340 343 #if CC_XCACHE_WRAPPER_FIFO_RSP341 #if (CC_XCACHE_WRAPPER_FIFO_RSP==1) 344 342 std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache] 345 343 std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache] 344 #elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) 345 typedef struct 346 { 347 data_t data; 348 uint32_t num_cache; 349 } miss_buf_t; 350 351 std::queue<miss_buf_t> r_icache_miss_buf; 352 std::queue<miss_buf_t> r_dcache_miss_buf; 346 353 #else 347 354 bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words]
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