Changeset 147
- Timestamp:
- Apr 20, 2011, 1:19:10 PM (14 years ago)
- Location:
- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r144 r147 31 31 32 32 #include <inttypes.h> 33 #include <fstream>34 33 #include <systemc> 35 34 #include <queue> … … 43 42 44 43 /* 44 * CC_XCACHE_WRAPPER_SELECT_VICTIM : 45 * The selection and the update of cache (after a read miss) 46 * are separated in two step 47 * Also, the cleanup can be send in parallel at the read miss. 48 * 45 49 * CC_XCACHE_WRAPPER_FIFO_RSP 46 50 * Two simple fifo (each 2x32 depth) receive the cache line from 47 51 * RAM. Instead of two buffers (m_icache_words and m_dcache_words) 48 * 1 - nb_icache+nb_dcache simple fifo49 * 2 - 2 simple fifo50 * else - two buffers (m_icache_words and m_dcache_words)51 52 * 52 53 * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 65 66 * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 66 67 * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req 67 * 1 - one access with static priority (dcache prior) 68 * 2 - one access with static priority (icache prior) 69 * 3 - one access with round robin priority 70 * 4 - two access authorized 71 * 72 * CC_XCACHE_WRAPPER_MULTI_CACHE : 73 * 1 - icache static partitionnement 74 * 2 - icache dedicated 75 * 76 * CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 77 * (In multi-cache) 78 * A dcache used by a cpu and in miss_wait state can be use by 79 * an another cpu to make a load cached access. 80 * 81 * CC_XCACHE_WRAPPER_STORE_AFTER_STORE 82 * Store access in dcache (and hit) is make in two cycle : 83 * - first read directory and read data 84 * - second make a mask with old data and write new data. 85 * If data part has a write enable per byte, read data access can be suppress 86 * and we can pipeline consecutive store access. 87 * 68 * 1 - two access authorized 69 * 2 - one access with static priority (dcache prior) 70 * 3 - one access with static priority (icache prior) 71 * 4 - one access with round robin priority 72 * 88 73 * CC_XCACHE_WRAPPER_STOP_SIMULATION : 89 74 * stop simulation if processor is stall after a long time … … 96 81 * Number of cycle before to prinf debug message 97 82 * 98 * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 99 * Print transaction between : 100 * - the cpu and the cache (icache and dcache) 101 * - vci 102 * - cleanup 103 * - coherency 83 * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 84 * Print transaction between the cpu and the cache 104 85 */ 105 86 106 87 // implementation 88 #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM 89 #define CC_XCACHE_WRAPPER_SELECT_VICTIM 0 90 #endif 107 91 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP 108 #define CC_XCACHE_WRAPPER_FIFO_RSP 292 #define CC_XCACHE_WRAPPER_FIFO_RSP 0 109 93 #endif 110 94 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 111 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 95 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 112 96 #endif 113 97 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 114 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 98 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 115 99 #endif 116 100 #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 117 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 2101 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 0 118 102 #endif 119 103 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 120 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3 121 #endif 122 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE 123 #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 124 // if multi_cache : 125 // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 126 // <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1 127 #endif 128 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 129 #define CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1 130 #endif 131 #ifndef CC_XCACHE_WRAPPER_STORE_AFTER_STORE 132 #define CC_XCACHE_WRAPPER_STORE_AFTER_STORE 1 133 #endif 134 104 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 2 105 #endif 135 106 // debugging 136 #ifndef CC_XCACHE_WRAPPER_VERBOSE137 #define CC_XCACHE_WRAPPER_VERBOSE 1138 #endif139 107 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION 140 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 108 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 141 109 #endif 142 110 #ifndef CC_XCACHE_WRAPPER_DEBUG 143 #define CC_XCACHE_WRAPPER_DEBUG 111 #define CC_XCACHE_WRAPPER_DEBUG 0 144 112 #endif 145 113 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 146 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1500 147 #endif 148 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 149 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 150 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" 151 #endif 152 153 // don't change 154 #if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 155 #undef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 156 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 0 114 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 200000 115 #endif 116 #ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 117 #define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 0 157 118 #endif 158 119 … … 178 139 DCACHE_IDLE, 179 140 DCACHE_WRITE_UPDT, 141 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 180 142 DCACHE_MISS_VICTIM, 143 #endif 181 144 DCACHE_MISS_WAIT, 182 145 DCACHE_MISS_UPDT, … … 194 157 enum icache_fsm_state_e { 195 158 ICACHE_IDLE, 159 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 196 160 ICACHE_MISS_VICTIM, 161 #endif 197 162 ICACHE_MISS_WAIT, 198 163 ICACHE_MISS_UPDT, … … 239 204 enum cleanup_fsm_state_e { 240 205 CLEANUP_IDLE, 241 CLEANUP_REQ, 242 CLEANUP_RSP_DCACHE, 243 CLEANUP_RSP_ICACHE, 206 CLEANUP_DCACHE, 207 CLEANUP_ICACHE, 244 208 }; 245 209 … … 267 231 sc_in<bool> p_clk; 268 232 sc_in<bool> p_resetn; 269 sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq];233 sc_in<bool> p_irq[iss_t::n_irq]; 270 234 soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; 271 235 soclib::caba::VciInitiator<vci_param> p_vci_ini_c; … … 277 241 const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; 278 242 const soclib::common::Segment m_segment; 279 iss_t ** m_iss; //[m_nb_cpu]243 iss_t m_iss; 280 244 const uint32_t m_srcid_rw; 281 245 const uint32_t m_srcid_c; 282 246 283 const size_t m_nb_cpu;284 const size_t m_nb_icache;285 const size_t m_nb_dcache;286 const size_t m_nb_cache;287 247 const size_t m_dcache_ways; 288 248 const size_t m_dcache_words; … … 298 258 bool m_stop_simulation; 299 259 uint32_t m_stop_simulation_nb_frz_cycles_max; 300 uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]260 uint32_t m_stop_simulation_nb_frz_cycles; 301 261 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 302 262 303 263 // REGISTERS 304 sc_signal<uint32_t> r_cpu_prior; 305 sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache] 306 sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache] 307 sc_signal<bool> * r_dcache_sync;//[m_nb_dcache] 308 309 sc_signal<int> * r_dcache_fsm; //[m_nb_dcache] 310 sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache] 311 sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache] 312 sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache] 313 sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache] 314 sc_signal<int> * r_dcache_type_save; //[m_nb_dcache] 315 sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache] 316 sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache] 317 sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache] 318 sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache] 319 sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache] 320 sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache] 321 sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache] 322 sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache] 323 sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache] 324 sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache] 325 sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache] 326 sc_signal<data_64> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] 327 sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] 328 sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] 329 sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache] 330 sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache] 331 332 sc_signal<int> * r_icache_fsm; //[m_nb_icache] 333 sc_signal<int> * r_icache_fsm_save; //[m_nb_icache] 334 sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache] 335 sc_signal<bool> * r_icache_miss_req; //[m_nb_icache] 336 sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache] 337 sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache] 338 sc_signal<bool> * r_icache_unc_req; //[m_nb_icache] 339 sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache] 340 sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache] 341 sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache] 342 sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache] 343 sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache] 264 sc_signal<int> r_dcache_fsm; 265 sc_signal<int> r_dcache_fsm_save; 266 sc_signal<addr_40> r_dcache_addr_save; 267 sc_signal<data_t> r_dcache_wdata_save; 268 sc_signal<data_t> r_dcache_rdata_save; 269 sc_signal<int> r_dcache_type_save; 270 sc_signal<be_t> r_dcache_be_save; 271 sc_signal<bool> r_dcache_cached_save; 272 sc_signal<bool> r_dcache_cleanup_req; 273 sc_signal<addr_40> r_dcache_cleanup_line; 274 sc_signal<bool> r_dcache_miss_req; 275 sc_signal<size_t> r_dcache_miss_way; 276 sc_signal<size_t> r_dcache_miss_set; 277 sc_signal<bool> r_dcache_unc_req; 278 sc_signal<bool> r_dcache_sc_req; 279 sc_signal<bool> r_dcache_inval_rsp; 280 sc_signal<size_t> r_dcache_update_addr; 281 sc_signal<data_64> r_dcache_ll_data; 282 sc_signal<addr_40> r_dcache_ll_addr; 283 sc_signal<bool> r_dcache_ll_valid; 284 sc_signal<bool> r_dcache_previous_unc; 285 286 sc_signal<int> r_icache_fsm; 287 sc_signal<int> r_icache_fsm_save; 288 sc_signal<addr_40> r_icache_addr_save; 289 sc_signal<bool> r_icache_miss_req; 290 sc_signal<size_t> r_icache_miss_way; 291 sc_signal<size_t> r_icache_miss_set; 292 sc_signal<bool> r_icache_unc_req; 293 sc_signal<bool> r_icache_cleanup_req; 294 sc_signal<addr_40> r_icache_cleanup_line; 295 sc_signal<bool> r_icache_inval_rsp; 296 sc_signal<size_t> r_icache_update_addr; 344 297 345 298 sc_signal<int> r_vci_cmd_fsm; … … 348 301 sc_signal<size_t> r_vci_cmd_cpt; 349 302 sc_signal<bool> r_vci_cmd_dcache_prior; 350 sc_signal<uint32_t> r_vci_cmd_num_cache; 351 303 352 304 sc_signal<int> r_vci_rsp_fsm; 305 sc_signal<bool> r_vci_rsp_ins_error; 306 sc_signal<bool> r_vci_rsp_data_error; 353 307 sc_signal<size_t> r_vci_rsp_cpt; 354 bool s_vci_rsp_ack; 355 sc_signal<uint32_t> r_vci_rsp_num_cache; 356 sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache] 357 sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] 358 359 #if (CC_XCACHE_WRAPPER_FIFO_RSP==1) 360 std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache] 361 std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache] 362 #elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) 363 typedef struct 364 { 365 data_t data; 366 uint32_t num_cache; 367 } miss_buf_t; 368 369 std::queue<miss_buf_t> r_icache_miss_buf; 370 std::queue<miss_buf_t> r_dcache_miss_buf; 308 sc_signal<bool> r_vci_rsp_ack; 309 310 #if CC_XCACHE_WRAPPER_FIFO_RSP 311 std::queue<data_t> r_icache_miss_buf; 312 std::queue<data_t> r_dcache_miss_buf; 371 313 #else 372 bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words] 373 data_t ** r_icache_miss_buf; //[m_nb_icache][m_icache_words] 374 bool ** r_dcache_miss_val; //[m_nb_dcache][m_dcache_words] 375 data_t ** r_dcache_miss_buf; //[m_nb_dcache][m_dcache_words] 376 #endif 377 data_t * r_tgt_buf; //[m_cache_words] 378 be_t * r_tgt_be; //[m_cache_words] 314 bool *r_icache_miss_val; //[m_icache_words] 315 data_t *r_icache_miss_buf; //[m_icache_words] 316 bool *r_dcache_miss_val; //[m_dcache_words] 317 data_t *r_dcache_miss_buf; //[m_dcache_words] 318 #endif 319 sc_signal<bool> r_icache_buf_unc_valid; 320 321 data_t *r_tgt_buf; //[m_cache_words] 322 be_t *r_tgt_be; //[m_cache_words] 379 323 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 380 324 sc_signal<uint32_t> r_cache_word; … … 382 326 383 327 sc_signal<int> r_vci_tgt_fsm; 384 sc_signal<addr_40> r_tgt_iaddr; 385 sc_signal<addr_40> r_tgt_daddr; 328 sc_signal<addr_40> r_tgt_addr; 386 329 sc_signal<size_t> r_tgt_word; 387 330 sc_signal<bool> r_tgt_update; … … 392 335 sc_signal<size_t> r_tgt_trdid; 393 336 //sc_signal<size_t> r_tgt_plen; 394 sc_signal<uint32_t> r_tgt_num_cache; 395 sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache] 396 sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache] 397 sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache] 398 sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache] 337 sc_signal<bool> r_tgt_icache_req; 338 sc_signal<bool> r_tgt_dcache_req; 339 sc_signal<bool> r_tgt_icache_rsp; 340 sc_signal<bool> r_tgt_dcache_rsp; 399 341 400 342 sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network 401 sc_signal<uint32_t> r_cleanup_num_cache; 402 sc_signal<bool> r_cleanup_icache; 403 404 MultiWriteBuffer<addr_40>** r_wbuf; 405 GenericCache<vci_addr_t> ** r_icache; 406 GenericCache<vci_addr_t> ** r_dcache; 407 408 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 409 std::ofstream * log_transaction_file_icache; //[m_nb_cpu] 410 std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] 411 std::ofstream log_transaction_file_cmd; 412 std::ofstream log_transaction_file_tgt; 413 std::ofstream log_transaction_file_cleanup; 343 344 MultiWriteBuffer<addr_40> r_wbuf; 345 GenericCache<vci_addr_t> r_icache; 346 GenericCache<vci_addr_t> r_dcache; 347 348 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 349 std::ofstream log_dcache_transaction_file; 414 350 #endif 415 351 416 352 // Activity counters 417 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 418 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 419 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 420 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 421 422 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 423 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 424 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 425 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 426 427 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 428 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 429 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 430 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 431 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 432 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 433 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 434 435 uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 436 uint32_t m_cpt_total_cycles; // total number of cycles 437 438 uint32_t m_cpt_data_read; // number of data read 439 uint32_t m_cpt_data_read_miss; // number of data read miss 440 uint32_t m_cpt_data_read_uncached; // number of data read uncached 441 uint32_t m_cpt_data_write; // number of data write 442 uint32_t m_cpt_data_write_miss; // number of data write miss 443 uint32_t m_cpt_data_write_uncached; // number of data write uncached 444 uint32_t m_cpt_ins_miss; // * number of instruction miss 445 446 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 447 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 448 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 449 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 450 451 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 452 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 453 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 454 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 455 456 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 457 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 458 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 459 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 460 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 461 462 uint32_t * m_cpt_icache_access; //[m_nb_icache] 463 uint32_t * m_cpt_dcache_access; //[m_nb_dcache] 464 uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache] 465 uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache] 466 uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache] 467 uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache] 468 uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache] 469 470 uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] 471 uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] 472 uint32_t * m_cpt_fsm_cmd; 473 uint32_t * m_cpt_fsm_rsp; 474 uint32_t * m_cpt_fsm_tgt; 475 uint32_t * m_cpt_fsm_cleanup; 476 477 // Non blocking multi-cache 478 typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] 479 typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] 480 bool * ireq_cached ; //[m_nb_icache] 481 uint32_t * ireq_num_cpu; //[m_nb_dcache] 482 typename iss_t::DataRequest * dreq ; //[m_nb_dcache] 483 typename iss_t::DataResponse * drsp ; //[m_nb_dcache] 484 bool * dreq_cached ; //[m_nb_dcache] 485 uint32_t * dreq_num_cpu; //[m_nb_dcache] 486 487 const uint32_t m_num_cache_LSB; 488 const uint32_t m_num_cache_MSB; 489 addr_40 m_num_cache_LSB_mask; 490 addr_40 m_num_cache_mask; 353 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 354 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 355 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 356 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 357 358 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 359 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 360 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 361 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 362 363 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 364 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 365 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 366 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 367 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 368 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 369 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 370 371 uint32_t m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 372 uint32_t m_cpt_total_cycles; // total number of cycles 373 374 uint32_t m_cpt_data_read; // number of data read 375 uint32_t m_cpt_data_read_miss; // number of data read miss 376 uint32_t m_cpt_data_read_uncached; // number of data read uncached 377 uint32_t m_cpt_data_write; // number of data write 378 uint32_t m_cpt_data_write_miss; // number of data write miss 379 uint32_t m_cpt_data_write_uncached; // number of data write uncached 380 uint32_t m_cpt_ins_miss; // * number of instruction miss 381 382 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 383 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 384 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 385 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 386 387 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 388 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 389 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 390 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 391 392 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 393 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 394 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 395 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 396 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 491 397 492 398 protected: … … 503 409 const soclib::common::IntTab &initiator_index_c, 504 410 const soclib::common::IntTab &target_index, 505 size_t nb_cpu,506 size_t nb_cache,507 411 size_t icache_ways, 508 412 size_t icache_sets, … … 518 422 ~VciCcXCacheWrapperV4(); 519 423 520 void print_trace(size_t mode = 0);521 void print_cpi();522 void print_stats(bool print_wbuf=true, bool print_fsm=true);424 void print_trace(size_t mode = 0); 425 void print_cpi(); 426 void print_stats(); 523 427 524 428 // #if CC_XCACHE_WRAPPER_STOP_SIMULATION … … 531 435 void genMoore(); 532 436 533 uint32_t get_num_cache (addr_40 & addr); 534 uint32_t get_num_cache_only(addr_40 addr); 535 void set_num_cache (addr_40 & addr, uint32_t num_cache); 536 addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache); 537 538 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); 437 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); 539 438 soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); 540 439 }; -
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
r144 r147 55 55 /////////////////////////////////////////////////////////////////////////////// 56 56 57 #include <cassert> 57 58 #include <iomanip> 58 59 #include "arithmetics.h" 59 #include "size.h"60 60 #include "../include/vci_cc_xcache_wrapper_v4.h" 61 61 62 // =====[ DEBUG ]====================================63 64 #define ASSERT_VERBOSE65 #define ASSERT_NCYCLES m_cpt_total_cycles66 67 #include "debug.h"68 69 62 #if CC_XCACHE_WRAPPER_DEBUG 70 # define PRINTF(msg...) PRINTF_COND(m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN,msg)63 # define PRINTF(msg...) do { if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) printf(msg); } while (0); 71 64 #else 72 65 # define PRINTF(msg...) 73 66 #endif 74 67 75 // =====[ FIFO_RSP ]================================= 76 77 #if (CC_XCACHE_WRAPPER_FIFO_RSP==1) 78 # define CACHE_MISS_BUF_ALLOC do { \ 79 r_icache_miss_buf = new std::queue<data_t> [m_nb_icache]; \ 80 r_dcache_miss_buf = new std::queue<data_t> [m_nb_dcache]; \ 81 } while (0) 82 # define CACHE_MISS_BUF_DEALLOC do { \ 83 delete [] r_icache_miss_buf; \ 84 delete [] r_dcache_miss_buf; \ 85 } while (0) 86 # define CACHE_MISS_BUF_RESET(c) do { \ 87 for (uint32_t x=0; x<m_nb_##c##cache; ++x) { \ 88 while (r_##c##cache_miss_buf[x].size()>0) { \ 89 r_##c##cache_miss_buf[x].pop(); \ 90 } \ 91 } \ 92 } while (0) 93 # define CACHE_MISS_BUF_REQ_INIT(c,x) 94 # define CACHE_MISS_BUF_RSP_VAL(c,x,n) (r_##c##cache_miss_buf[x].size()>0) 95 # define CACHE_MISS_BUF_RSP_ACK(c,x) (r_##c##cache_miss_buf[x].size()<2) 96 # define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf[x].front() 97 # define CACHE_MISS_BUF_RSP_POP(c,x) do { \ 98 r_##c##cache_miss_buf[x].pop(); \ 99 } while (0) 100 # define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ 101 r_##c##cache_miss_buf[x].push(d); \ 102 } while (0) 103 # define CACHE_MISS_BUF_RSP_PRINT(c) do { \ 104 for (uint32_t x=0; x<m_nb_##c##cache; ++x) { \ 105 PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf[x].size()); \ 106 } \ 107 } while (0) 108 #elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) 109 # define CACHE_MISS_BUF_ALLOC 110 # define CACHE_MISS_BUF_DEALLOC 111 # define CACHE_MISS_BUF_RESET(c) do { \ 112 while (r_##c##cache_miss_buf.size()>0) { \ 113 r_##c##cache_miss_buf.pop(); \ 114 } \ 115 } while (0) 116 # define CACHE_MISS_BUF_REQ_INIT(c,x) 117 # define CACHE_MISS_BUF_RSP_VAL(c,x,n) ((r_##c##cache_miss_buf.size()>0) and (r_##c##cache_miss_buf.front().num_cache==x)) 118 # define CACHE_MISS_BUF_RSP_ACK(c,x) (r_##c##cache_miss_buf.size()<2) 119 # define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf.front().data 120 # define CACHE_MISS_BUF_RSP_POP(c,x) do { \ 121 r_##c##cache_miss_buf.pop(); \ 122 } while (0) 123 # define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ 124 miss_buf_t miss_buf; \ 125 miss_buf.data = d; \ 126 miss_buf.num_cache = x; \ 127 r_##c##cache_miss_buf.push(miss_buf); \ 128 } while (0) 129 # define CACHE_MISS_BUF_RSP_PRINT(c) do { \ 130 PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size()); \ 131 } while (0) 132 #else 133 # define CACHE_MISS_BUF_ALLOC do { \ 134 r_icache_miss_val = new bool * [m_nb_icache]; \ 135 r_icache_miss_buf = new data_t * [m_nb_icache]; \ 136 for (uint32_t x=0; x<m_nb_icache;++x) { \ 137 r_icache_miss_val [x] = new bool [m_icache_words]; \ 138 r_icache_miss_buf [x] = new data_t [m_icache_words]; \ 139 } \ 140 r_dcache_miss_val = new bool * [m_nb_dcache]; \ 141 r_dcache_miss_buf = new data_t * [m_nb_dcache]; \ 142 for (uint32_t x=0; x<m_nb_dcache;++x) { \ 143 r_dcache_miss_val [x] = new bool [m_dcache_words]; \ 144 r_dcache_miss_buf [x] = new data_t [m_dcache_words]; \ 145 } \ 146 } while (0) 147 # define CACHE_MISS_BUF_DEALLOC do { \ 148 for (uint32_t x=0; x<m_nb_icache;++x) { \ 149 delete [] r_icache_miss_val[x]; \ 150 delete [] r_icache_miss_buf[x]; \ 151 } \ 152 delete [] r_icache_miss_val; \ 153 delete [] r_icache_miss_buf; \ 154 for (uint32_t x=0; x<m_nb_dcache;++x) { \ 155 delete [] r_dcache_miss_val[x]; \ 156 delete [] r_dcache_miss_buf[x]; \ 157 } \ 158 delete [] r_dcache_miss_val; \ 159 delete [] r_dcache_miss_buf; \ 160 } while (0) 161 # define CACHE_MISS_BUF_RESET(c) 162 # define CACHE_MISS_BUF_REQ_INIT(c,x) do { \ 163 for (uint32_t i=0; i<m_##c##cache_words;++i) \ 164 r_##c##cache_miss_val[x][i] = false; \ 165 } while (0) 166 # define CACHE_MISS_BUF_RSP_VAL(c,x,n) r_##c##cache_miss_val[x][n] 167 # define CACHE_MISS_BUF_RSP_ACK(c,x) true 168 # define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf[x][n] 169 # define CACHE_MISS_BUF_RSP_POP(c,x) 170 # define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ 171 r_##c##cache_miss_val[x][n] = true; \ 172 r_##c##cache_miss_buf[x][n] = d; \ 173 } while (0) 174 # define CACHE_MISS_BUF_RSP_PRINT(c) do { \ 175 for (uint32_t x=0; x<m_nb_##c##cache;++x) \ 176 for (uint32_t i=0; i<m_##c##cache_words;++i) \ 177 PRINTF("%d %x |",r_##c##cache_miss_val[x][i],r_##c##cache_miss_buf[x][i]); PRINTF("\n"); \ 178 } while (0) 179 #endif 180 181 // =====[ MULTI_CACHE ]============================== 182 183 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 184 # define get_num_icache( addr,num_cpu) get_num_cache (addr) 185 # define get_num_icache_only(addr,num_cpu) get_num_cache_only(addr) 186 # define set_num_icache( addr,num_cache) set_num_cache (addr,num_cache) 187 # define set_num_icache_only(addr,num_cache) set_num_cache_only(addr,num_cache) 188 # define get_num_dcache( addr) get_num_cache (addr) 189 # define get_num_dcache_only(addr) get_num_cache_only(addr) 190 # define set_num_dcache( addr,num_cache) set_num_cache (addr,num_cache) 191 # define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache) 192 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 193 # define get_num_icache( addr,num_cpu) num_cpu 194 # define get_num_icache_only(addr,num_cpu) num_cpu 195 # define set_num_icache( addr,num_cache) do {} while (0) 196 # define set_num_icache_only(addr,num_cache) addr 197 # define get_num_dcache( addr) get_num_cache (addr) 198 # define get_num_dcache_only(addr) get_num_cache_only(addr) 199 # define set_num_dcache( addr,num_cache) set_num_cache (addr,num_cache) 200 # define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache) 68 # define ASSERT(cond,msg) assert ((cond) and msg); 69 70 #if CC_XCACHE_WRAPPER_FIFO_RSP 71 # define CACHE_MISS_BUF_ALLOC 72 # define CACHE_MISS_BUF_DEALLOC 73 # define CACHE_MISS_BUF_RESET(c) while (r_##c##cache_miss_buf.size()>0) {r_##c##cache_miss_buf.pop();} 74 # define CACHE_MISS_BUF_REQ_INIT(c) 75 # define CACHE_MISS_BUF_RSP_VAL(c,n) (r_##c##cache_miss_buf.size()>0) 76 # define CACHE_MISS_BUF_RSP_ACK(c) (r_##c##cache_miss_buf.size()<2) 77 # define CACHE_MISS_BUF_RSP_DATA(c,n) r_##c##cache_miss_buf.front() 78 # define CACHE_MISS_BUF_RSP_POP(c) do { r_##c##cache_miss_buf.pop();} while (0) 79 # define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do { r_##c##cache_miss_buf.push(d);} while (0) 80 # define CACHE_MISS_BUF_RSP_PRINT(c) do { PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size());} while (0) 201 81 #else 202 #error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE" 82 # define CACHE_MISS_BUF_ALLOC do { \ 83 r_icache_miss_val = new bool [m_icache_words]; \ 84 r_icache_miss_buf = new data_t[m_icache_words]; \ 85 r_dcache_miss_val = new bool [m_dcache_words]; \ 86 r_dcache_miss_buf = new data_t[m_dcache_words]; \ 87 } while (0) 88 # define CACHE_MISS_BUF_DEALLOC do { \ 89 delete [] r_icache_miss_val; \ 90 delete [] r_icache_miss_buf; \ 91 delete [] r_dcache_miss_val; \ 92 delete [] r_dcache_miss_buf; \ 93 } while (0) 94 # define CACHE_MISS_BUF_RESET(c) 95 # define CACHE_MISS_BUF_REQ_INIT(c) do {for (uint32_t i=0; i<m_##c##cache_words;++i) r_##c##cache_miss_val[i] = false;} while (0) 96 # define CACHE_MISS_BUF_RSP_VAL(c,n) r_##c##cache_miss_val[n] 97 # define CACHE_MISS_BUF_RSP_ACK(c) true 98 # define CACHE_MISS_BUF_RSP_DATA(c,n) r_##c##cache_miss_buf[n] 99 # define CACHE_MISS_BUF_RSP_POP(c) 100 # define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do {r_##c##cache_miss_val[n] = true; r_##c##cache_miss_buf[n] = d;} while (0) 101 # define CACHE_MISS_BUF_RSP_PRINT(c) do {for (uint32_t i=0; i<m_##c##cache_words;++i) PRINTF("%d %x |",r_##c##cache_miss_val[i],r_##c##cache_miss_buf[i]); PRINTF("\n");} while (0) 203 102 #endif 204 103 … … 210 109 "DCACHE_IDLE", 211 110 "DCACHE_WRITE_UPDT", 111 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 212 112 "DCACHE_MISS_VICTIM", 113 #endif 213 114 "DCACHE_MISS_WAIT", 214 115 "DCACHE_MISS_UPDT", … … 225 126 const char *icache_fsm_state_str[] = { 226 127 "ICACHE_IDLE", 128 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 227 129 "ICACHE_MISS_VICTIM", 130 #endif 228 131 "ICACHE_MISS_WAIT", 229 132 "ICACHE_MISS_UPDT", … … 267 170 const char *cleanup_fsm_state_str[] = { 268 171 "CLEANUP_IDLE", 269 "CLEANUP_REQ", 270 "CLEANUP_RSP_DCACHE", 271 "CLEANUP_RSP_ICACHE", 172 "CLEANUP_DCACHE", 173 "CLEANUP_ICACHE", 272 174 }; 273 175 } 274 275 typedef long long unsigned int blob_t;276 176 277 177 #define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXCacheWrapperV4<vci_param, iss_t> … … 289 189 const soclib::common::IntTab &initiator_index_c, 290 190 const soclib::common::IntTab &target_index, 291 size_t nb_cpu,292 size_t nb_dcache,293 191 size_t icache_ways, 294 192 size_t icache_sets, … … 312 210 m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()), 313 211 m_segment(mtc.getSegment(target_index)), 212 m_iss(this->name(), proc_id), 314 213 m_srcid_rw(mtp.indexForId(initiator_index_rw)), 315 214 m_srcid_c(mtc.indexForId(initiator_index_c)), 316 215 317 m_nb_cpu(nb_cpu),318 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1)319 m_nb_icache(nb_dcache),320 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)321 m_nb_icache(m_nb_cpu),322 #endif323 m_nb_dcache(nb_dcache),324 m_nb_cache((m_nb_dcache>m_nb_icache)?m_nb_dcache:m_nb_icache),325 216 m_dcache_ways(dcache_ways), 326 217 m_dcache_words(dcache_words), 327 m_dcache_words_shift(uint32_log2(dcache_words)+ uint32_log2(sizeof(data_t))),218 m_dcache_words_shift(uint32_log2(dcache_words)+2), 328 219 m_dcache_yzmask((~0)<<m_dcache_words_shift), 329 220 m_icache_ways(icache_ways), 330 221 m_icache_words(icache_words), 331 m_icache_words_shift(uint32_log2(icache_words)+ uint32_log2(sizeof(data_t))),222 m_icache_words_shift(uint32_log2(icache_words)+2), 332 223 m_icache_yzmask((~0)<<m_icache_words_shift), 333 224 m_cache_words((dcache_words)?dcache_words:icache_words), 334 225 335 r_cpu_prior("r_cpu_prior"), 226 r_dcache_fsm("r_dcache_fsm"), 227 r_dcache_fsm_save("r_dcache_fsm_save"), 228 r_dcache_addr_save("r_dcache_addr_save"), 229 r_dcache_wdata_save("r_dcache_wdata_save"), 230 r_dcache_rdata_save("r_dcache_rdata_save"), 231 r_dcache_type_save("r_dcache_type_save"), 232 r_dcache_be_save("r_dcache_be_save"), 233 r_dcache_cached_save("r_dcache_cached_save"), 234 r_dcache_cleanup_req("r_dcache_cleanup_req"), 235 r_dcache_cleanup_line("r_dcache_cleanup_line"), 236 r_dcache_miss_req("r_dcache_miss_req"), 237 r_dcache_miss_way("r_dcache_miss_way"), 238 r_dcache_miss_set("r_dcache_miss_set"), 239 r_dcache_unc_req("r_dcache_unc_req"), 240 r_dcache_sc_req("r_dcache_sc_req"), 241 r_dcache_inval_rsp("r_dcache_inval_rsp"), 242 r_dcache_update_addr("r_dcache_update_addr"), 243 r_dcache_ll_data("r_dcache_ll_data"), 244 r_dcache_ll_addr("r_dcache_ll_addr"), 245 r_dcache_ll_valid("r_dcache_ll_valid"), 246 r_dcache_previous_unc("r_dcache_previous_unc"), 247 248 r_icache_fsm("r_icache_fsm"), 249 r_icache_fsm_save("r_icache_fsm_save"), 250 r_icache_addr_save("r_icache_addr_save"), 251 r_icache_miss_req("r_icache_miss_req"), 252 r_icache_miss_way("r_icache_miss_way"), 253 r_icache_miss_set("r_icache_miss_set"), 254 r_icache_unc_req("r_icache_unc_req"), 255 r_icache_cleanup_req("r_icache_cleanup_req"), 256 r_icache_cleanup_line("r_icache_cleanup_line"), 257 r_icache_inval_rsp("r_icache_inval_rsp"), 258 r_icache_update_addr("r_icache_update_addr"), 336 259 337 260 r_vci_cmd_fsm("r_vci_cmd_fsm"), … … 340 263 r_vci_cmd_cpt("r_vci_cmd_cpt"), 341 264 r_vci_cmd_dcache_prior("r_vci_cmd_dcache_prior"), 342 r_vci_cmd_num_cache("r_vci_cmd_num_cache"),343 265 344 266 r_vci_rsp_fsm("r_vci_rsp_fsm"), 267 r_vci_rsp_ins_error("r_vci_rsp_ins_error"), 268 r_vci_rsp_data_error("r_vci_rsp_data_error"), 345 269 r_vci_rsp_cpt("r_vci_rsp_cpt"), 346 //s_vci_rsp_ack("s_vci_rsp_ack"), 347 r_vci_rsp_num_cache("r_vci_rsp_num_cache"), 270 r_vci_rsp_ack("r_vci_rsp_ack"), 271 272 r_icache_buf_unc_valid("r_icache_buf_unc_valid"), 348 273 349 274 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 352 277 353 278 r_vci_tgt_fsm("r_vci_tgt_fsm"), 354 r_tgt_iaddr("r_tgt_iaddr"), 355 r_tgt_daddr("r_tgt_daddr"), 279 r_tgt_addr("r_tgt_addr"), 356 280 r_tgt_word("r_tgt_word"), 357 281 r_tgt_update("r_tgt_update"), … … 362 286 r_tgt_trdid("r_tgt_trdid"), 363 287 // r_tgt_plen("r_tgt_plen"), 364 r_tgt_num_cache("r_tgt_num_cache"), 288 r_tgt_icache_req("r_tgt_icache_req"), 289 r_tgt_dcache_req("r_tgt_dcache_req"), 290 r_tgt_icache_rsp("r_tgt_icache_rsp"), 291 r_tgt_dcache_rsp("r_tgt_dcache_rsp"), 365 292 366 293 r_cleanup_fsm("r_cleanup_fsm"), 367 r_cleanup_num_cache("r_cleanup_num_cache"), 368 r_cleanup_icache("r_cleanup_icache"), 369 370 m_num_cache_LSB(uint32_log2(icache_words) + uint32_log2(sizeof(data_t))), 371 m_num_cache_MSB(uint32_log2(nb_dcache) + m_num_cache_LSB) 294 295 r_wbuf("r_wbuf", wbuf_nwords, wbuf_nlines, wbuf_timeout, dcache_words), 296 r_icache("icache", icache_ways, icache_sets, icache_words), 297 r_dcache("dcache", dcache_ways, dcache_sets, dcache_words) 372 298 { 373 299 // Size of word is 32 bits 374 ASSERT((icache_words*vci_param::B) < (1<<vci_param::K), 375 "Need more PLEN bits."); 376 377 ASSERT((vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines/m_nb_dcache)), 378 "Need more TRDID bits."); 379 380 ASSERT(uint32_log2(nb_dcache) <= (1<<vci_param::P), 381 "Need more PKTID bits."); 382 383 ASSERT(IS_POW_OF_2(m_nb_dcache), 384 "nb_dcache must be a power of 2."); 385 386 ASSERT(IS_POW_OF_2(m_nb_cpu) and (m_nb_cpu <= m_nb_dcache) and (m_nb_cpu > 0), 387 "nb cpu must be a multiple of nb cache."); 388 389 ASSERT(IS_POW_OF_2(m_icache_ways) and (m_nb_icache <= m_icache_ways), 390 "nb icache ways must be a multiple of nb cache."); 391 392 ASSERT(IS_POW_OF_2(m_dcache_ways) and (m_nb_dcache <= m_dcache_ways), 393 "nb dcache ways must be a multiple of nb cache."); 394 395 ASSERT(icache_words == dcache_words, 396 "icache_words must be equal at dcache_words."); 397 398 ASSERT(IS_POW_OF_2(wbuf_nlines) and (m_nb_dcache <= wbuf_nlines), 399 "wbuf_nlines must be a multiple of nb cache."); 400 401 // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE 402 ASSERT((m_nb_dcache == 1) or (dcache_words >= 16), 403 "When multi cache is activated, need 4 bits (16 word) to the cache set ."); 404 405 if (m_nb_cpu > 1) 406 ASSERT(CC_XCACHE_MULTI_CPU!=0, 407 "Macro CC_XCACHE_MULTI_CPU in wbuf must be set at 1."); 408 409 p_irq = new sc_in<bool> * [m_nb_cpu]; 410 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 411 p_irq [num_cpu] = new sc_in<bool> [iss_t::n_irq]; 412 413 m_iss = new iss_t * [m_nb_cpu]; 414 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 415 { 416 std::ostringstream iss_name(""); 417 iss_name << this->name() << "_" << num_cpu; 418 419 m_iss[num_cpu] = new iss_t (iss_name.str().c_str(), proc_id+num_cpu); 420 } 421 300 ASSERT( (icache_words*vci_param::B) < (1<<vci_param::K), 301 "I need more PLEN bits"); 302 303 ASSERT( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= wbuf_nlines), 304 "I need more TRDID bits"); 305 422 306 CACHE_MISS_BUF_ALLOC; 423 307 424 r_icache_lock = new sc_signal<uint32_t>[m_nb_icache]; 425 r_dcache_lock = new sc_signal<uint32_t>[m_nb_dcache]; 426 r_dcache_sync = new sc_signal<bool> [m_nb_dcache]; 427 428 r_icache_fsm = new sc_signal<int> [m_nb_icache]; 429 r_icache_fsm_save = new sc_signal<int> [m_nb_icache]; 430 r_icache_addr_save = new sc_signal<addr_40> [m_nb_icache]; 431 r_icache_miss_req = new sc_signal<bool> [m_nb_icache]; 432 r_icache_miss_way = new sc_signal<size_t> [m_nb_icache]; 433 r_icache_miss_set = new sc_signal<size_t> [m_nb_icache]; 434 r_icache_unc_req = new sc_signal<bool> [m_nb_icache]; 435 r_icache_cleanup_req = new sc_signal<bool> [m_nb_icache]; 436 r_icache_cleanup_line = new sc_signal<addr_40> [m_nb_icache]; 437 r_icache_inval_rsp = new sc_signal<bool> [m_nb_icache]; 438 r_icache_update_addr = new sc_signal<size_t> [m_nb_icache]; 439 r_icache_buf_unc_valid = new sc_signal<bool> [m_nb_icache]; 440 441 r_dcache_fsm = new sc_signal<int> [m_nb_dcache]; 442 r_dcache_fsm_save = new sc_signal<int> [m_nb_dcache]; 443 r_dcache_addr_save = new sc_signal<addr_40> [m_nb_dcache]; 444 r_dcache_wdata_save = new sc_signal<data_t> [m_nb_dcache]; 445 r_dcache_rdata_save = new sc_signal<data_t> [m_nb_dcache]; 446 r_dcache_type_save = new sc_signal<int> [m_nb_dcache]; 447 r_dcache_be_save = new sc_signal<be_t> [m_nb_dcache]; 448 r_dcache_cached_save = new sc_signal<bool> [m_nb_dcache]; 449 r_dcache_cleanup_req = new sc_signal<bool> [m_nb_dcache]; 450 r_dcache_cleanup_line = new sc_signal<addr_40> [m_nb_dcache]; 451 r_dcache_miss_req = new sc_signal<bool> [m_nb_dcache]; 452 r_dcache_miss_way = new sc_signal<size_t> [m_nb_dcache]; 453 r_dcache_miss_set = new sc_signal<size_t> [m_nb_dcache]; 454 r_dcache_unc_req = new sc_signal<bool> [m_nb_dcache]; 455 r_dcache_sc_req = new sc_signal<bool> [m_nb_dcache]; 456 r_dcache_inval_rsp = new sc_signal<bool> [m_nb_dcache]; 457 r_dcache_update_addr = new sc_signal<size_t> [m_nb_dcache]; 458 r_dcache_previous_unc = new sc_signal<bool> [m_nb_dcache]; 459 460 r_dcache_num_cpu_save = new sc_signal<uint32_t> [m_nb_dcache]; 461 r_dcache_ll_data = new sc_signal<data_64> * [m_nb_dcache]; 462 r_dcache_ll_addr = new sc_signal<addr_40> * [m_nb_dcache]; 463 r_dcache_ll_valid = new sc_signal<bool> * [m_nb_dcache]; 464 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 465 { 466 r_dcache_ll_data [num_cache] = new sc_signal<data_64> [m_nb_cpu]; 467 r_dcache_ll_addr [num_cache] = new sc_signal<addr_40> [m_nb_cpu]; 468 r_dcache_ll_valid [num_cache] = new sc_signal<bool> [m_nb_cpu]; 469 } 470 471 r_tgt_icache_req = new sc_signal<bool> [m_nb_icache]; 472 r_tgt_icache_rsp = new sc_signal<bool> [m_nb_icache]; 473 r_tgt_dcache_req = new sc_signal<bool> [m_nb_dcache]; 474 r_tgt_dcache_rsp = new sc_signal<bool> [m_nb_dcache]; 475 476 r_tgt_buf = new data_t [m_cache_words]; 477 r_tgt_be = new be_t [m_cache_words]; 478 479 r_vci_rsp_ins_error = new sc_signal<bool> [m_nb_icache]; 480 r_vci_rsp_data_error = new sc_signal<bool> [m_nb_dcache]; 481 482 ireq = new typename iss_t::InstructionRequest [m_nb_icache]; 483 irsp = new typename iss_t::InstructionResponse [m_nb_icache]; 484 ireq_cached = new bool [m_nb_icache]; 485 ireq_num_cpu = new uint32_t [m_nb_dcache]; 486 487 dreq = new typename iss_t::DataRequest [m_nb_dcache]; 488 drsp = new typename iss_t::DataResponse [m_nb_dcache]; 489 dreq_cached = new bool [m_nb_dcache]; 490 dreq_num_cpu = new uint32_t [m_nb_dcache]; 491 492 m_cpt_icache_access = new uint32_t [m_nb_icache]; 493 m_cpt_dcache_access = new uint32_t [m_nb_dcache]; 494 m_cpt_icache_miss_victim_wait = new uint32_t [m_nb_icache]; 495 m_cpt_dcache_miss_victim_wait = new uint32_t [m_nb_dcache]; 496 497 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE 498 m_cpt_dcache_store_after_store = new uint32_t [m_nb_dcache]; 499 #endif 500 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 501 m_cpt_dcache_hit_after_miss_read = new uint32_t [m_nb_dcache]; 502 m_cpt_dcache_hit_after_miss_write = new uint32_t [m_nb_dcache]; 503 #endif 504 505 m_cpt_fsm_dcache = new uint32_t * [m_nb_dcache]; 506 m_cpt_fsm_icache = new uint32_t * [m_nb_icache]; 507 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 508 m_cpt_fsm_dcache[num_cache] = new uint32_t [soclib::common::size(dcache_fsm_state_str )]; 509 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 510 m_cpt_fsm_icache[num_cache] = new uint32_t [soclib::common::size(icache_fsm_state_str )]; 511 m_cpt_fsm_cmd = new uint32_t [soclib::common::size(cmd_fsm_state_str )]; 512 m_cpt_fsm_rsp = new uint32_t [soclib::common::size(rsp_fsm_state_str )]; 513 m_cpt_fsm_tgt = new uint32_t [soclib::common::size(tgt_fsm_state_str )]; 514 m_cpt_fsm_cleanup = new uint32_t [soclib::common::size(cleanup_fsm_state_str)]; 515 516 m_cpt_frz_cycles = new uint32_t [m_nb_cpu]; 517 // r_icache_fsm("r_icache_fsm"), 518 // r_icache_fsm_save("r_icache_fsm_save"), 519 // r_icache_addr_save("r_icache_addr_save"), 520 // r_icache_miss_req("r_icache_miss_req"), 521 // r_icache_miss_way("r_icache_miss_way"), 522 // r_icache_miss_set("r_icache_miss_set"), 523 // r_icache_unc_req("r_icache_unc_req"), 524 // r_icache_cleanup_req("r_icache_cleanup_req"), 525 // r_icache_cleanup_line("r_icache_cleanup_line"), 526 // r_icache_inval_rsp("r_icache_inval_rsp"), 527 // r_icache_update_addr("r_icache_update_addr"), 528 // r_icache_buf_unc_valid("r_icache_buf_unc_valid"), 529 530 // r_dcache_fsm("r_dcache_fsm"), 531 // r_dcache_fsm_save("r_dcache_fsm_save"), 532 // r_dcache_addr_save("r_dcache_addr_save"), 533 // r_dcache_wdata_save("r_dcache_wdata_save"), 534 // r_dcache_rdata_save("r_dcache_rdata_save"), 535 // r_dcache_type_save("r_dcache_type_save"), 536 // r_dcache_be_save("r_dcache_be_save"), 537 // r_dcache_cached_save("r_dcache_cached_save"), 538 // r_dcache_cleanup_req("r_dcache_cleanup_req"), 539 // r_dcache_cleanup_line("r_dcache_cleanup_line"), 540 // r_dcache_miss_req("r_dcache_miss_req"), 541 // r_dcache_miss_way("r_dcache_miss_way"), 542 // r_dcache_miss_set("r_dcache_miss_set"), 543 // r_dcache_unc_req("r_dcache_unc_req"), 544 // r_dcache_sc_req("r_dcache_sc_req"), 545 // r_dcache_inval_rsp("r_dcache_inval_rsp"), 546 // r_dcache_update_addr("r_dcache_update_addr"), 547 // r_dcache_ll_data("r_dcache_ll_data"), 548 // r_dcache_ll_addr("r_dcache_ll_addr"), 549 // r_dcache_ll_valid("r_dcache_ll_valid"), 550 // r_dcache_previous_unc("r_dcache_previous_unc"), 551 552 // r_tgt_icache_req("r_tgt_icache_req"), 553 // r_tgt_icache_rsp("r_tgt_icache_rsp"), 554 555 // r_tgt_dcache_req("r_tgt_dcache_req"), 556 // r_tgt_dcache_rsp("r_tgt_dcache_rsp"), 557 558 // r_vci_rsp_ins_error("r_vci_rsp_ins_error"), 559 // r_vci_rsp_data_error("r_vci_rsp_data_error"), 560 561 size_t _icache_ways = icache_ways /m_nb_icache; 562 size_t _icache_sets = icache_sets ; 563 size_t _dcache_ways = dcache_ways /m_nb_dcache; 564 size_t _dcache_sets = dcache_sets ; 565 size_t _icache_words = icache_words; 566 size_t _dcache_words = dcache_words; 567 568 size_t _wbuf_nwords = wbuf_nwords ; 569 size_t _wbuf_nlines = wbuf_nlines /m_nb_dcache; 570 size_t _wbuf_timeout = wbuf_timeout; 571 572 573 #if CC_XCACHE_WRAPPER_VERBOSE 574 std::cout << "<VciCcXCacheWrapperV4> Parameters :" << std::endl; 575 std::cout << " * nb_cpu : " << nb_cpu << std::endl; 576 std::cout << " * nb_cache : " << m_nb_icache << " icache(s), " << m_nb_dcache << " dcache(s)" << std::endl; 577 std::cout << " * icache (total) : " << icache_ways << " way(s), " << icache_sets << " set(s), " << icache_words << " word(s)" << std::endl; 578 std::cout << " * icache (per cache) : " << _icache_ways << " way(s), " << _icache_sets << " set(s), " << _icache_words << " word(s)" << std::endl; 579 std::cout << " * dcache (total) : " << dcache_ways << " way(s), " << dcache_sets << " set(s), " << dcache_words << " word(s)" << std::endl; 580 std::cout << " * dcache (per cache) : " << _dcache_ways << " way(s), " << _dcache_sets << " set(s), " << _dcache_words << " word(s)" << std::endl; 581 std::cout << " * wbuf (total) : " << wbuf_nlines << " line(s), " << wbuf_nwords << " word(s), timeout : " << wbuf_timeout << std::endl; 582 std::cout << " * wbuf (per cache) : " << _wbuf_nlines << " line(s), " << _wbuf_nwords << " word(s), timeout : " << _wbuf_timeout << std::endl; 583 #endif 584 585 r_icache = new GenericCache<vci_addr_t> * [m_nb_icache]; 586 r_dcache = new GenericCache<vci_addr_t> * [m_nb_dcache]; 587 r_wbuf = new MultiWriteBuffer<addr_40> * [m_nb_dcache]; 588 589 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 590 { 591 r_icache [num_cache] = new GenericCache<vci_addr_t> ("icache", _icache_ways, _icache_sets, _icache_words); 592 } 593 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 594 { 595 r_dcache [num_cache] = new GenericCache<vci_addr_t> ("dcache", _dcache_ways, _dcache_sets, _dcache_words); 596 r_wbuf [num_cache] = new MultiWriteBuffer<addr_40> ("r_wbuf", _wbuf_nwords, _wbuf_nlines, _wbuf_timeout, _dcache_words); 597 } 598 599 m_num_cache_LSB_mask = 0; 600 for (uint32_t i=0; i<m_num_cache_LSB; ++i) 601 { 602 m_num_cache_LSB_mask <<= 1; 603 m_num_cache_LSB_mask |= 1; 604 } 605 m_num_cache_mask = 0; 606 for (uint32_t i=0; i<(m_num_cache_MSB-m_num_cache_LSB); ++i) 607 { 608 m_num_cache_mask <<= 1; 609 m_num_cache_mask |= 1; 610 } 308 r_tgt_buf = new data_t[m_cache_words]; 309 r_tgt_be = new be_t [m_cache_words]; 611 310 612 311 SC_METHOD(transition); … … 617 316 dont_initialize(); 618 317 sensitive << p_clk.neg(); 318 619 319 620 320 typename iss_t::CacheInfo cache_info; … … 626 326 cache_info.dcache_assoc = dcache_ways; 627 327 cache_info.dcache_n_lines = dcache_sets; 628 629 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 630 m_iss[num_cpu]->setCacheInfo(cache_info); 631 328 m_iss.setCacheInfo(cache_info); 329 632 330 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 633 331 m_stop_simulation = false; 634 m_stop_simulation_nb_frz_cycles = new uint32_t [m_nb_cpu]; 635 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 636 m_stop_simulation_nb_frz_cycles [num_cpu] = 0; 332 m_stop_simulation_nb_frz_cycles = 0; 637 333 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 638 334 639 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 640 log_transaction_file_icache = new std::ofstream [m_nb_cpu]; 641 log_transaction_file_dcache = new std::ofstream [m_nb_cpu]; 642 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 643 { 644 { 645 std::ostringstream filename(""); 646 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_icache-" << proc_id << "_" << num_cpu << ".log"; 647 log_transaction_file_icache[num_cpu].open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 648 } 649 { 650 std::ostringstream filename(""); 651 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_dcache-" << proc_id << "_" << num_cpu << ".log"; 652 log_transaction_file_dcache[num_cpu].open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 653 } 654 } 655 656 { 657 std::ostringstream filename(""); 658 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_cmd-" << proc_id << ".log"; 659 log_transaction_file_cmd.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 660 } 661 { 662 std::ostringstream filename(""); 663 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_tgt-" << proc_id << ".log"; 664 log_transaction_file_tgt.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 665 } 666 { 667 std::ostringstream filename(""); 668 filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_cleanup-" << proc_id << ".log"; 669 log_transaction_file_cleanup.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 670 } 335 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 336 std::ostringstream filename(""); 337 filename << "Instruction_flow_" << proc_id << ".log"; 338 339 log_dcache_transaction_file.open(filename.str().c_str() ,std::ios::out | std::ios::trunc); 671 340 #endif 672 341 } // end constructor … … 676 345 /////////////////////////////////// 677 346 { 678 delete [] m_stop_simulation_nb_frz_cycles; 679 680 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 681 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 682 { 683 log_transaction_file_dcache[num_cpu].close(); 684 log_transaction_file_icache[num_cpu].close(); 685 } 686 delete [] log_transaction_file_dcache; 687 delete [] log_transaction_file_icache; 688 689 log_transaction_file_cmd .close(); 690 log_transaction_file_tgt .close(); 691 log_transaction_file_cleanup.close(); 692 #endif 693 694 delete [] r_icache_lock ; 695 delete [] r_dcache_lock ; 696 delete [] r_dcache_sync ; 697 698 delete [] r_icache_fsm ; 699 delete [] r_icache_fsm_save ; 700 delete [] r_icache_addr_save ; 701 delete [] r_icache_miss_req ; 702 delete [] r_icache_miss_way ; 703 delete [] r_icache_miss_set ; 704 delete [] r_icache_unc_req ; 705 delete [] r_icache_cleanup_req ; 706 delete [] r_icache_cleanup_line ; 707 delete [] r_icache_inval_rsp ; 708 delete [] r_icache_update_addr ; 709 delete [] r_icache_buf_unc_valid; 710 711 delete [] r_dcache_fsm ; 712 delete [] r_dcache_fsm_save ; 713 delete [] r_dcache_addr_save ; 714 delete [] r_dcache_wdata_save ; 715 delete [] r_dcache_rdata_save ; 716 delete [] r_dcache_type_save ; 717 delete [] r_dcache_be_save ; 718 delete [] r_dcache_cached_save ; 719 delete [] r_dcache_cleanup_req ; 720 delete [] r_dcache_cleanup_line ; 721 delete [] r_dcache_miss_req ; 722 delete [] r_dcache_miss_way ; 723 delete [] r_dcache_miss_set ; 724 delete [] r_dcache_unc_req ; 725 delete [] r_dcache_sc_req ; 726 delete [] r_dcache_inval_rsp ; 727 delete [] r_dcache_update_addr ; 728 delete [] r_dcache_previous_unc ; 729 730 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 731 { 732 delete [] r_dcache_ll_data [num_cache]; 733 delete [] r_dcache_ll_addr [num_cache]; 734 delete [] r_dcache_ll_valid [num_cache]; 735 } 736 delete [] r_dcache_num_cpu_save ; 737 delete [] r_dcache_ll_data ; 738 delete [] r_dcache_ll_addr ; 739 delete [] r_dcache_ll_valid ; 740 741 delete [] r_tgt_icache_req ; 742 delete [] r_tgt_icache_rsp ; 743 delete [] r_tgt_dcache_req ; 744 delete [] r_tgt_dcache_rsp ; 745 347 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 348 log_dcache_transaction_file.close(); 349 #endif 350 351 delete [] r_tgt_buf; 746 352 delete [] r_tgt_be ; 747 delete [] r_tgt_buf;748 749 delete [] r_vci_rsp_ins_error ;750 delete [] r_vci_rsp_data_error ;751 752 delete [] ireq ;753 delete [] irsp ;754 delete [] ireq_cached ;755 delete [] ireq_num_cpu ;756 delete [] dreq ;757 delete [] drsp ;758 delete [] dreq_cached ;759 delete [] dreq_num_cpu ;760 761 delete [] m_cpt_frz_cycles;762 763 delete [] m_cpt_icache_access ;764 delete [] m_cpt_dcache_access ;765 delete [] m_cpt_icache_miss_victim_wait;766 delete [] m_cpt_dcache_miss_victim_wait;767 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE768 delete [] m_cpt_dcache_store_after_store;769 #endif770 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS771 delete [] m_cpt_dcache_hit_after_miss_read;772 delete [] m_cpt_dcache_hit_after_miss_write;773 #endif774 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)775 delete [] m_cpt_fsm_dcache [num_cache];776 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)777 delete [] m_cpt_fsm_icache [num_cache];778 779 delete [] m_cpt_fsm_dcache ;780 delete [] m_cpt_fsm_icache ;781 delete [] m_cpt_fsm_cmd ;782 delete [] m_cpt_fsm_rsp ;783 delete [] m_cpt_fsm_tgt ;784 delete [] m_cpt_fsm_cleanup;785 786 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)787 {788 delete r_icache [num_cache];789 }790 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)791 {792 delete r_wbuf [num_cache];793 delete r_dcache [num_cache];794 }795 delete [] r_wbuf;796 delete [] r_icache;797 delete [] r_dcache;798 799 353 800 354 CACHE_MISS_BUF_DEALLOC; 801 802 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)803 {804 delete m_iss [num_cpu];805 delete [] p_irq [num_cpu];806 }807 delete [] m_iss;808 delete [] p_irq;809 355 } 810 356 … … 813 359 //////////////////////// 814 360 { 815 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)816 361 std::cout << "CPU " << m_srcid_rw << " : CPI = " 817 << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles[num_cpu]) << std::endl ;362 << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ; 818 363 } 819 364 //////////////////////// 820 tmpl(void)::print_stats(bool print_wbuf, bool print_fsm)365 tmpl(void)::print_stats() 821 366 //////////////////////// 822 367 { 368 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); 369 823 370 uint32_t m_cpt_data_read_cached = m_cpt_data_read-m_cpt_data_read_uncached; 824 371 uint32_t m_cpt_data_write_cached = m_cpt_data_write-m_cpt_data_write_uncached; 825 372 std::cout << "------------------------------------" << std:: dec << std::endl; 826 373 std::cout << "CPU " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl; 827 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 828 { 829 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles[num_cpu]); 830 831 std::cout << "- CPI : [" << num_cpu << "] "<< (float)m_cpt_total_cycles/run_cycles << std::endl ; 832 std::cout << "- IPC : [" << num_cpu << "] "<< (float)run_cycles/m_cpt_total_cycles << std::endl ; 833 } 374 std::cout << "- CPI : " << (float)m_cpt_total_cycles/run_cycles << std::endl ; 375 std::cout << "- IPC : " << (float)run_cycles/m_cpt_total_cycles << std::endl ; 834 376 std::cout << "- DATA READ * : " << m_cpt_data_read << std::endl ; 835 377 std::cout << " + Uncached : " << m_cpt_data_read_uncached << " (" << (float)m_cpt_data_read_uncached*100.0/(float)m_cpt_data_read << "%)" << std::endl ; … … 862 404 std::cout << " + DCACHE Only : " << (float)m_cpt_cc_inval_dcache *100.0/(float)m_cpt_cc_inval << "%" << std::endl; 863 405 std::cout << " + BROADCAST : " << (float)m_cpt_cc_inval_broadcast*100.0/(float)m_cpt_cc_inval << "%" << std::endl; 864 865 uint32_t m_cpt_icache_access_all = 0;866 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)867 m_cpt_icache_access_all += m_cpt_icache_access [num_cache];868 869 std::cout << "- ICACHE ACCESS : " << m_cpt_icache_access_all << std::endl;870 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)871 std::cout << " + [" << num_cache << "] : " << m_cpt_icache_access [num_cache] << " (" << (float)m_cpt_icache_access [num_cache]*100.0/(float)m_cpt_icache_access_all << "%)" << std::endl;872 873 uint32_t m_cpt_dcache_access_all = 0;874 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)875 m_cpt_dcache_access_all += m_cpt_dcache_access [num_cache];876 877 std::cout << "- DCACHE ACCESS : " << m_cpt_dcache_access_all << std::endl;878 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)879 {880 std::cout << " + [" << num_cache << "] : " << m_cpt_dcache_access [num_cache] << " (" << (float)m_cpt_dcache_access [num_cache]*100.0/(float)m_cpt_dcache_access_all << "%)";881 882 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE883 std::cout << " - store after store : " << m_cpt_dcache_store_after_store [num_cache];884 #endif885 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS886 std::cout << " - Hit after Miss : Read " << m_cpt_dcache_hit_after_miss_read [num_cache] << ", Write " << m_cpt_dcache_hit_after_miss_write [num_cache];887 #endif888 std::cout << std::endl;889 }890 891 uint32_t m_cpt_icache_miss_victim_wait_all = 0;892 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)893 m_cpt_icache_miss_victim_wait_all += m_cpt_icache_miss_victim_wait [num_cache];894 std::cout << "- ICACHE MISS VICTIM WAIT : " << m_cpt_icache_miss_victim_wait_all << std::endl;895 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)896 std::cout << " + [" << num_cache << "] : " << m_cpt_icache_miss_victim_wait [num_cache] << std::endl;897 898 uint32_t m_cpt_dcache_miss_victim_wait_all = 0;899 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)900 m_cpt_dcache_miss_victim_wait_all += m_cpt_dcache_miss_victim_wait [num_cache];901 std::cout << "- DCACHE MISS VICTIM WAIT : " << m_cpt_dcache_miss_victim_wait_all << std::endl;902 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)903 std::cout << " + [" << num_cache << "] : " << m_cpt_dcache_miss_victim_wait [num_cache] << std::endl;904 905 if (print_fsm)906 {907 std::cout << "- DCACHE FSM" << std::endl;908 for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i)909 {910 std::cout << " + " << dcache_fsm_state_str[i] << " :\t ";911 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)912 std::cout << m_cpt_fsm_dcache [num_cache][i] << ", ";913 std::cout << std::endl;914 }915 std::cout << "- ICACHE FSM" << std::endl;916 for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i)917 {918 std::cout << " + " << icache_fsm_state_str[i] << " :\t ";919 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)920 std::cout << m_cpt_fsm_icache [num_cache][i] << ", ";921 std::cout << std::endl;922 }923 std::cout << "- CMD FSM" << std::endl;924 for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str ); ++i)925 std::cout << " + " << cmd_fsm_state_str[i] << " :\t " << m_cpt_fsm_cmd [i] << std::endl;926 std::cout << "- RSP FSM" << std::endl;927 for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str ); ++i)928 std::cout << " + " << rsp_fsm_state_str[i] << " :\t " << m_cpt_fsm_rsp [i] << std::endl;929 std::cout << "- TGT FSM" << std::endl;930 for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str ); ++i)931 std::cout << " + " << tgt_fsm_state_str[i] << " :\t " << m_cpt_fsm_tgt [i] << std::endl;932 std::cout << "- CLEANUP FSM" << std::endl;933 for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str ); ++i)934 std::cout << " + " << cleanup_fsm_state_str[i] << " :\t " << m_cpt_fsm_cleanup [i] << std::endl;935 }936 937 406 std::cout << "* : accepted or not by the cache" << std::endl ; 938 407 939 if (print_wbuf) 940 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 941 r_wbuf[num_cache]->printStatistics(); 408 r_wbuf.printStatistics(); 942 409 } 943 410 … … 954 421 typename iss_t::DataRequest dreq; 955 422 423 m_iss.getRequests( ireq, dreq ); 956 424 std::cout << std::dec << "Proc \"" << name() << "\"" << std::endl; 957 958 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 959 { 960 m_iss[num_cpu]->getRequests( ireq, dreq ); 961 std::cout << ireq << std::endl; 962 std::cout << dreq << std::endl; 963 } 964 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 965 std::cout << " " << icache_fsm_state_str[r_icache_fsm[num_cache]] << std::endl; 966 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 967 std::cout << " " << dcache_fsm_state_str[r_dcache_fsm[num_cache]] << std::endl; 968 969 std::cout << " " << cmd_fsm_state_str[r_vci_cmd_fsm] 425 std::cout << ireq << std::endl; 426 std::cout << dreq << std::endl; 427 std::cout << " " << dcache_fsm_state_str[r_dcache_fsm] 428 << " " << icache_fsm_state_str[r_icache_fsm] 429 << " " << cmd_fsm_state_str[r_vci_cmd_fsm] 970 430 << " " << rsp_fsm_state_str[r_vci_rsp_fsm] 971 431 << " " << tgt_fsm_state_str[r_vci_tgt_fsm] … … 974 434 if(mode & 0x1) 975 435 { 976 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 977 r_wbuf[num_cache]->printTrace((mode>>1)&1); 436 r_wbuf.printTrace((mode>>1)&1); 978 437 } 979 438 if(mode & 0x4) 980 439 { 981 440 std::cout << " Data cache" << std::endl; 982 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 983 r_dcache[num_cache]->printTrace(); 441 r_dcache.printTrace(); 984 442 } 985 443 if(mode & 0x8) 986 444 { 987 445 std::cout << " Instruction cache" << std::endl; 988 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 989 r_icache[num_cache]->printTrace(); 446 r_icache.printTrace(); 990 447 } 448 449 // if(mode & 0x10) 450 // { 451 // std::cout << " Icache miss buffer : "; 452 // CACHE_MISS_BUF_RSP_PRINT(i); 453 // std::cout << std::endl; 454 455 // std::cout << " Dcache miss buffer : "; 456 // CACHE_MISS_BUF_RSP_PRINT(d); 457 // std::cout << std::endl; 458 // } 991 459 } 992 460 … … 997 465 if ( not p_resetn.read() ) { 998 466 999 r_cpu_prior = 0; 1000 1001 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 1002 m_iss[num_cpu]->reset(); 467 m_iss.reset(); 1003 468 1004 469 // FSM states 1005 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1006 { 1007 r_icache_fsm [num_cache] = ICACHE_IDLE; 1008 1009 r_icache_lock[num_cache] = m_nb_cpu; 1010 } 1011 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1012 { 1013 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1014 1015 r_dcache_lock[num_cache] = m_nb_cpu; 1016 r_dcache_sync[num_cache] = false; 1017 } 1018 470 r_dcache_fsm = DCACHE_IDLE; 471 r_icache_fsm = ICACHE_IDLE; 1019 472 r_vci_cmd_fsm = CMD_IDLE; 1020 473 r_vci_rsp_fsm = RSP_IDLE; … … 1022 475 r_cleanup_fsm = CLEANUP_IDLE; 1023 476 1024 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)1025 {1026 477 // write buffer & caches 1027 r_icache[num_cache]->reset(); 478 r_wbuf.reset(); 479 r_icache.reset(); 480 r_dcache.reset(); 1028 481 1029 482 // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs 1030 r_icache_miss_req [num_cache] = false; 1031 r_icache_unc_req [num_cache] = false; 1032 r_icache_cleanup_req [num_cache] = false; 1033 1034 // internal messages in DCACHE et ICACHE FSMs 1035 r_icache_inval_rsp [num_cache] = false; 1036 1037 // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs 1038 r_icache_buf_unc_valid [num_cache] = false; 483 r_icache_miss_req = false; 484 r_icache_unc_req = false; 485 r_icache_cleanup_req = false; 486 r_dcache_miss_req = false; 487 r_dcache_unc_req = false; 488 r_dcache_sc_req = false; 489 r_dcache_cleanup_req = false; 490 r_dcache_previous_unc= false; 1039 491 1040 492 // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs 1041 r_tgt_icache_req [num_cache] = false; 1042 r_tgt_icache_rsp [num_cache] = false; 1043 1044 r_vci_rsp_ins_error [num_cache] = false; 1045 }// end for num_cache 1046 1047 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1048 { 1049 // write buffer & caches 1050 r_wbuf [num_cache]->reset(); 1051 r_dcache[num_cache]->reset(); 1052 1053 // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs 1054 r_dcache_miss_req [num_cache] = false; 1055 r_dcache_unc_req [num_cache] = false; 1056 r_dcache_sc_req [num_cache] = false; 1057 r_dcache_cleanup_req [num_cache] = false; 1058 r_dcache_previous_unc[num_cache] = false; 1059 1060 // internal messages in DCACHE et ICACHE FSMs 1061 r_dcache_inval_rsp [num_cache] = false; 1062 1063 // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs 1064 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 1065 r_dcache_ll_valid [num_cache][num_cpu] = false; 1066 1067 // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs 1068 r_tgt_dcache_req [num_cache] = false; 1069 r_tgt_dcache_rsp [num_cache] = false; 1070 1071 r_vci_rsp_data_error [num_cache] = false; 1072 }// end for num_cache 493 r_tgt_icache_req = false; 494 r_tgt_dcache_req = false; 495 r_tgt_icache_rsp = false; 496 r_tgt_dcache_rsp = false; 1073 497 1074 498 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 1076 500 #endif 1077 501 502 503 // internal messages in DCACHE et ICACHE FSMs 504 r_icache_inval_rsp = false; 505 r_dcache_inval_rsp = false; 506 507 // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs 508 r_dcache_ll_valid = false; 509 r_icache_buf_unc_valid = false; 510 1078 511 r_vci_cmd_dcache_prior = false; 512 513 r_vci_rsp_data_error = false; 514 r_vci_rsp_ins_error = false; 1079 515 1080 516 CACHE_MISS_BUF_RESET(i); … … 1099 535 m_cpt_cc_update_dcache_word_useful = 0; 1100 536 1101 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 1102 m_cpt_frz_cycles [num_cpu] = 0; 537 m_cpt_frz_cycles = 0; 1103 538 m_cpt_total_cycles = 0; 1104 539 … … 1128 563 m_length_write_transaction = 0; 1129 564 1130 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)1131 {1132 m_cpt_icache_access [num_cache] = 0;1133 m_cpt_icache_miss_victim_wait [num_cache] = 0;1134 1135 for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i)1136 m_cpt_fsm_icache [num_cache][i] = 0;1137 }1138 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)1139 {1140 m_cpt_dcache_access [num_cache] = 0;1141 m_cpt_dcache_miss_victim_wait [num_cache] = 0;1142 1143 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE1144 m_cpt_dcache_store_after_store [num_cache] = 0;1145 #endif1146 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS1147 m_cpt_dcache_hit_after_miss_read [num_cache] = 0;1148 m_cpt_dcache_hit_after_miss_write [num_cache] = 0;1149 #endif1150 for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i)1151 m_cpt_fsm_dcache [num_cache][i] = 0;1152 }1153 1154 for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str ); ++i)1155 m_cpt_fsm_cmd [i] = 0;1156 for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str ); ++i)1157 m_cpt_fsm_rsp [i] = 0;1158 for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str ); ++i)1159 m_cpt_fsm_tgt [i] = 0;1160 for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str); ++i)1161 m_cpt_fsm_cleanup [i] = 0;1162 1163 565 return; 1164 566 } … … 1167 569 1168 570 PRINTF("--------------------------------------------\n"); 1169 PRINTF(" * CC_XCACHE_WRAPPER \"%s\" Transition - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); 1170 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1171 PRINTF(" * fsm dcache = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,dcache_fsm_state_str[r_dcache_fsm[num_cache]],r_dcache_lock[num_cache].read(),(blob_t)r_dcache_addr_save[num_cache].read(),(blob_t)set_num_dcache_only(r_dcache_addr_save[num_cache].read(),num_cache)); 1172 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1173 PRINTF(" * fsm icache = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,icache_fsm_state_str[r_icache_fsm[num_cache]],r_icache_lock[num_cache].read(),(blob_t)r_icache_addr_save[num_cache].read(),(blob_t)set_num_icache_only(r_icache_addr_save[num_cache].read(),num_cache)); 1174 PRINTF(" * fsm cmd = (%.2d) %s\n",r_vci_cmd_num_cache.read(), cmd_fsm_state_str[r_vci_cmd_fsm]); 1175 PRINTF(" * fsm rsp = (%.2d) %s\n",r_vci_rsp_num_cache.read(), rsp_fsm_state_str[r_vci_rsp_fsm]); 1176 PRINTF(" * fsm tgt = (%.2d) %s - i %llx d %llx\n",r_tgt_num_cache.read(), tgt_fsm_state_str[r_vci_tgt_fsm],(blob_t)r_tgt_iaddr.read(),(blob_t)r_tgt_daddr.read()); 1177 //PRINTF(" * fsm tgt = %s - %llx\n",tgt_fsm_state_str[r_vci_tgt_fsm],(blob_t)r_tgt_addr.read()); 1178 PRINTF(" * fsm cleanup = (%.2d) %s\n",r_cleanup_num_cache.read(), cleanup_fsm_state_str[r_cleanup_fsm]); 1179 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1180 { 1181 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 1182 PRINTF(" * ll info : [%.2d][%.2d] %d %llx (%llx) %llx\n" 1183 ,num_cache 1184 ,num_cpu 1185 , r_dcache_ll_valid [num_cache][num_cpu].read() 1186 ,(blob_t)r_dcache_ll_addr [num_cache][num_cpu].read() 1187 ,(blob_t)set_num_dcache_only(r_dcache_ll_addr [num_cache][num_cpu].read(),num_cache) 1188 ,(blob_t)r_dcache_ll_data [num_cache][num_cpu].read()); 1189 1190 PRINTF(" * dcache_previous_unc : [%.2d] %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); 1191 1192 #if CC_XCACHE_WRAPPER_DEBUG 1193 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1194 r_wbuf[num_cache]->printTrace(1); 1195 #endif 1196 } 571 PRINTF(" * CC_XCACHE_WRAPPER \"%s\" - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); 572 PRINTF(" * fsm dcache = %s\n",dcache_fsm_state_str[r_dcache_fsm]); 573 PRINTF(" * fsm icache = %s\n",icache_fsm_state_str[r_icache_fsm]); 574 PRINTF(" * fsm cmd = %s\n",cmd_fsm_state_str[r_vci_cmd_fsm]); 575 PRINTF(" * fsm rsp = %s\n",rsp_fsm_state_str[r_vci_rsp_fsm]); 576 PRINTF(" * fsm tgt = %s\n",tgt_fsm_state_str[r_vci_tgt_fsm]); 577 PRINTF(" * fsm cleanup = %s\n",cleanup_fsm_state_str[r_cleanup_fsm]); 578 PRINTF(" * ll info : %d %llx %llx\n",r_dcache_ll_valid.read(), (uint64_t)r_dcache_ll_addr.read(), (uint64_t)r_dcache_ll_data.read()); 579 PRINTF(" * dcache_previous_unc : %d\n",r_dcache_previous_unc.read()); 1197 580 // CACHE_MISS_BUF_RSP_PRINT(i); 1198 581 // CACHE_MISS_BUF_RSP_PRINT(d); 1199 582 1200 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 1201 m_cpt_fsm_dcache [num_cache][r_dcache_fsm[num_cache]] ++; 1202 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1203 m_cpt_fsm_icache [num_cache][r_icache_fsm[num_cache]] ++; 1204 m_cpt_fsm_cmd [r_vci_cmd_fsm] ++; 1205 m_cpt_fsm_rsp [r_vci_rsp_fsm] ++; 1206 m_cpt_fsm_tgt [r_vci_tgt_fsm] ++; 1207 m_cpt_fsm_cleanup [r_cleanup_fsm] ++; 583 #if CC_XCACHE_WRAPPER_DEBUG 584 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 585 { 586 r_wbuf.printTrace(1); 587 } 588 #endif 1208 589 1209 590 m_cpt_total_cycles++; … … 1245 626 if ( p_vci_tgt.cmdval.read() ) 1246 627 { 1247 PRINTF(" * <TGT> Request\n");628 PRINTF(" * <TGT> request\n"); 1248 629 1249 630 addr_40 address = p_vci_tgt.address.read(); … … 1253 634 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 1254 635 std::cout << "coherence request is not a write" << std::endl; 1255 std::cout << " address = " << std::hex << address << std::dec << std::endl;636 std::cout << "oddress = " << std::hex << address << std::dec << std::endl; 1256 637 std::cout << "srcid = " << p_vci_tgt.srcid.read() << std::endl; 1257 638 exit(0); … … 1263 644 std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 1264 645 std::cout << "out of segment coherence request" << std::endl; 1265 std::cout << " address = " << std::hex << address << std::dec << std::endl;646 std::cout << "oddress = " << std::hex << address << std::dec << std::endl; 1266 647 std::cout << "srcid = " << p_vci_tgt.srcid.read() << std::endl; 1267 648 exit(0); 1268 649 } 1269 650 1270 addr_40 tgt_addr = ((((addr_40)p_vci_tgt.be.read() & 0x3) << 32) | ((addr_40) p_vci_tgt.wdata.read())) << (addr_40)m_dcache_words_shift; 1271 // * m_dcache_words * 4; 1272 1273 addr_40 tgt_iaddr = tgt_addr; 1274 addr_40 tgt_daddr = tgt_addr; 1275 1276 PRINTF(" * <TGT> srcid : %d\n",(uint32_t)p_vci_tgt.srcid.read()); 1277 PRINTF(" * <TGT> trdid : %d\n",(uint32_t)p_vci_tgt.trdid.read()); 1278 PRINTF(" * <TGT> pktid : %d\n",(uint32_t)p_vci_tgt.pktid.read()); 1279 PRINTF(" * <TGT> address (before) : %llx\n",(blob_t)tgt_iaddr); 1280 1281 r_tgt_srcid = p_vci_tgt.srcid.read(); 1282 r_tgt_trdid = p_vci_tgt.trdid.read(); 1283 r_tgt_pktid = p_vci_tgt.pktid.read(); 1284 // r_tgt_plen = p_vci_tgt.plen.read(); 651 r_tgt_addr = (((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | 652 ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4; 653 r_tgt_srcid = p_vci_tgt.srcid.read(); 654 r_tgt_trdid = p_vci_tgt.trdid.read(); 655 r_tgt_pktid = p_vci_tgt.pktid.read(); 656 // r_tgt_plen = p_vci_tgt.plen.read(); 1285 657 1286 // BROADCAST 658 PRINTF(" * <TGT> address : %llx\n",(uint64_t)address); 659 PRINTF(" * <TGT> address : %llx\n",(uint64_t)((((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | 660 ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4)); 661 1287 662 if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type 1288 663 { … … 1296 671 // r_tgt_brdcast= true; 1297 672 r_vci_tgt_fsm = TGT_REQ_BROADCAST; 1298 uint32_t tgt_num_cache;1299 tgt_num_cache = get_num_icache(tgt_iaddr,0); // none effect (else CC_XCACHE_WRAPPER_MULTI_CACHE==1)1300 tgt_num_cache = get_num_dcache(tgt_daddr);1301 r_tgt_num_cache = tgt_num_cache;1302 1303 PRINTF(" * <TGT> REQ_BROADCAST\n");1304 PRINTF(" * <TGT> num_cache (data) : %d\n",tgt_num_cache);1305 1306 673 m_cpt_cc_inval_broadcast++ ; 1307 1308 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1309 {1310 log_transaction_file_tgt1311 << "[" << m_cpt_total_cycles << "] "1312 << "BROADCAST "1313 << std::hex1314 << " L " << std::setw(10) << (blob_t)tgt_addr1315 << std::dec1316 << " - " << tgt_num_cache1317 << std::endl;1318 }1319 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1320 1321 674 } 1322 675 else // multi-update or multi-invalidate for data type … … 1324 677 uint32_t cell = address - m_segment.baseAddress(); // addr_40 1325 678 // r_tgt_brdcast = false; 1326 1327 679 if (cell == 0) 1328 680 { // invalidate data … … 1335 687 r_tgt_update = false; 1336 688 r_vci_tgt_fsm = TGT_REQ_DCACHE; 1337 uint32_t tgt_num_cache = get_num_dcache(tgt_daddr); // static partionnement1338 r_tgt_num_cache = tgt_num_cache;1339 1340 PRINTF(" * <TGT> REQ_DCACHE\n");1341 PRINTF(" * <TGT> num_cache : %d\n",tgt_num_cache);1342 1343 689 m_cpt_cc_inval_dcache++ ; 1344 1345 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1346 {1347 log_transaction_file_tgt1348 << "[" << m_cpt_total_cycles << "] "1349 << "INVAL DATA "1350 << std::hex1351 << " L " << std::setw(10) << (blob_t)tgt_addr1352 << std::dec1353 << " - " << tgt_num_cache1354 << std::endl;1355 }1356 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1357 1358 690 } 1359 691 else if (cell == 4) // invalidate instruction … … 1367 699 r_tgt_update = false; 1368 700 r_vci_tgt_fsm = TGT_REQ_ICACHE; 1369 uint32_t tgt_num_cpu = p_vci_tgt.pktid.read();1370 uint32_t tgt_num_cache = get_num_icache(tgt_iaddr,tgt_num_cpu);1371 r_tgt_num_cache = tgt_num_cache;1372 1373 PRINTF(" * <TGT> REQ_ICACHE\n");1374 PRINTF(" * <TGT> num_cache : %d\n",tgt_num_cache);1375 1376 701 m_cpt_cc_inval_icache++ ; 1377 1378 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1379 {1380 log_transaction_file_tgt1381 << "[" << m_cpt_total_cycles << "] "1382 << "INVAL INS "1383 << std::hex1384 << " L " << std::setw(10) << (blob_t)tgt_addr1385 << std::dec1386 << " - " << tgt_num_cache1387 << std::endl;1388 }1389 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1390 1391 702 } 1392 703 else if ( (cell == 8) or (cell==12) ) // update data or instruction … … 1402 713 m_cpt_cc_update_dcache++; 1403 714 r_tgt_update_data = true; 1404 1405 uint32_t tgt_num_cache = get_num_dcache(tgt_daddr);1406 r_tgt_num_cache = tgt_num_cache;1407 1408 PRINTF(" * <TGT> UPDT_WORD DATA\n");1409 PRINTF(" * <TGT> num_cache : %d\n",tgt_num_cache);1410 1411 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1412 {1413 log_transaction_file_tgt1414 << "[" << m_cpt_total_cycles << "] "1415 << "UPT DATA "1416 << std::hex1417 << " L " << std::setw(10) << (blob_t)tgt_addr1418 << std::dec1419 << " - " << tgt_num_cache1420 << std::endl;1421 }1422 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1423 715 } 1424 716 else … … 1426 718 m_cpt_cc_update_icache++; 1427 719 r_tgt_update_data = false; 1428 1429 uint32_t tgt_num_cpu = p_vci_tgt.pktid.read();1430 uint32_t tgt_num_cache = get_num_icache(tgt_iaddr,tgt_num_cpu);1431 r_tgt_num_cache = tgt_num_cache;1432 1433 PRINTF(" * <TGT> UPDT_WORD INSTRUCTION\n");1434 PRINTF(" * <TGT> num_cache : %d\n",tgt_num_cache);1435 1436 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1437 {1438 log_transaction_file_tgt1439 << "[" << m_cpt_total_cycles << "] "1440 << "UPT INS "1441 << std::hex1442 << " L " << std::setw(10) << (blob_t)tgt_addr1443 << std::dec1444 << " - " << tgt_num_cache1445 << std::endl;1446 }1447 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION1448 720 } 1449 721 r_tgt_update = true; … … 1452 724 1453 725 } // end if address 1454 1455 r_tgt_iaddr = tgt_iaddr;1456 r_tgt_daddr = tgt_daddr;1457 PRINTF(" * <TGT> address (after) : i %llx, d %llx\n",(blob_t)tgt_iaddr,(blob_t)tgt_daddr);1458 1459 726 } // end if cmdval 1460 727 break; … … 1472 739 r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index 1473 740 #ifdef COHERENCE_DEBUG 1474 std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_ daddr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl;741 std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_addr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl; 1475 742 #endif 1476 743 r_vci_tgt_fsm = TGT_UPDT_DATA; … … 1522 789 1523 790 case TGT_REQ_BROADCAST: 1524 { 1525 bool tgt_icache_req; 1526 1527 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1528 tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read(); 1529 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 1530 tgt_icache_req = false; 1531 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1532 tgt_icache_req |= r_tgt_icache_req[num_cache].read(); 1533 #endif 1534 if (not tgt_icache_req and not r_tgt_dcache_req[r_tgt_num_cache].read()) 1535 { 1536 r_vci_tgt_fsm = TGT_RSP_BROADCAST; 1537 1538 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1539 r_tgt_icache_req[r_tgt_num_cache] = true; 1540 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 1541 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1542 r_tgt_icache_req[ num_cache] = true; 1543 #endif 1544 1545 r_tgt_dcache_req[r_tgt_num_cache] = true; 1546 } 791 if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 792 { 793 r_vci_tgt_fsm = TGT_RSP_BROADCAST; 794 r_tgt_icache_req = true; 795 r_tgt_dcache_req = true; 1547 796 } 1548 797 break; … … 1550 799 case TGT_REQ_ICACHE: 1551 800 { 1552 // Request treated by the icache 1553 if ( not r_tgt_icache_req[r_tgt_num_cache].read() ) 801 if ( not r_tgt_icache_req.read() ) 1554 802 { 1555 803 r_vci_tgt_fsm = TGT_RSP_ICACHE; 1556 r_tgt_icache_req [r_tgt_num_cache]= true;804 r_tgt_icache_req = true; 1557 805 } 1558 806 break; … … 1560 808 1561 809 case TGT_REQ_DCACHE: 1562 { 1563 // Request treated by the dcache 1564 1565 if ( not r_tgt_dcache_req[r_tgt_num_cache].read() ) 810 if ( not r_tgt_dcache_req.read() ) 811 { 812 r_vci_tgt_fsm = TGT_RSP_DCACHE; 813 r_tgt_dcache_req = true; 814 } 815 break; 816 817 case TGT_RSP_BROADCAST: 818 if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 819 { 820 // one response 821 if ( not r_tgt_icache_rsp or not r_tgt_dcache_rsp ) 1566 822 { 1567 r_vci_tgt_fsm = TGT_RSP_DCACHE; 1568 r_tgt_dcache_req[r_tgt_num_cache] = true; 1569 } 1570 break; 1571 } 1572 case TGT_RSP_BROADCAST: 1573 { 1574 PRINTF(" * <TGT> dcache[%d] : %d - %d\n",(uint32_t)r_tgt_num_cache, (uint32_t)r_tgt_dcache_req[r_tgt_num_cache].read(),(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read()); 1575 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1576 PRINTF(" * <TGT> icache[%d] : %d - %d\n",(uint32_t)num_cache, (uint32_t)r_tgt_icache_req[num_cache].read(),(uint32_t)r_tgt_icache_rsp[num_cache].read()); 1577 1578 bool tgt_icache_req; 1579 1580 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1581 tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read(); 1582 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 1583 tgt_icache_req = false; 1584 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1585 tgt_icache_req |= r_tgt_icache_req[num_cache].read(); 1586 #endif 1587 if (not tgt_icache_req and not r_tgt_dcache_req[r_tgt_num_cache].read()) 823 if ( p_vci_tgt.rspack.read() ) 824 { 825 r_vci_tgt_fsm = TGT_IDLE; 826 r_tgt_icache_rsp = false; 827 r_tgt_dcache_rsp = false; 828 } 829 } 830 831 // if data and instruction have the inval line, need two responses 832 if ( r_tgt_icache_rsp and r_tgt_dcache_rsp ) 1588 833 { 1589 bool tgt_icache_rsp; 1590 uint32_t tgt_icache_rsp_num_cache; 1591 1592 #if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) 1593 tgt_icache_rsp_num_cache = r_tgt_num_cache; 1594 tgt_icache_rsp = r_tgt_icache_rsp[r_tgt_num_cache].read(); 1595 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 1596 tgt_icache_rsp_num_cache = 0; 1597 for (;tgt_icache_rsp_num_cache<m_nb_icache; ++tgt_icache_rsp_num_cache) 834 if ( p_vci_tgt.rspack.read() ) 1598 835 { 1599 PRINTF(" * <TGT> icache[%d] : %d\n",(uint32_t)tgt_icache_rsp_num_cache, (uint32_t)r_tgt_icache_rsp[tgt_icache_rsp_num_cache].read()); 1600 1601 if (r_tgt_icache_rsp[tgt_icache_rsp_num_cache].read()) 1602 break; 836 r_tgt_icache_rsp = false; // only reset one for respond the second time 1603 837 } 1604 1605 tgt_icache_rsp = (tgt_icache_rsp_num_cache<m_nb_icache); 1606 #endif 1607 1608 PRINTF(" * <TGT> icache_rsp [%d] : %d\n",tgt_icache_rsp_num_cache,(uint32_t) tgt_icache_rsp); 1609 PRINTF(" * <TGT> dcache_rsp [%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t) r_tgt_dcache_rsp[r_tgt_num_cache]); 1610 1611 if (tgt_icache_rsp or r_tgt_dcache_rsp[r_tgt_num_cache]) 1612 { 1613 // Have send one response 1614 if ( p_vci_tgt.rspack.read()) 1615 { 1616 // reset dcache if activated 1617 if (r_tgt_dcache_rsp[r_tgt_num_cache]) 1618 r_tgt_dcache_rsp[r_tgt_num_cache] = false; 1619 else 1620 // reset one icache 1621 r_tgt_icache_rsp[tgt_icache_rsp_num_cache] = false; 1622 } 1623 } 1624 1625 // // one response 1626 // if ( not r_tgt_icache_rsp[r_tgt_num_cache] or not r_tgt_dcache_rsp[r_tgt_num_cache] ) 1627 // { 1628 // if ( p_vci_tgt.rspack.read() ) 1629 // { 1630 // r_vci_tgt_fsm = TGT_IDLE; 1631 // r_tgt_icache_rsp[r_tgt_num_cache] = false; 1632 // r_tgt_dcache_rsp[r_tgt_num_cache] = false; 1633 // } 1634 // } 1635 1636 // // if data and instruction have the inval line, need two responses 1637 // if ( r_tgt_icache_rsp[r_tgt_num_cache] and r_tgt_dcache_rsp[r_tgt_num_cache] ) 1638 // { 1639 // if ( p_vci_tgt.rspack.read() ) 1640 // { 1641 // r_tgt_icache_rsp[r_tgt_num_cache] = false; // only reset one for respond the second time 1642 // } 1643 // } 1644 1645 PRINTF(" * <TGT> icache_rsp : %d\n",(uint32_t) r_tgt_icache_rsp[r_tgt_num_cache]); 1646 PRINTF(" * <TGT> dcache_rsp[%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read()); 1647 // if there is no need for a response 1648 if (not tgt_icache_rsp and not r_tgt_dcache_rsp[r_tgt_num_cache] ) 1649 { 1650 r_vci_tgt_fsm = TGT_IDLE; 1651 } 1652 1653 } 1654 break; 1655 } 838 } 839 840 // if there is no need for a response 841 if ( not r_tgt_icache_rsp and not r_tgt_dcache_rsp ) 842 { 843 r_vci_tgt_fsm = TGT_IDLE; 844 } 845 846 } 847 break; 1656 848 //////////////////// 1657 849 case TGT_RSP_ICACHE: 1658 850 { 1659 bool transaction_rsp = (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp[r_tgt_num_cache].read()) and not r_tgt_icache_req[r_tgt_num_cache].read(); 1660 1661 PRINTF(" * <TGT> RSP_ICACHE : transaction : %d ((%d or not %d) and not %d)\n",transaction_rsp 1662 ,(int)p_vci_tgt.rspack.read() 1663 ,(int)r_tgt_icache_rsp[r_tgt_num_cache].read() 1664 ,(int)r_tgt_icache_req[r_tgt_num_cache].read() 1665 ); 1666 1667 if (transaction_rsp) 851 if ( (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp.read()) and not r_tgt_icache_req.read() ) 1668 852 { 1669 853 r_vci_tgt_fsm = TGT_IDLE; 1670 r_tgt_icache_rsp [r_tgt_num_cache]= false;854 r_tgt_icache_rsp = false; 1671 855 } 1672 856 break; … … 1675 859 case TGT_RSP_DCACHE: 1676 860 { 1677 bool transaction_rsp = (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp[r_tgt_num_cache].read()) and not r_tgt_dcache_req[r_tgt_num_cache].read(); 1678 1679 PRINTF(" * <TGT> RSP_DCACHE : transaction : %d\n",transaction_rsp); 1680 1681 if (transaction_rsp) 861 if ( (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp.read()) and not r_tgt_dcache_req.read() ) 1682 862 { 1683 863 r_vci_tgt_fsm = TGT_IDLE; 1684 r_tgt_dcache_rsp [r_tgt_num_cache]= false;864 r_tgt_dcache_rsp = false; 1685 865 } 1686 866 break; 1687 867 } 1688 868 } // end switch TGT_FSM 1689 1690 /////////////////////////////////////////////////////////////////////1691 // Interface between CPU and CACHE FSM1692 ///////////////////////////////////////////////////////////////////////1693 1694 uint32_t ireq_num_cache [m_nb_cpu];1695 uint32_t dreq_num_cache [m_nb_cpu];1696 bool have_sync = false;1697 1698 {1699 typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER;1700 typename iss_t::DataRequest _dreq = ISS_DREQ_INITIALIZER;1701 1702 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)1703 {1704 ireq [num_cache] = _ireq;1705 //irsp [num_cache] = _irsp;1706 }1707 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)1708 {1709 dreq [num_cache] = _dreq;1710 //drsp [num_cache] = _drsp;1711 1712 have_sync |= r_dcache_sync [num_cache];1713 }1714 }1715 1716 for (uint32_t _num_cpu=0; _num_cpu<m_nb_cpu; ++_num_cpu)1717 {1718 // round robin priority1719 uint32_t num_cpu = (r_cpu_prior+_num_cpu)%m_nb_cpu;1720 1721 typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER;1722 typename iss_t::DataRequest _dreq = ISS_DREQ_INITIALIZER;1723 1724 m_iss[num_cpu]->getRequests(_ireq, _dreq);1725 1726 addr_40 addr;1727 uint32_t num_cache;1728 1729 addr = (addr_40)_ireq.addr;1730 num_cache = get_num_icache(addr,num_cpu);1731 1732 bool icache_req_valid = ((not ireq[num_cache].valid and // no previous request in this cycle1733 (r_icache_lock [num_cache] == m_nb_cpu)) or // no previous request in previous cycle1734 (r_icache_lock [num_cache] == num_cpu)); // previous request in previous cycle by this cpu1735 1736 if (icache_req_valid)1737 {1738 bool valid = _ireq.valid;1739 1740 if (valid)1741 {1742 PRINTF(" * <CPU2CACHE> ICACHE : Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache);1743 ireq_num_cache [num_cpu ] = num_cache;1744 r_icache_lock [num_cache] = num_cpu;1745 }1746 else1747 {1748 PRINTF(" * <CPU2CACHE> ICACHE : No Transaction between cpu %d and cache %d : invalid\n",num_cpu,num_cache);1749 ireq_num_cache [num_cpu] = m_nb_icache;1750 }1751 1752 ireq_cached [num_cache] = m_cacheability_table[(vci_addr_t)_ireq.addr];1753 ireq_num_cpu [num_cache] = num_cpu;1754 ireq [num_cache] = _ireq;1755 ireq [num_cache].addr = addr;1756 }1757 else1758 {1759 PRINTF(" * <CPU2CACHE> ICACHE : No transaction (cpu %d)\n",num_cpu);1760 1761 ireq_num_cache [num_cpu] = m_nb_icache;1762 }1763 1764 addr = (addr_40)_dreq.addr;1765 num_cache = get_num_dcache(addr);1766 1767 1768 bool dcache_no_lock = (r_dcache_lock [num_cache] == m_nb_cpu);1769 bool dcache_lock_owner = (r_dcache_lock [num_cache] == num_cpu);1770 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS1771 bool dcache_lock_no_owner= not dcache_no_lock and not dcache_lock_owner;1772 bool dcache_wait = ((r_dcache_fsm[num_cache] == DCACHE_MISS_WAIT)// or1773 // (r_dcache_fsm[num_cache] == DCACHE_UNC_WAIT) or1774 // (r_dcache_fsm[num_cache] == DCACHE_SC_WAIT)1775 );1776 1777 bool dcache_req_valid = ((not dreq[num_cache].valid and // no previous request in this cycle1778 not have_sync and // no sync instruction1779 (dcache_no_lock or1780 (dcache_lock_no_owner and dcache_wait))) or // no previous request in previous cycle1781 (dcache_lock_owner and not dcache_wait)); // previous request in previous cycle by this cpu1782 #else1783 bool dcache_req_valid = ((not dreq[num_cache].valid and // no previous request in this cycle1784 not have_sync and // no sync instruction1785 dcache_no_lock) or // no previous request in previous cycle1786 dcache_lock_owner); // previous request in previous cycle by this cpu1787 #endif1788 // @@@@1789 1790 1791 // test if already used1792 if (dcache_req_valid)1793 {1794 bool valid = _dreq.valid;1795 1796 if (valid)1797 {1798 PRINTF(" * <CPU2CACHE> DCACHE : Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache);1799 dreq_num_cache [num_cpu ] = num_cache;1800 1801 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS1802 if (not dcache_lock_no_owner)1803 #endif1804 r_dcache_lock [num_cache] = num_cpu;1805 }1806 else1807 {1808 PRINTF(" * <CPU2CACHE> DCACHE : No Transaction between cpu %d and cache %d : invalid\n",num_cpu,num_cache);1809 dreq_num_cache [num_cpu] = m_nb_dcache;1810 }1811 1812 dreq_cached [num_cache] = m_cacheability_table[(vci_addr_t)_dreq.addr];1813 dreq_num_cpu [num_cache] = num_cpu;1814 dreq [num_cache] = _dreq;1815 dreq [num_cache].addr = addr;1816 }1817 else1818 {1819 PRINTF(" * <CPU2CACHE> DCACHE : No transaction (cpu %d)\n",num_cpu);1820 1821 dreq_num_cache [num_cpu] = m_nb_dcache;1822 }1823 1824 1825 #if CC_XCACHE_WRAPPER_DEBUG1826 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)1827 {1828 std::cout << " * <CPU2CACHE> Instruction Request : " << ireq_num_cache[num_cpu] << " - " << _ireq << std::endl1829 << " * <CPU2CACHE> Data Request : " << dreq_num_cache[num_cpu] << " - " << _dreq << std::endl;1830 }1831 #endif1832 }1833 1834 // round robin priority1835 r_cpu_prior = (r_cpu_prior+1)%m_nb_cpu;1836 869 1837 870 ///////////////////////////////////////////////////////////////////// … … 1866 899 // flip-flop. It is reset by the ICACHE FSM. 1867 900 /////////////////////////////////////////////////////////////////////// 1868 1869 for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache) 1870 { 1871 typename iss_t::InstructionRequest _ireq = ireq [num_cache]; 1872 typename iss_t::InstructionResponse _irsp = ISS_IRSP_INITIALIZER; 1873 1874 switch(r_icache_fsm[num_cache]) { 901 902 typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER; 903 typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER; 904 905 typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER; 906 typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER; 907 908 m_iss.getRequests( ireq, dreq ); 909 910 #if CC_XCACHE_WRAPPER_DEBUG 911 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 912 std::cout << " * Instruction Request : " << ireq << std::endl; 913 #endif 914 915 switch(r_icache_fsm) { 1875 916 ///////////////// 1876 917 case ICACHE_IDLE: 1877 918 { 1878 if ( r_tgt_icache_req [num_cache]) { // external request1879 // if ( _ireq.valid ) m_cost_ins_miss_frz++;1880 r_icache_fsm [num_cache]= ICACHE_CC_CHECK;1881 r_icache_fsm_save [num_cache] = r_icache_fsm[num_cache];919 if ( r_tgt_icache_req ) { // external request 920 if ( ireq.valid ) m_cost_ins_miss_frz++; 921 r_icache_fsm = ICACHE_CC_CHECK; 922 r_icache_fsm_save = r_icache_fsm.read(); 1882 923 break; 1883 924 } 1884 if ( _ireq.valid ) { 1885 data_t icache_ins = 0; 1886 bool icache_hit = false; 1887 bool icache_cached = ireq_cached [num_cache]; 1888 // uint32_t icache_num_cpu = ireq_num_cpu [num_cache]; 1889 bool icache_cleanup_hit = r_icache_cleanup_req[num_cache] and (((addr_40)_ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line[num_cache].read()); 925 if ( ireq.valid ) { 926 data_t icache_ins = 0; 927 bool icache_hit = false; 928 bool icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr]; 929 bool icache_cleanup_hit = r_icache_cleanup_req and (((addr_40)ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line.read()); 1890 930 1891 931 // icache_hit & icache_ins evaluation 1892 932 if ( icache_cached ) { 1893 icache_hit = r_icache [num_cache]->read((vci_addr_t) _ireq.addr, &icache_ins);933 icache_hit = r_icache.read((vci_addr_t) ireq.addr, &icache_ins); 1894 934 } else { 1895 935 // if uncache, again in the icache_miss_buf 1896 icache_hit = (r_icache_buf_unc_valid[num_cache] and ((addr_40) _ireq.addr == (addr_40)r_icache_addr_save[num_cache])); 1897 icache_ins = CACHE_MISS_BUF_RSP_DATA(i,num_cache,0); 1898 1899 if (icache_hit) 1900 CACHE_MISS_BUF_RSP_POP(i,num_cache); 936 icache_hit = ( r_icache_buf_unc_valid and ((addr_40) ireq.addr == (addr_40)r_icache_addr_save)); 937 icache_ins = CACHE_MISS_BUF_RSP_DATA(i,0); 938 CACHE_MISS_BUF_RSP_POP(i); 1901 939 } 1902 940 1903 PRINTF(" * <ICACHE [%d]> hit %d - cached %d - cleanup_hit %d\n",num_cache, icache_hit, icache_cached, icache_cleanup_hit); 1904 1905 if (icache_hit and icache_cleanup_hit) 941 PRINTF(" * <ICACHE> hit %d - cached %d - cleanup_hit %d\n",icache_hit, icache_cached, icache_cleanup_hit); 942 943 ASSERT( not (icache_hit and icache_cleanup_hit), 944 "Icache hit and icache_cleanup_hit"); 945 946 if ( not icache_hit and not icache_cleanup_hit) { 947 m_cpt_ins_miss++; 948 m_cost_ins_miss_frz++; 949 r_icache_addr_save = (addr_40) ireq.addr; 950 951 CACHE_MISS_BUF_REQ_INIT(i); 952 953 if ( icache_cached ) { 954 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 955 r_icache_fsm = ICACHE_MISS_VICTIM; 956 #else 957 r_icache_fsm = ICACHE_MISS_WAIT; 958 #endif 959 r_icache_miss_req = true; 960 961 } else { 962 r_icache_fsm = ICACHE_UNC_WAIT; 963 r_icache_unc_req = true; 964 } 965 } else { 966 r_icache_buf_unc_valid = false; 967 } 968 m_cpt_icache_dir_read += m_icache_ways; 969 m_cpt_icache_data_read += m_icache_ways; 970 irsp.valid = icache_hit; 971 irsp.instruction = icache_ins; 972 } 973 break; 974 } 975 ////////////////////// 976 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 977 case ICACHE_MISS_VICTIM: 978 { 979 if (not r_icache_cleanup_req) 980 { 981 size_t way; 982 size_t set; 983 vci_addr_t addr = (vci_addr_t) r_icache_addr_save.read(); 984 vci_addr_t victim; 985 986 r_icache_cleanup_req = r_icache.victim_select(addr, &victim, &way, &set ); 987 r_icache_cleanup_line = (addr_40) victim; 988 r_icache_miss_way = way; 989 r_icache_miss_set = set; 990 991 r_icache_fsm = ICACHE_MISS_WAIT; 992 } 993 break; 994 } 995 #endif 996 ////////////////////// 997 case ICACHE_MISS_WAIT: 998 { 999 m_cost_ins_miss_frz++; 1000 if ( r_tgt_icache_req ) { // external request 1001 r_icache_fsm = ICACHE_CC_CHECK; 1002 r_icache_fsm_save = r_icache_fsm.read(); 1003 break; 1004 } 1005 1006 bool val = CACHE_MISS_BUF_RSP_VAL(i,0); 1007 1008 PRINTF(" * <ICACHE> val : %d\n",val); 1009 1010 if (val) 1011 { 1012 PRINTF(" * <ICACHE> r_icache_inval_rsp : %d\n",(int) r_icache_inval_rsp ); 1013 PRINTF(" * <ICACHE> r_vci_rsp_ins_error : %d\n",(int) r_vci_rsp_ins_error ); 1014 PRINTF(" * <ICACHE> r_icache_cleanup_req : %d\n",(int) r_icache_cleanup_req); 1015 1016 // if (not r_icache_inval_rsp ) 1017 // { 1018 // Miss read response and no invalidation 1019 if ( r_vci_rsp_ins_error ) { 1020 r_icache_fsm = ICACHE_ERROR; 1021 } else { 1022 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM 1023 if (not r_icache_cleanup_req.read()) 1024 #endif 1025 { 1026 r_icache_update_addr = 0; 1027 r_icache_fsm = ICACHE_MISS_UPDT; 1028 } 1029 } 1030 // } 1031 // else 1032 // { 1033 // r_icache_inval_rsp = false; 1034 1035 // // Miss read response and invalidation 1036 // if ( r_vci_rsp_ins_error ) 1037 // r_icache_fsm = ICACHE_ERROR; 1038 // else 1039 // r_icache_fsm = ICACHE_CC_CLEANUP; 1040 // } 1041 } 1042 break; 1043 } 1044 ///////////////////// 1045 case ICACHE_UNC_WAIT: 1046 { 1047 m_cost_ins_miss_frz++; 1048 if ( r_tgt_icache_req ) { // external request 1049 r_icache_fsm = ICACHE_CC_CHECK; 1050 r_icache_fsm_save = r_icache_fsm.read(); 1051 break; 1052 } 1053 1054 bool ok = CACHE_MISS_BUF_RSP_VAL(i,0); 1055 1056 if (ok) 1057 { 1058 if ( r_vci_rsp_ins_error ) { 1059 r_icache_fsm = ICACHE_ERROR; 1060 } else { 1061 r_icache_fsm = ICACHE_IDLE; 1062 r_icache_buf_unc_valid = true; 1063 } 1064 } 1065 break; 1066 } 1067 ////////////////// 1068 case ICACHE_ERROR: 1069 { 1070 if ( (addr_40)ireq.addr == (addr_40)r_icache_addr_save ) { 1071 irsp.error = true; 1072 irsp.valid = true; 1073 } 1074 r_icache_fsm = ICACHE_IDLE; 1075 r_vci_rsp_ins_error = false; 1076 break; 1077 } 1078 ////////////////////// 1079 case ICACHE_MISS_UPDT: 1080 { 1081 size_t word = r_icache_update_addr.read(); 1082 vci_addr_t addr = (vci_addr_t) r_icache_addr_save.read(); 1083 size_t way = 0; 1084 size_t set = 0; 1085 1086 // need invalid rsp, don't select a victim 1087 if (not r_icache_inval_rsp ) 1088 { 1089 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1090 way = r_icache_miss_way.read(); 1091 set = r_icache_miss_set.read(); 1092 #else 1093 1094 // First word : select an victim ! 1095 if (word == 0) 1906 1096 { 1907 PRINTF(" * <ICACHE [%d]> Warning : icache hit and icache_cleanup_hit\n",num_cache); 1908 icache_hit = false; 1097 vci_addr_t victim; 1098 1099 // r_icache_cleanup_req is false because is the transition condition to go in ICACHE_MISS_UPDT state 1100 r_icache_cleanup_req = r_icache.victim_select(addr, &victim, &way, &set ); 1101 r_icache.victim_update_tag(addr, way, set); 1102 1103 r_icache_cleanup_line = (addr_40) victim; 1104 r_icache_miss_way = way; 1105 r_icache_miss_set = set; 1909 1106 } 1910 1107 else 1911 1108 { 1912 if ( not icache_hit and not icache_cleanup_hit) 1913 { 1914 m_cpt_ins_miss++; 1915 m_cost_ins_miss_frz++; 1916 1917 r_icache_addr_save[num_cache] = (addr_40) _ireq.addr; 1918 1919 if ( icache_cached ) 1920 { 1921 // to prevent deadlock, miss victim don't be block 1922 if (not r_icache_cleanup_req[num_cache]) 1923 { 1924 CACHE_MISS_BUF_REQ_INIT(i,num_cache); 1925 r_icache_fsm [num_cache] = ICACHE_MISS_VICTIM; 1926 r_icache_miss_req[num_cache] = true; 1927 } 1928 else 1929 m_cpt_icache_miss_victim_wait [num_cache] ++; 1930 } 1931 else 1932 { 1933 CACHE_MISS_BUF_REQ_INIT(i,num_cache); 1934 r_icache_addr_save[num_cache] = (addr_40) _ireq.addr; 1935 1936 r_icache_fsm [num_cache] = ICACHE_UNC_WAIT; 1937 r_icache_unc_req[num_cache] = true; 1938 } 1939 } 1940 else 1941 { 1942 r_icache_buf_unc_valid[num_cache] = false; 1943 } 1944 m_cpt_icache_dir_read += m_icache_ways; 1945 m_cpt_icache_data_read += m_icache_ways; 1109 way = r_icache_miss_way.read(); 1110 set = r_icache_miss_set.read(); 1946 1111 } 1947 1948 _irsp.valid = icache_hit; 1949 _irsp.instruction = icache_ins; 1950 } 1951 break; 1952 } 1953 ////////////////////// 1954 case ICACHE_MISS_VICTIM: 1955 { 1956 // if (not r_icache_cleanup_req[num_cache]) 1957 { 1958 size_t way; 1959 size_t set; 1960 vci_addr_t addr = (vci_addr_t) r_icache_addr_save[num_cache].read(); 1961 vci_addr_t victim; 1962 1963 r_icache_cleanup_req [num_cache] = r_icache[num_cache]->victim_select(addr, &victim, &way, &set ); 1964 r_icache_cleanup_line[num_cache] = (addr_40) victim; 1965 r_icache_miss_way [num_cache] = way; 1966 r_icache_miss_set [num_cache] = set; 1967 1968 r_icache_fsm [num_cache] = ICACHE_MISS_WAIT; 1969 } 1970 break; 1971 } 1972 ////////////////////// 1973 case ICACHE_MISS_WAIT: 1974 { 1975 m_cost_ins_miss_frz++; 1976 if ( r_tgt_icache_req[num_cache] ) { // external request 1977 r_icache_fsm [num_cache] = ICACHE_CC_CHECK; 1978 r_icache_fsm_save [num_cache] = r_icache_fsm[num_cache].read(); 1979 break; 1980 } 1981 1982 bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,0); 1983 1984 PRINTF(" * <ICACHE [%d]> val : %d\n",num_cache,val); 1112 #endif 1113 } 1114 bool val = CACHE_MISS_BUF_RSP_VAL(i,word); 1985 1115 1986 1116 if (val) 1987 1117 { 1988 PRINTF(" * <ICACHE [%d]> r_icache_inval_rsp : %d\n",num_cache,(int) r_icache_inval_rsp [num_cache]); 1989 PRINTF(" * <ICACHE [%d]> r_vci_rsp_ins_error : %d\n",num_cache,(int) r_vci_rsp_ins_error [num_cache]); 1990 PRINTF(" * <ICACHE [%d]> r_icache_cleanup_req : %d\n",num_cache,(int) r_icache_cleanup_req[num_cache]); 1991 1992 // Miss read response and no invalidation 1993 if ( r_vci_rsp_ins_error [num_cache]) { 1994 r_icache_fsm[num_cache] = ICACHE_ERROR; 1995 } else { 1996 r_icache_update_addr[num_cache] = 0; 1997 r_icache_fsm [num_cache] = ICACHE_MISS_UPDT; 1998 } 1999 } 2000 break; 2001 } 2002 ///////////////////// 2003 case ICACHE_UNC_WAIT: 2004 { 2005 m_cost_ins_miss_frz++; 2006 if ( r_tgt_icache_req[num_cache] ) { // external request 2007 r_icache_fsm [num_cache] = ICACHE_CC_CHECK; 2008 r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache].read(); 2009 break; 2010 } 2011 2012 bool ok = CACHE_MISS_BUF_RSP_VAL(i,num_cache,0); 2013 2014 PRINTF(" * <ICACHE [%d]> ok : %d\n",num_cache,ok); 2015 PRINTF(" * <ICACHE [%d]> error : %d\n",num_cache,(uint32_t)r_vci_rsp_ins_error [num_cache]); 2016 2017 if (ok) 2018 { 2019 if ( r_vci_rsp_ins_error [num_cache]) { 2020 r_icache_fsm[num_cache] = ICACHE_ERROR; 2021 } else { 2022 r_icache_fsm [num_cache] = ICACHE_IDLE; 2023 r_icache_buf_unc_valid[num_cache] = true; 2024 } 2025 } 2026 break; 2027 } 2028 ////////////////// 2029 case ICACHE_ERROR: 2030 { 2031 if ( (addr_40)_ireq.addr == (addr_40)r_icache_addr_save[num_cache] ) { 2032 _irsp.error = true; 2033 _irsp.valid = true; 2034 } 2035 r_icache_fsm [num_cache] = ICACHE_IDLE; 2036 r_vci_rsp_ins_error [num_cache] = false; 2037 break; 2038 } 2039 ////////////////////// 2040 case ICACHE_MISS_UPDT: 2041 { 2042 size_t word = r_icache_update_addr[num_cache].read(); 2043 vci_addr_t addr = (vci_addr_t) r_icache_addr_save [num_cache].read(); 2044 size_t way = r_icache_miss_way[num_cache].read(); 2045 size_t set = r_icache_miss_set[num_cache].read(); 2046 2047 bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,word); 2048 2049 if (val) 2050 { 2051 PRINTF(" * <ICACHE [%d]> rsp_val : %d/%d\n",num_cache,(int)r_icache_update_addr[num_cache],(int)m_icache_words); 2052 PRINTF(" * <ICACHE [%d]> r_icache_inval_rsp : %d\n" ,num_cache,(int)r_icache_inval_rsp[num_cache]); 2053 PRINTF(" * <ICACHE [%d]> ins : %x\n" ,num_cache,(int)CACHE_MISS_BUF_RSP_DATA(i,num_cache,word)); 1118 PRINTF(" * <ICACHE> rsp_val : %d/%d\n",(int)r_icache_update_addr,m_icache_words); 1119 PRINTF(" * <ICACHE> r_icache_inval_rsp : %d\n",(int)r_icache_inval_rsp); 1120 PRINTF(" * <ICACHE> ins : %x\n",(int)CACHE_MISS_BUF_RSP_DATA(i,word)); 2054 1121 2055 1122 // m_cpt_icache_dir_write++; 2056 1123 // m_cpt_icache_data_write++; 2057 // if ( _ireq.valid ) m_cost_ins_miss_frz++;1124 // if ( ireq.valid ) m_cost_ins_miss_frz++; 2058 1125 2059 1126 // if need invalid rsp, don't modify the cache, but pop the buf_rsp 2060 if (not r_icache_inval_rsp[num_cache]) 2061 r_icache[num_cache]->write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,num_cache,word)); 2062 2063 CACHE_MISS_BUF_RSP_POP(i,num_cache); 2064 2065 r_icache_update_addr[num_cache] = ++word; 1127 if (not r_icache_inval_rsp ) 1128 r_icache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,word)); 1129 CACHE_MISS_BUF_RSP_POP(i); 1130 1131 r_icache_update_addr = ++word; 2066 1132 2067 1133 // if last word, finish the update 2068 1134 if (word >= m_icache_words) 2069 1135 { 2070 // in all case (inval_rsp or not), update the victim tag2071 r_icache[num_cache]->victim_update_tag(addr, way, set);2072 2073 1136 // Last word : if previous invalid_rsp, can cleanup, else update the TAG 2074 if (r_icache_inval_rsp [num_cache])1137 if (r_icache_inval_rsp) 2075 1138 { 2076 r_icache_inval_rsp [num_cache]= false;2077 r_icache_fsm [num_cache]= ICACHE_CC_CLEANUP;1139 r_icache_inval_rsp = false; 1140 r_icache_fsm = ICACHE_CC_CLEANUP; 2078 1141 } 2079 1142 else 2080 1143 { 2081 r_icache_fsm [num_cache] = ICACHE_IDLE; 1144 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1145 r_icache.victim_update_tag(addr, way, set); 1146 #endif 1147 r_icache_fsm = ICACHE_IDLE; 2082 1148 } 2083 1149 } … … 2089 1155 case ICACHE_CC_CLEANUP: 2090 1156 { 1157 // external cache invalidate request 1158 if ( r_tgt_icache_req ) 1159 { 1160 r_icache_fsm = ICACHE_CC_CHECK; 1161 r_icache_fsm_save = r_icache_fsm.read(); 1162 break; 1163 } 2091 1164 // cleanup 2092 if(not r_icache_cleanup_req[num_cache]){ 2093 r_icache_cleanup_req [num_cache] = true; 2094 r_icache_cleanup_line[num_cache] = r_icache_addr_save[num_cache].read() >> m_icache_words_shift; 2095 r_icache_fsm [num_cache] = ICACHE_IDLE; 2096 2097 m_cpt_icache_dir_read += m_icache_ways; 2098 r_icache[num_cache]->inval((addr_40)r_icache_addr_save[num_cache]); 1165 if(not r_icache_cleanup_req){ 1166 r_icache_cleanup_req = true; 1167 r_icache_cleanup_line = r_icache_addr_save.read() >> m_icache_words_shift; 1168 r_icache_fsm = ICACHE_IDLE; 2099 1169 } 2100 1170 break; … … 2106 1176 m_cpt_icache_dir_read += m_icache_ways; 2107 1177 m_cpt_icache_data_read += m_icache_ways; 2108 addr_40 ad = r_tgt_ iaddr;1178 addr_40 ad = r_tgt_addr; 2109 1179 data_t icache_rdata = 0; 2110 1180 2111 PRINTF(" * <ICACHE [%d]> CC_CHECK\n",num_cache); 2112 2113 if((r_icache_fsm_save[num_cache] == ICACHE_MISS_WAIT) and 2114 ((r_icache_addr_save[num_cache].read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) { 2115 PRINTF(" * <ICACHE [%d]> have request, need inval rsp\n",num_cache); 2116 2117 r_icache_inval_rsp[num_cache] = true; 2118 r_tgt_icache_req [num_cache] = false; 1181 if((r_icache_fsm_save == ICACHE_MISS_WAIT) and 1182 ( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) { 1183 r_icache_inval_rsp = true; 1184 r_tgt_icache_req = false; 2119 1185 if(r_tgt_update){ // Also send a cleanup and answer 2120 PRINTF(" * <ICACHE [%d]> send a cleanup and answer\n",num_cache); 2121 r_tgt_icache_rsp[num_cache] = true; 1186 r_tgt_icache_rsp = true; 2122 1187 } else { // Also send a cleanup but don't answer 2123 PRINTF(" * <ICACHE [%d]> send a cleanup and but don't answer\n",num_cache); 2124 r_tgt_icache_rsp[num_cache] = false; 1188 r_tgt_icache_rsp = false; 2125 1189 } 2126 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache];1190 r_icache_fsm = r_icache_fsm_save; 2127 1191 } else { 2128 bool icache_hit = r_icache[num_cache]->read(ad, &icache_rdata); 2129 2130 PRINTF(" * <ICACHE [%d]> have no request, hit cache : %d\n",num_cache,icache_hit); 2131 2132 if ( icache_hit and r_tgt_update) 1192 bool icache_hit = r_icache.read(ad, &icache_rdata); 1193 if ( icache_hit and r_tgt_update ) 2133 1194 { 2134 1195 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE … … 2137 1198 data_t rdata = 0; 2138 1199 2139 r_icache [num_cache]->read(ad+word*4,&rdata);1200 r_icache.read(ad+word*4,&rdata); 2140 1201 r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); 2141 1202 … … 2149 1210 if (word==m_icache_words) 2150 1211 { 2151 r_icache_fsm [num_cache]= ICACHE_CC_UPDT;1212 r_icache_fsm = ICACHE_CC_UPDT; 2152 1213 2153 1214 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT … … 2161 1222 r_cache_word = word; 2162 1223 #else //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 2163 r_icache_fsm [num_cache]= ICACHE_CC_UPDT;1224 r_icache_fsm = ICACHE_CC_UPDT; 2164 1225 // complete the line buffer in case of update 2165 1226 for(size_t i=0; i<m_icache_words; i++){ 2166 1227 data_t rdata = 0; 2167 r_icache [num_cache]->read(ad + i*4,&rdata);1228 r_icache.read(ad + i*4,&rdata); 2168 1229 data_t mask = vci_param::be2mask(r_tgt_be[i]); 2169 1230 r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata); 2170 1231 } 2171 1232 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 2172 } else if ( icache_hit and not r_tgt_update ) {2173 r_icache_fsm [num_cache]= ICACHE_CC_INVAL;1233 } else if ( icache_hit and not r_tgt_update ) { 1234 r_icache_fsm = ICACHE_CC_INVAL; 2174 1235 } else { // instruction not found (can happen) 2175 r_tgt_icache_req [num_cache]= false;1236 r_tgt_icache_req = false; 2176 1237 if(r_tgt_update){ 2177 r_tgt_icache_rsp [num_cache]= true;1238 r_tgt_icache_rsp = true; 2178 1239 } else { 2179 r_tgt_icache_rsp [num_cache]= false;1240 r_tgt_icache_rsp = false; 2180 1241 } 2181 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache];1242 r_icache_fsm = r_icache_fsm_save; 2182 1243 } 2183 1244 } … … 2187 1248 case ICACHE_CC_INVAL: 2188 1249 { 2189 addr_40 ad = r_tgt_iaddr;2190 // if ( _ireq.valid ) m_cost_ins_miss_frz++;1250 addr_40 ad = r_tgt_addr; 1251 if ( ireq.valid ) m_cost_ins_miss_frz++; 2191 1252 m_cpt_icache_dir_read += m_icache_ways; 2192 r_tgt_icache_rsp [num_cache]= true;2193 r_icache [num_cache]->inval(ad);2194 r_tgt_icache_req [num_cache]= false;2195 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache];1253 r_tgt_icache_rsp = true; 1254 r_icache.inval(ad); 1255 r_tgt_icache_req = false; 1256 r_icache_fsm = r_icache_fsm_save; 2196 1257 break; 2197 1258 } … … 2199 1260 case ICACHE_CC_UPDT: 2200 1261 { 2201 addr_40 ad = r_tgt_ iaddr.read();1262 addr_40 ad = r_tgt_addr.read(); 2202 1263 m_cpt_icache_dir_write++; 2203 1264 m_cpt_icache_data_write++; … … 2207 1268 2208 1269 if(r_tgt_be[word]) 2209 r_icache [num_cache]->write(ad+word*4, r_tgt_buf[word]);1270 r_icache.write(ad+word*4, r_tgt_buf[word]); 2210 1271 2211 1272 word ++; … … 2218 1279 if (word==m_icache_words) 2219 1280 { 2220 r_tgt_icache_req [num_cache]= false;2221 r_tgt_icache_rsp [num_cache]= true;2222 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache].read();1281 r_tgt_icache_req = false; 1282 r_tgt_icache_rsp = true; 1283 r_icache_fsm = r_icache_fsm_save.read(); 2223 1284 word = 0; 2224 1285 } … … 2227 1288 data_t* buf = r_tgt_buf; 2228 1289 for(size_t i=0; i<m_icache_words;i++){ 2229 if(r_tgt_be[i]) r_icache [num_cache]->write( ad + i*4, buf[i]);2230 } 2231 r_tgt_icache_req [num_cache]= false;2232 r_tgt_icache_rsp [num_cache]= true;2233 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache].read();1290 if(r_tgt_be[i]) r_icache.write( ad + i*4, buf[i]); 1291 } 1292 r_tgt_icache_req = false; 1293 r_tgt_icache_rsp = true; 1294 r_icache_fsm = r_icache_fsm_save.read(); 2234 1295 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 2235 1296 … … 2237 1298 } 2238 1299 2239 }// end switch r_icache_fsm 2240 2241 irsp [num_cache] = _irsp; 2242 if (_ireq.valid and _irsp.valid) 2243 { 2244 PRINTF(" * <CPU2CACHE> Transaction between cpu %d and Icache %d (unlock)\n",r_icache_lock [num_cache].read(),num_cache); 2245 2246 r_icache_lock [num_cache] = m_nb_cpu; 2247 m_cpt_icache_access [num_cache] ++; 2248 } 2249 2250 }// end for num_cache 1300 } // end switch r_icache_fsm 1301 1302 #if CC_XCACHE_WRAPPER_DEBUG 1303 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1304 std::cout << " * Instruction Response : " << irsp << std::endl; 1305 #endif 2251 1306 2252 1307 //////////////////////////////////////////////////////////////////////:///////////// … … 2306 1361 /////////////////////////////////////////////////////////////////////////////////// 2307 1362 2308 for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache) 2309 {2310 typename iss_t::DataRequest _dreq = dreq [num_cache];2311 typename iss_t::DataResponse _drsp = ISS_DRSP_INITIALIZER; 2312 2313 switch ( r_dcache_fsm [num_cache]) {1363 #if CC_XCACHE_WRAPPER_DEBUG 1364 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1365 std::cout << " * Data Request : " << dreq << std::endl; 1366 #endif 1367 1368 switch ( r_dcache_fsm ) { 2314 1369 2315 1370 ///////////////// 2316 1371 case DCACHE_IDLE: 2317 1372 { 2318 if ( r_tgt_dcache_req [num_cache]) { // external request2319 r_dcache_fsm [num_cache]= DCACHE_CC_CHECK;2320 r_dcache_fsm_save [num_cache] = r_dcache_fsm[num_cache];1373 if ( r_tgt_dcache_req ) { // external request 1374 r_dcache_fsm = DCACHE_CC_CHECK; 1375 r_dcache_fsm_save = r_dcache_fsm; 2321 1376 break; 2322 1377 } 2323 1378 2324 if ( _dreq.valid ) {2325 PRINTF(" * <DCACHE [%d]> Have dreq\n",num_cache);1379 if ( dreq.valid ) { 1380 PRINTF(" * <DCACHE> Have dreq\n"); 2326 1381 2327 1382 data_t dcache_rdata = 0; 2328 // dcache_cached and dcache_hit don't used with _dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} 2329 bool dcache_cached = dreq_cached [num_cache]; 2330 uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; 2331 bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); 2332 bool dcache_cleanup_hit = r_dcache_cleanup_req[num_cache] and (((addr_40)_dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line[num_cache].read()); 2333 2334 PRINTF(" * <DCACHE [%d]> hit %d - cached %d - cleanup_hit %d\n",num_cache,dcache_hit, dcache_cached, dcache_cleanup_hit); 1383 // dcache_cached and dcache_hit don't used with dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} 1384 bool dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr]; 1385 bool dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); 1386 bool dcache_cleanup_hit = r_dcache_cleanup_req and (((addr_40)dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line.read()); 1387 1388 PRINTF(" * <DCACHE> hit %d - cached %d - cleanup_hit %d\n",dcache_hit, dcache_cached, dcache_cleanup_hit); 2335 1389 2336 1390 m_cpt_dcache_data_read += m_dcache_ways; 2337 1391 m_cpt_dcache_dir_read += m_dcache_ways; 2338 1392 2339 switch( _dreq.type ) {1393 switch( dreq.type ) { 2340 1394 case iss_t::DATA_READ: 2341 1395 case iss_t::DATA_LL: … … 2346 1400 { 2347 1401 // address is in the cache : return the word 2348 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2349 2350 _drsp.valid = true; 2351 _drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) 1402 r_dcache_fsm = DCACHE_IDLE; 1403 drsp.valid = true; 1404 drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) 2352 1405 2353 1406 // if the request is a Load Linked instruction, save request information 2354 if( _dreq.type == iss_t::DATA_LL)1407 if(dreq.type == iss_t::DATA_LL) 2355 1408 { 2356 PRINTF(" * <DCACHE [%d]> ll_valid = true\n",num_cache);2357 2358 r_dcache_ll_valid [num_cache][dcache_num_cpu]= true;2359 r_dcache_ll_data [num_cache][dcache_num_cpu]= dcache_rdata;2360 r_dcache_ll_addr [num_cache][dcache_num_cpu] = (vci_addr_t) _dreq.addr;1409 PRINTF(" * <DCACHE> ll_valid = true\n"); 1410 1411 r_dcache_ll_valid = true; 1412 r_dcache_ll_data = dcache_rdata; 1413 r_dcache_ll_addr = (vci_addr_t) dreq.addr; 2361 1414 #ifdef COHERENCE_DEBUG 2362 std::cout << "Value returned for LL at address : " << std::hex << _dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;2363 r_dcache [num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata);2364 std::cout << "Value stored at this address : " << std::hex << _dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;1415 std::cout << "Value returned for LL at address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; 1416 r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); 1417 std::cout << "Value stored at this address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; 2365 1418 #endif 2366 1419 } … … 2370 1423 if (not dcache_cleanup_hit) 2371 1424 { 1425 CACHE_MISS_BUF_REQ_INIT(d); 2372 1426 2373 1427 // Miss : send signal at the CMD_FSM (via r_dcache_miss_req or r_dcache_unc_req) 2374 1428 if ( dcache_cached ) { 2375 // to prevent deadlock, miss victim don't be block 2376 if (not r_dcache_cleanup_req[num_cache].read()) 1429 m_cpt_data_read_miss++; 1430 m_cost_data_miss_frz++; 1431 r_dcache_miss_req = true; 1432 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1433 r_dcache_fsm = DCACHE_MISS_VICTIM; 1434 #else 1435 r_dcache_fsm = DCACHE_MISS_WAIT; 1436 #endif 1437 1438 } else { 1439 if (not r_dcache_previous_unc.read()) // strongly order to the uncached access 2377 1440 { 2378 CACHE_MISS_BUF_REQ_INIT(d,num_cache); 2379 2380 m_cpt_data_read_miss++; 2381 m_cost_data_miss_frz++; 2382 r_dcache_miss_req [num_cache] = true; 2383 r_dcache_fsm [num_cache] = DCACHE_MISS_VICTIM; 2384 } 2385 else 2386 m_cpt_icache_miss_victim_wait [num_cache] ++; 2387 } else { 2388 if (not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access 2389 { 2390 CACHE_MISS_BUF_REQ_INIT(d,num_cache); 2391 2392 r_dcache_previous_unc[num_cache] = true; 1441 r_dcache_previous_unc = true; 2393 1442 2394 1443 m_cpt_data_read_uncached++; 2395 1444 m_cost_unc_read_frz++; 2396 r_dcache_unc_req [num_cache]= true;2397 r_dcache_fsm [num_cache]= DCACHE_UNC_WAIT;1445 r_dcache_unc_req = true; 1446 r_dcache_fsm = DCACHE_UNC_WAIT; 2398 1447 } 2399 1448 } … … 2404 1453 case iss_t::DATA_SC: 2405 1454 { 2406 PRINTF(" * <DCACHE [%d]> DATA_SC - ll_valid = %d, num_cpu = %d\n",num_cache,r_dcache_ll_valid[num_cache][dcache_num_cpu].read(),dcache_num_cpu);2407 2408 if (not r_dcache_previous_unc [num_cache].read() and not dcache_cleanup_hit) // strongly order to the uncached access1455 PRINTF(" * <DCACHE> DATA_SC - ll_valid = %d\n",r_dcache_ll_valid.read()); 1456 1457 if (not r_dcache_previous_unc.read() and not dcache_cleanup_hit) // strongly order to the uncached access 2409 1458 { 2410 1459 //m_cpt_data_read_unc++; // instruction must read the memory in uncached mode … … 2413 1462 // if previous load linked (with the same address), make a transaction 2414 1463 // else, keep in IDLE state and return 1 (no OK) 2415 if( r_dcache_ll_valid[num_cache][dcache_num_cpu].read() and 2416 (r_dcache_ll_addr [num_cache][dcache_num_cpu].read() == (vci_addr_t)_dreq.addr)){ 2417 PRINTF(" * <DCACHE [%d]> have previous load linked\n",num_cache); 1464 if(r_dcache_ll_valid.read() and (r_dcache_ll_addr.read() == (vci_addr_t)dreq.addr)){ 1465 PRINTF(" * <DCACHE> have previous load linked\n"); 2418 1466 2419 r_dcache_previous_unc[num_cache] = true; 2420 r_dcache_sc_req [num_cache] = true; 2421 2422 CACHE_MISS_BUF_REQ_INIT(d,num_cache); 2423 2424 r_dcache_fsm [num_cache] = DCACHE_SC_WAIT; 1467 r_dcache_previous_unc = true; 1468 1469 r_dcache_sc_req = true; 1470 1471 CACHE_MISS_BUF_REQ_INIT(d); 1472 1473 r_dcache_fsm = DCACHE_SC_WAIT; 2425 1474 } else { 2426 PRINTF(" * <DCACHE [%d]> don't have previous load linked\n",num_cache);1475 PRINTF(" * <DCACHE> don't have previous load linked\n"); 2427 1476 2428 _drsp.valid = true;2429 _drsp.rdata = 1; // SC rsp NOK2430 r_dcache_ll_valid [num_cache][dcache_num_cpu]= false;1477 drsp.valid = true; 1478 drsp.rdata = 1; // SC rsp NOK 1479 r_dcache_ll_valid = false; 2431 1480 } 2432 1481 } … … 2437 1486 case iss_t::XTN_WRITE: 2438 1487 { 2439 bool valid = false;1488 bool drsp_valid = false; 2440 1489 // only DCACHE INVALIDATE and SYNC request are supported 2441 switch ( _dreq.addr>>2)1490 switch (dreq.addr>>2) 2442 1491 { 2443 1492 case iss_t::XTN_DCACHE_INVAL : 2444 1493 { 2445 valid = true;2446 r_dcache_fsm [num_cache]= DCACHE_INVAL;1494 drsp_valid = true; 1495 r_dcache_fsm = DCACHE_INVAL; 2447 1496 break; 2448 1497 } … … 2452 1501 // * gain : 1 cycle 2453 1502 // * cost : can be on the critical path 2454 2455 bool empty=true; 2456 for (uint32_t i=0; i<m_nb_dcache; ++i) 2457 empty &= r_wbuf[i]->empty(); 2458 2459 if (empty) 1503 if (r_wbuf.empty()) 2460 1504 { 2461 valid = true;2462 r_dcache_fsm [num_cache]= DCACHE_IDLE;1505 drsp_valid = true; 1506 r_dcache_fsm = DCACHE_IDLE; 2463 1507 } 2464 1508 else 2465 1509 { 2466 valid = false; 2467 r_dcache_fsm [num_cache] = DCACHE_SYNC; 2468 r_dcache_sync[num_cache] = true; 1510 drsp_valid = false; 1511 r_dcache_fsm = DCACHE_SYNC; 2469 1512 } 2470 1513 break; … … 2473 1516 { 2474 1517 // std::cout << "Warning in VCI_CC_XCACHE_WRAPPER " << name() << std::endl; 2475 // std::cout << "Unsupported external access : " << ( _dreq.addr>>2) << std::endl;2476 2477 r_dcache_fsm [num_cache]= DCACHE_IDLE;1518 // std::cout << "Unsupported external access : " << (dreq.addr>>2) << std::endl; 1519 1520 r_dcache_fsm = DCACHE_IDLE; 2478 1521 } 2479 }//end switch ( _dreq.addr>>2)2480 2481 _drsp.valid =valid;2482 _drsp.rdata = 0;1522 }//end switch (dreq.addr>>2) 1523 1524 drsp.valid = drsp_valid; 1525 drsp.rdata = 0; 2483 1526 break; 2484 1527 } 2485 1528 case iss_t::DATA_WRITE: 2486 1529 2487 PRINTF(" * <DCACHE [%d]> r_dcache_previous_unc : %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); 2488 2489 if (dcache_cached or not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access 1530 if (dcache_cached or not r_dcache_previous_unc.read()) // strongly order to the uncached access 2490 1531 { 2491 bool valid; 2492 addr_40 addr = _dreq.addr; 2493 set_num_dcache(addr,num_cache); 2494 2495 // FIXME : 2496 // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) 2497 // * pour cela, virer le set_num_dcache ! 2498 valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); 2499 PRINTF(" * <DCACHE [%d]> r_wbuf valid : %d\n",num_cache,valid); 2500 2501 if (valid) 1532 bool drsp_valid; 1533 1534 drsp_valid = r_wbuf.write((addr_40) dreq.addr, dreq.be, dreq.wdata, dcache_cached); 1535 1536 if (drsp_valid) 2502 1537 { 2503 1538 m_cpt_data_write++; … … 2505 1540 if (not dcache_cached) 2506 1541 { 2507 r_dcache_previous_unc [num_cache]= true;1542 r_dcache_previous_unc = true; 2508 1543 m_cpt_data_write_uncached++; 2509 1544 } … … 2511 1546 m_cpt_data_write_miss++; 2512 1547 2513 if (dcache_hit) { 2514 // update data cache 2515 r_dcache_fsm[num_cache] = DCACHE_WRITE_UPDT; 1548 if ( dcache_hit) { 1549 r_dcache_fsm = DCACHE_WRITE_UPDT; 2516 1550 } else { 2517 // write accepted 2518 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1551 r_dcache_fsm = DCACHE_IDLE; 2519 1552 } 2520 1553 } 2521 1554 2522 _drsp.valid =valid;2523 _drsp.rdata = 0;1555 drsp.valid = drsp_valid; 1556 drsp.rdata = 0; 2524 1557 } 2525 1558 break; 2526 } // end switch _dreq.type 2527 2528 r_dcache_addr_save [num_cache] = (addr_40) _dreq.addr; 2529 r_dcache_type_save [num_cache] = _dreq.type; 2530 r_dcache_wdata_save [num_cache] = _dreq.wdata; 2531 r_dcache_be_save [num_cache] = _dreq.be; 2532 r_dcache_rdata_save [num_cache] = dcache_rdata; 2533 r_dcache_cached_save [num_cache] = dcache_cached; 2534 r_dcache_num_cpu_save[num_cache] = dcache_num_cpu; 2535 2536 } else { // end if _dreq.valid 2537 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1559 } // end switch dreq.type 1560 1561 r_dcache_addr_save = (addr_40) dreq.addr; 1562 r_dcache_type_save = dreq.type; 1563 r_dcache_wdata_save = dreq.wdata; 1564 r_dcache_be_save = dreq.be; 1565 r_dcache_rdata_save = dcache_rdata; 1566 r_dcache_cached_save = dcache_cached; 1567 1568 } else { // end if dreq.valid 1569 r_dcache_fsm = DCACHE_IDLE; 2538 1570 } 2539 1571 … … 2544 1576 { 2545 1577 m_cpt_dcache_data_write++; 2546 data_t mask = vci_param::be2mask(r_dcache_be_save[num_cache]); 2547 data_t wdata = (mask & r_dcache_wdata_save[num_cache]) | (~mask & r_dcache_rdata_save[num_cache]); 2548 vci_addr_t ad = r_dcache_addr_save[num_cache].read(); 2549 r_dcache[num_cache]->write(ad, wdata); 2550 2551 int dcache_fsm_next = DCACHE_IDLE; // default 2552 2553 #if CC_XCACHE_WRAPPER_STORE_AFTER_STORE 2554 // Test if write after write 2555 2556 if (_dreq.valid and (_dreq.type == iss_t::DATA_WRITE)) 2557 { 2558 PRINTF(" * <DCACHE [%d]> Have dreq (Write after Write)\n",num_cache); 2559 2560 data_t dcache_rdata = 0; 2561 // dcache_cached and dcache_hit don't used with _dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} 2562 bool dcache_cached = dreq_cached [num_cache]; 2563 uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; 2564 bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); 2565 2566 m_cpt_dcache_data_read += m_dcache_ways; 2567 m_cpt_dcache_dir_read += m_dcache_ways; 2568 2569 PRINTF(" * <DCACHE [%d]> r_dcache_previous_unc : %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); 2570 2571 if (dcache_cached or not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access 2572 { 2573 bool valid; 2574 addr_40 addr = _dreq.addr; 2575 set_num_dcache(addr,num_cache); 2576 2577 // FIXME : 2578 // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) 2579 // * pour cela, virer le set_num_dcache ! 2580 valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); 2581 PRINTF(" * <DCACHE [%d]> r_wbuf valid : %d\n",num_cache,valid); 2582 2583 if (valid) 2584 { 2585 m_cpt_dcache_store_after_store [num_cache] ++; 2586 2587 m_cpt_data_write++; 2588 2589 if (not dcache_cached) 2590 { 2591 r_dcache_previous_unc[num_cache] = true; 2592 m_cpt_data_write_uncached++; 2593 } 2594 else if (not dcache_hit) 2595 m_cpt_data_write_miss++; 2596 2597 if (dcache_hit) { 2598 // update data cache 2599 dcache_fsm_next = DCACHE_WRITE_UPDT; 2600 } else { 2601 // write accepted 2602 dcache_fsm_next = DCACHE_IDLE; 2603 } 2604 } 2605 2606 _drsp.valid = valid; 2607 _drsp.rdata = 0; 2608 } 2609 2610 r_dcache_addr_save [num_cache] = (addr_40) _dreq.addr; 2611 // r_dcache_type_save [num_cache] = _dreq.type; 2612 r_dcache_wdata_save [num_cache] = _dreq.wdata; 2613 r_dcache_be_save [num_cache] = _dreq.be; 2614 r_dcache_rdata_save [num_cache] = dcache_rdata; 2615 // r_dcache_cached_save [num_cache] = dcache_cached; 2616 // r_dcache_num_cpu_save[num_cache] = dcache_num_cpu; 2617 } 2618 #endif 2619 2620 r_dcache_fsm [num_cache] = dcache_fsm_next; // default 1578 data_t mask = vci_param::be2mask(r_dcache_be_save); 1579 data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save); 1580 vci_addr_t ad = r_dcache_addr_save.read(); 1581 r_dcache.write(ad, wdata); 1582 1583 r_dcache_fsm = DCACHE_IDLE; 2621 1584 2622 1585 break; 2623 1586 } 2624 1587 ////////////////////// 1588 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 2625 1589 case DCACHE_MISS_VICTIM: 2626 1590 { 2627 // if (not r_dcache_cleanup_req[num_cache].read())1591 if (not r_dcache_cleanup_req.read()) 2628 1592 { 2629 1593 size_t way; 2630 1594 size_t set; 2631 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save [num_cache].read();1595 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save.read(); 2632 1596 vci_addr_t victim; 2633 bool victim_val = r_dcache[num_cache]->victim_select(addr, &victim, &way, &set );2634 1597 2635 r_dcache_cleanup_req [num_cache] = victim_val; 2636 r_dcache_cleanup_line [num_cache] = (addr_40) victim; 2637 r_dcache_miss_way [num_cache] = way; 2638 r_dcache_miss_set [num_cache] = set; 2639 2640 PRINTF(" * <DCACHE [%d]> MISS_VICTIM : Victim %d - %llx (way %d, set %d)\n",num_cache,victim_val, (blob_t)victim, (int)way, (int)set); 2641 2642 r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT; 1598 r_dcache_cleanup_req = r_dcache.victim_select(addr, &victim, &way, &set ); 1599 r_dcache_cleanup_line = (addr_40) victim; 1600 r_dcache_miss_way = way; 1601 r_dcache_miss_set = set; 1602 1603 r_dcache_fsm = DCACHE_MISS_WAIT; 2643 1604 } 2644 1605 2645 1606 break; 2646 1607 } 1608 #endif 2647 1609 ////////////////////// 2648 1610 case DCACHE_MISS_WAIT: 2649 1611 { 2650 #if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 2651 data_t dcache_rdata = 0; 2652 bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); 2653 // bool dcache_cached = dreq_cached [num_cache]; 2654 // uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; 2655 2656 m_cpt_dcache_data_read += m_dcache_ways; 2657 m_cpt_dcache_dir_read += m_dcache_ways; 2658 2659 if (_dreq.valid) 2660 switch (_dreq.type) 2661 { 2662 case iss_t::DATA_READ : // accept only hit dcache load 2663 { 2664 m_cpt_data_read++; // new dcache read 2665 2666 if (dcache_hit) // no special test for uncached read, because it's always miss 2667 { 2668 m_cpt_dcache_hit_after_miss_read [num_cache] ++; 2669 2670 // address is in the cache : return the word 2671 _drsp.valid = true; 2672 _drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) 2673 } 2674 break; 2675 } 2676 // case iss_t::DATA_WRITE : // accept only cached write and miss in dcache (else need update dcache) 2677 // { 2678 // if (dcache_cached and not dcache_hit) 2679 // { 2680 // bool valid; 2681 // addr_40 addr = _dreq.addr; 2682 // set_num_dcache(addr,num_cache); 2683 2684 // // FIXME : 2685 // // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) 2686 // // * pour cela, virer le set_num_dcache ! 2687 // valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); 2688 // PRINTF(" * <DCACHE [%d]> r_wbuf valid : %d\n",num_cache,valid); 2689 2690 // if (valid) 2691 // { 2692 // m_cpt_dcache_hit_after_miss_write [num_cache] ++; 2693 2694 // m_cpt_data_write++; 2695 // m_cpt_data_write_miss++; 2696 // } 2697 2698 // _drsp.valid = valid; 2699 // _drsp.rdata = 0; 2700 // } 2701 // break; 2702 // } 2703 default : 2704 { 2705 break; 2706 } 2707 } 2708 #endif 2709 2710 // if ( _dreq.valid ) m_cost_data_miss_frz++; 2711 if ( r_tgt_dcache_req[num_cache].read() ) { // external request 2712 r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; 2713 r_dcache_fsm_save [num_cache] = r_dcache_fsm[num_cache]; 1612 1613 if ( dreq.valid ) m_cost_data_miss_frz++; 1614 if ( r_tgt_dcache_req.read() ) { // external request 1615 r_dcache_fsm = DCACHE_CC_CHECK; 1616 r_dcache_fsm_save = r_dcache_fsm; 2714 1617 break; 2715 1618 } 2716 1619 2717 bool val = CACHE_MISS_BUF_RSP_VAL(d, num_cache,0);1620 bool val = CACHE_MISS_BUF_RSP_VAL(d,0); 2718 1621 if (val) 2719 1622 { 1623 // if (not r_dcache_inval_rsp ) 1624 // { 1625 2720 1626 // Miss read response and no invalidation 2721 if ( r_vci_rsp_data_error[num_cache])1627 if ( r_vci_rsp_data_error ) 2722 1628 { 2723 r_dcache_fsm [num_cache]= DCACHE_ERROR;1629 r_dcache_fsm = DCACHE_ERROR; 2724 1630 } 2725 1631 else 2726 1632 { 2727 r_dcache_update_addr[num_cache] = 0; 2728 r_dcache_fsm [num_cache] = DCACHE_MISS_UPDT; 1633 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM 1634 if (not r_dcache_cleanup_req.read()) 1635 #endif 1636 { 1637 r_dcache_update_addr = 0; 1638 r_dcache_fsm = DCACHE_MISS_UPDT; 1639 } 2729 1640 } 1641 // } 1642 // else 1643 // { 1644 // r_dcache_inval_rsp = false; 1645 1646 // // Miss read response and invalidation 1647 // if ( r_vci_rsp_data_error ) { 1648 // r_dcache_fsm = DCACHE_ERROR; 1649 // } else { 1650 // r_dcache_fsm = DCACHE_CC_CLEANUP; 1651 // } 1652 // } 2730 1653 } 2731 1654 break; … … 2734 1657 case DCACHE_MISS_UPDT: 2735 1658 { 2736 size_t word = r_dcache_update_addr [num_cache].read();2737 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save [num_cache].read();2738 size_t way = r_dcache_miss_way[num_cache].read();2739 size_t set = r_dcache_miss_set[num_cache].read();1659 size_t word = r_dcache_update_addr.read(); 1660 vci_addr_t addr = (vci_addr_t) r_dcache_addr_save.read(); 1661 size_t way = 0; 1662 size_t set = 0; 2740 1663 2741 PRINTF(" * <DCACHE [%d]> MISS_UPDT : Victim way %d, set %d\n",num_cache, (int)way, (int)set); 2742 2743 if (CACHE_MISS_BUF_RSP_VAL(d,num_cache,word)) 1664 // need invalid rsp, don't select a victim 1665 if (not r_dcache_inval_rsp ) 1666 { 1667 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1668 way = r_dcache_miss_way.read(); 1669 set = r_dcache_miss_set.read(); 1670 #else 1671 // First word : select an victim ! 1672 if (word == 0) 1673 { 1674 vci_addr_t victim; 1675 1676 // r_dcache_cleanup_req is false (condition to enter in DCACHE_MISS_UPDT 1677 r_dcache_cleanup_req = r_dcache.victim_select(addr, &victim, &way, &set ); 1678 r_dcache.victim_update_tag(addr, way, set); 1679 r_dcache_cleanup_line = (addr_40) victim; 1680 1681 r_dcache_miss_way = way; 1682 r_dcache_miss_set = set; 1683 } 1684 else 1685 { 1686 way = r_dcache_miss_way.read(); 1687 set = r_dcache_miss_set.read(); 1688 } 1689 #endif 1690 } 1691 1692 bool val = CACHE_MISS_BUF_RSP_VAL(d,word); 1693 if (val) 2744 1694 { 2745 1695 // m_cpt_dcache_dir_write++; 2746 // if ( _dreq.valid ) m_cost_data_miss_frz++;1696 // if ( ireq.valid ) m_cost_data_miss_frz++; 2747 1697 2748 1698 // if need invalid rsp, don't modify the cache, but pop the buf_rsp 2749 // (power save) 2750 if (not r_dcache_inval_rsp[num_cache]) 1699 if (not r_dcache_inval_rsp ) 2751 1700 { 2752 r_dcache [num_cache]->write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,num_cache,word));1701 r_dcache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,word)); 2753 1702 m_cpt_dcache_data_write++; 2754 1703 } 2755 1704 2756 CACHE_MISS_BUF_RSP_POP(d ,num_cache);2757 r_dcache_update_addr [num_cache]= ++word;1705 CACHE_MISS_BUF_RSP_POP(d); 1706 r_dcache_update_addr = ++word; 2758 1707 2759 1708 // if last word, finish the update 2760 1709 if (word >= m_dcache_words) 2761 1710 { 2762 // in all case (inval_rsp or not), update the victim tag2763 // because victim is already cleanup2764 r_dcache[num_cache]->victim_update_tag(addr, way, set);2765 2766 1711 // Last word : if previous invalid_rsp, can cleanup, else update the TAG 2767 if (r_dcache_inval_rsp [num_cache])1712 if (r_dcache_inval_rsp) 2768 1713 { 2769 r_dcache_inval_rsp [num_cache]= false;2770 r_dcache_fsm [num_cache]= DCACHE_CC_CLEANUP;1714 r_dcache_inval_rsp = false; 1715 r_dcache_fsm = DCACHE_CC_CLEANUP; 2771 1716 } 2772 1717 else 2773 1718 { 2774 r_dcache_fsm [num_cache] = DCACHE_IDLE; 1719 #if CC_XCACHE_WRAPPER_SELECT_VICTIM 1720 r_dcache.victim_update_tag(addr, way, set); 1721 #endif 1722 r_dcache_fsm = DCACHE_IDLE; 2775 1723 } 2776 1724 } … … 2782 1730 case DCACHE_UNC_WAIT: 2783 1731 { 2784 // if ( _dreq.valid ) m_cost_unc_read_frz++;2785 if ( r_tgt_dcache_req [num_cache]) { // external request2786 r_dcache_fsm [num_cache]= DCACHE_CC_CHECK;2787 r_dcache_fsm_save [num_cache] = r_dcache_fsm[num_cache];1732 if ( dreq.valid ) m_cost_unc_read_frz++; 1733 if ( r_tgt_dcache_req ) { // external request 1734 r_dcache_fsm = DCACHE_CC_CHECK; 1735 r_dcache_fsm_save = r_dcache_fsm; 2788 1736 break; 2789 1737 } 2790 1738 2791 bool ok = CACHE_MISS_BUF_RSP_VAL(d, num_cache,0);1739 bool ok = CACHE_MISS_BUF_RSP_VAL(d,0); 2792 1740 2793 1741 if (ok) { 2794 if ( r_vci_rsp_data_error[num_cache]) {2795 r_dcache_fsm [num_cache]= DCACHE_ERROR;1742 if ( r_vci_rsp_data_error ) { 1743 r_dcache_fsm = DCACHE_ERROR; 2796 1744 } else { 2797 data_t rdata = CACHE_MISS_BUF_RSP_DATA(d, num_cache,0);2798 CACHE_MISS_BUF_RSP_POP(d ,num_cache);2799 2800 if( _dreq.type == iss_t::DATA_LL){2801 PRINTF(" * <DCACHE [%d]> ll_valid = true\n",num_cache);2802 2803 r_dcache_ll_valid [num_cache][r_dcache_num_cpu_save[num_cache]]= true;2804 r_dcache_ll_data [num_cache][r_dcache_num_cpu_save[num_cache]]= rdata;2805 r_dcache_ll_addr [num_cache][r_dcache_num_cpu_save[num_cache]] = (vci_addr_t) _dreq.addr;1745 data_t rdata = CACHE_MISS_BUF_RSP_DATA(d,0); 1746 CACHE_MISS_BUF_RSP_POP(d); 1747 1748 if(dreq.type == iss_t::DATA_LL){ 1749 PRINTF(" * <DCACHE> ll_valid = true\n"); 1750 1751 r_dcache_ll_valid = true; 1752 r_dcache_ll_data = rdata; 1753 r_dcache_ll_addr = (vci_addr_t) dreq.addr; 2806 1754 } 2807 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2808 2809 _drsp.valid = true; 2810 _drsp.rdata = rdata; 1755 r_dcache_fsm = DCACHE_IDLE; 1756 drsp.valid = true; 1757 drsp.rdata = rdata; 2811 1758 } 2812 1759 } … … 2816 1763 case DCACHE_SC_WAIT: 2817 1764 { 2818 // if ( _dreq.valid ) m_cost_unc_read_frz++;2819 if ( r_tgt_dcache_req [num_cache]) { // external request2820 r_dcache_fsm [num_cache]= DCACHE_CC_CHECK;2821 r_dcache_fsm_save [num_cache] = r_dcache_fsm [num_cache];1765 if ( dreq.valid ) m_cost_unc_read_frz++; 1766 if ( r_tgt_dcache_req ) { // external request 1767 r_dcache_fsm = DCACHE_CC_CHECK; 1768 r_dcache_fsm_save = r_dcache_fsm; 2822 1769 break; 2823 1770 } 2824 1771 2825 bool ok = CACHE_MISS_BUF_RSP_VAL(d, num_cache,0);1772 bool ok = CACHE_MISS_BUF_RSP_VAL(d,0); 2826 1773 2827 1774 if (ok) { 2828 if ( r_vci_rsp_data_error[num_cache]) {2829 r_dcache_fsm [num_cache]= DCACHE_ERROR;1775 if ( r_vci_rsp_data_error ) { 1776 r_dcache_fsm = DCACHE_ERROR; 2830 1777 } else { 2831 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2832 2833 _drsp.valid = true; 2834 _drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,num_cache,0); 2835 CACHE_MISS_BUF_RSP_POP(d,num_cache); 2836 r_dcache_ll_valid [num_cache][r_dcache_num_cpu_save[num_cache]] = false; 1778 r_dcache_fsm = DCACHE_IDLE; 1779 drsp.valid = true; 1780 drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,0); 1781 CACHE_MISS_BUF_RSP_POP(d); 1782 r_dcache_ll_valid = false; 2837 1783 } 2838 1784 } … … 2843 1789 case DCACHE_ERROR: 2844 1790 { 2845 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2846 2847 r_vci_rsp_data_error[num_cache] = false; 2848 _drsp.error = true; 2849 _drsp.valid = true; 1791 r_dcache_fsm = DCACHE_IDLE; 1792 r_vci_rsp_data_error = false; 1793 drsp.error = true; 1794 drsp.valid = true; 2850 1795 break; 2851 1796 } … … 2853 1798 case DCACHE_INVAL: 2854 1799 { 2855 if ( r_tgt_dcache_req [num_cache].read() ) { // external request2856 r_dcache_fsm [num_cache]= DCACHE_CC_CHECK;2857 r_dcache_fsm_save [num_cache] = r_dcache_fsm [num_cache];1800 if ( r_tgt_dcache_req.read() ) { // external request 1801 r_dcache_fsm = DCACHE_CC_CHECK; 1802 r_dcache_fsm_save = r_dcache_fsm; 2858 1803 break; 2859 1804 } 2860 if( not r_dcache_cleanup_req [num_cache].read() ){1805 if( not r_dcache_cleanup_req.read() ){ 2861 1806 m_cpt_dcache_dir_read += m_dcache_ways; 2862 vci_addr_t ad = r_dcache_addr_save [num_cache].read();2863 r_dcache_cleanup_req [num_cache] = r_dcache[num_cache]->inval(ad);2864 r_dcache_cleanup_line [num_cache] = r_dcache_addr_save [num_cache].read() >> m_dcache_words_shift;2865 2866 r_dcache_fsm [num_cache]= DCACHE_IDLE;1807 vci_addr_t ad = r_dcache_addr_save.read(); 1808 r_dcache_cleanup_req = r_dcache.inval(ad); 1809 r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift; 1810 1811 r_dcache_fsm = DCACHE_IDLE; 2867 1812 } 2868 1813 break; … … 2870 1815 case DCACHE_SYNC : 2871 1816 { 2872 if ( r_tgt_dcache_req [num_cache]) { // external request2873 r_dcache_fsm [num_cache]= DCACHE_CC_CHECK;2874 r_dcache_fsm_save [num_cache] = r_dcache_fsm[num_cache];1817 if ( r_tgt_dcache_req ) { // external request 1818 r_dcache_fsm = DCACHE_CC_CHECK; 1819 r_dcache_fsm_save = r_dcache_fsm; 2875 1820 break; 2876 1821 } 2877 1822 2878 bool empty=true; 2879 for (uint32_t i=0; i<m_nb_dcache; ++i) 2880 empty &= r_wbuf[i]->empty(); 2881 2882 if (empty) 2883 { 2884 _drsp.valid = true; // end, can accept the sync request 2885 r_dcache_fsm [num_cache] = DCACHE_IDLE; 2886 r_dcache_sync[num_cache] = false; 2887 } 1823 if (r_wbuf.empty()) 1824 { 1825 drsp.valid = true; // end, can accept the sync request 1826 r_dcache_fsm = DCACHE_IDLE; 1827 } 2888 1828 break; 2889 1829 } … … 2891 1831 case DCACHE_CC_CHECK: // read directory in case of invalidate or update request 2892 1832 { 2893 addr_40 ad = r_tgt_ daddr;1833 addr_40 ad = r_tgt_addr; 2894 1834 data_t dcache_rdata = 0; 2895 1835 2896 PRINTF(" * <DCACHE [%d]> CC_CHECK\n",num_cache); 2897 2898 // 2899 if((r_dcache_fsm_save[num_cache] == DCACHE_MISS_WAIT) and 2900 ((r_dcache_addr_save[num_cache].read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { 2901 PRINTF(" * <DCACHE [%d]> have request, need inval rsp\n",num_cache); 2902 2903 r_dcache_inval_rsp[num_cache] = true; 2904 r_tgt_dcache_req [num_cache] = false; 1836 if((r_dcache_fsm_save == DCACHE_MISS_WAIT) and 1837 ( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { 1838 r_dcache_inval_rsp = true; 1839 r_tgt_dcache_req = false; 2905 1840 if(r_tgt_update){ // Also send a cleanup and answer 2906 PRINTF(" * <DCACHE [%d]> send a cleanup and answer\n",num_cache); 2907 r_tgt_dcache_rsp[num_cache] = true; 1841 r_tgt_dcache_rsp = true; 2908 1842 } else { // Also send a cleanup but don't answer 2909 PRINTF(" * <DCACHE [%d]> send a cleanup and but don't answer\n",num_cache); 2910 r_tgt_dcache_rsp[num_cache] = false; 1843 r_tgt_dcache_rsp = false; 2911 1844 } 2912 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache];1845 r_dcache_fsm = r_dcache_fsm_save; 2913 1846 } else { 2914 bool dcache_hit = r_dcache[num_cache]->read(ad, &dcache_rdata); 2915 2916 PRINTF(" * <DCACHE [%d]> have no request, hit cache : %d, update : %d\n",num_cache,dcache_hit,(uint32_t)r_tgt_update); 1847 bool dcache_hit = r_dcache.read(ad, &dcache_rdata); 2917 1848 2918 1849 m_cpt_dcache_data_read += m_dcache_ways; … … 2929 1860 data_t rdata = 0; 2930 1861 2931 r_dcache [num_cache]->read(ad+word*4,&rdata);1862 r_dcache.read(ad+word*4,&rdata); 2932 1863 2933 1864 r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); … … 2942 1873 if (word==m_dcache_words) 2943 1874 { 2944 r_dcache_fsm [num_cache]= DCACHE_CC_UPDT;1875 r_dcache_fsm = DCACHE_CC_UPDT; 2945 1876 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 2946 1877 for (word=0; word<m_dcache_words; ++word) … … 2956 1887 for(size_t i=0; i<m_dcache_words; i++){ 2957 1888 data_t rdata = 0; 2958 r_dcache [num_cache]->read(ad + i*4,&rdata);1889 r_dcache.read(ad + i*4,&rdata); 2959 1890 data_t mask = vci_param::be2mask(r_tgt_be[i]); 2960 1891 r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata); 2961 1892 } 2962 r_dcache_fsm [num_cache]= DCACHE_CC_UPDT;1893 r_dcache_fsm = DCACHE_CC_UPDT; 2963 1894 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 2964 1895 } else if ( dcache_hit and not r_tgt_update ) { 2965 r_dcache_fsm [num_cache]= DCACHE_CC_INVAL;1896 r_dcache_fsm = DCACHE_CC_INVAL; 2966 1897 } else { 2967 1898 if(r_tgt_update){ 2968 r_tgt_dcache_rsp [num_cache]= true;1899 r_tgt_dcache_rsp = true; 2969 1900 } else { 2970 r_tgt_dcache_rsp [num_cache]= false;1901 r_tgt_dcache_rsp = false; 2971 1902 } 2972 r_tgt_dcache_req [num_cache]= false;2973 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache];1903 r_tgt_dcache_req = false; 1904 r_dcache_fsm = r_dcache_fsm_save; 2974 1905 } 2975 1906 } … … 2979 1910 case DCACHE_CC_UPDT: // update directory and data cache 2980 1911 { 2981 addr_40 ad = r_tgt_ daddr;1912 addr_40 ad = r_tgt_addr; 2982 1913 2983 1914 m_cpt_dcache_dir_write++; … … 2992 1923 2993 1924 if(r_tgt_be[word]) 2994 r_dcache [num_cache]->write(ad+word*4, r_tgt_buf[word]);1925 r_dcache.write(ad+word*4, r_tgt_buf[word]); 2995 1926 # ifdef COHERENCE_DEBUG 2996 1927 std::cout << " address " << std::hex << ad+word*4 << " data " << std::dec << r_tgt_buf[word] << std::endl; 2997 1928 data_t rdata = 0xAAAAAAAA; 2998 r_dcache [num_cache]->read(ad+word*4,&rdata);1929 r_dcache.read(ad+word*4,&rdata); 2999 1930 std::cout << "data written " << rdata << std::endl; 3000 1931 # endif … … 3009 1940 if (word==m_dcache_words) 3010 1941 { 3011 r_tgt_dcache_req [num_cache]= false;3012 r_tgt_dcache_rsp [num_cache]= true;3013 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache];1942 r_tgt_dcache_req = false; 1943 r_tgt_dcache_rsp = true; 1944 r_dcache_fsm = r_dcache_fsm_save; 3014 1945 word = 0; 3015 1946 } … … 3019 1950 for(size_t i=0; i<m_dcache_words; i++){ 3020 1951 if(r_tgt_be[i]) { 3021 r_dcache [num_cache]->write( ad + i*4, buf[i]);1952 r_dcache.write( ad + i*4, buf[i]); 3022 1953 # ifdef COHERENCE_DEBUG 3023 1954 std::cout << " address " << std::hex << ad+i*4 << " data " << std::dec << buf[i] << std::endl; 3024 1955 data_t rdata = 0xAAAAAAAA; 3025 r_dcache [num_cache]->read(ad + i*4,&rdata);1956 r_dcache.read(ad + i*4,&rdata); 3026 1957 std::cout << "data written " << rdata << std::endl; 3027 1958 # endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 3028 1959 } 3029 1960 } 3030 r_tgt_dcache_req [num_cache]= false;3031 r_tgt_dcache_rsp [num_cache]= true;3032 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache];1961 r_tgt_dcache_req = false; 1962 r_tgt_dcache_rsp = true; 1963 r_dcache_fsm = r_dcache_fsm_save; 3033 1964 #endif 3034 1965 break; … … 3037 1968 case DCACHE_CC_INVAL: // invalidate a cache line 3038 1969 { 3039 addr_40 ad = r_tgt_ daddr;3040 r_tgt_dcache_rsp [num_cache]= true;3041 r_dcache [num_cache]->inval(ad);3042 r_tgt_dcache_req [num_cache]= false;3043 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache];1970 addr_40 ad = r_tgt_addr; 1971 r_tgt_dcache_rsp = true; 1972 r_dcache.inval(ad); 1973 r_tgt_dcache_req = false; 1974 r_dcache_fsm = r_dcache_fsm_save; 3044 1975 break; 3045 1976 } … … 3047 1978 case DCACHE_CC_CLEANUP: 3048 1979 { 1980 // external cache invalidate request 1981 if ( r_tgt_dcache_req ) 1982 { 1983 r_dcache_fsm = DCACHE_CC_CHECK; 1984 r_dcache_fsm_save = r_dcache_fsm; 1985 break; 1986 } 3049 1987 // cleanup 3050 if(not r_dcache_cleanup_req[num_cache]){ 3051 r_dcache_cleanup_req [num_cache] = true; 3052 r_dcache_cleanup_line [num_cache] = r_dcache_addr_save[num_cache].read() >> m_dcache_words_shift; 3053 r_dcache_fsm [num_cache] = DCACHE_IDLE; 3054 3055 m_cpt_dcache_dir_read += m_dcache_ways; 3056 r_dcache[num_cache]->inval((addr_40)r_dcache_addr_save[num_cache]); 1988 if(not r_dcache_cleanup_req){ 1989 r_dcache_cleanup_req = true; 1990 r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift; 1991 r_dcache_fsm = DCACHE_IDLE; 3057 1992 } 3058 1993 break; … … 3064 1999 // The update() method must be called at each cycle to update the internal state. 3065 2000 // All pending write requests must be locked in case of SYNC 3066 3067 // bool have_sync=(r_dcache_fsm[num_cache] == DCACHE_SYNC); 2001 bool wbuf_flush=(r_dcache_fsm == DCACHE_SYNC); 3068 2002 #if (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==1) 3069 r_wbuf [num_cache]->update_multi_scan (have_sync);2003 r_wbuf.update_multi_scan (wbuf_flush); 3070 2004 #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==2) 3071 r_wbuf [num_cache]->update_round_robin_scan(have_sync);2005 r_wbuf.update_round_robin_scan(wbuf_flush); 3072 2006 #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==3) 3073 r_wbuf [num_cache]->update_one_scan (have_sync);2007 r_wbuf.update_one_scan (wbuf_flush); 3074 2008 #else 3075 r_wbuf[num_cache]->update (have_sync); 3076 #endif 3077 3078 drsp [num_cache] = _drsp; 3079 if (_dreq.valid and _drsp.valid) 2009 r_wbuf.update (wbuf_flush); 2010 #endif 2011 2012 #if CC_XCACHE_WRAPPER_DEBUG 2013 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 2014 std::cout << " * Data Response : " << drsp << std::endl; 2015 #endif 2016 2017 /////////// execute one iss cycle ///////////////////////////////////////////// 3080 2018 { 3081 PRINTF(" * <CPU2CACHE> Transaction between cpu %d and Dcache %d (unlock)\n",r_dcache_lock [num_cache].read(),num_cache);3082 3083 r_dcache_lock [num_cache] = m_nb_cpu;3084 m_ cpt_dcache_access [num_cache] ++;2019 uint32_t it = 0; 2020 for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 2021 if(p_irq[i].read()) it |= (1<<i); 2022 m_iss.executeNCycles(1, irsp, drsp, it); 3085 2023 } 3086 2024 3087 }// end for num_cache 3088 3089 /////////// execute one iss cycle ///////////////////////////////////////////// 3090 3091 for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu) 2025 if ( (ireq.valid and not irsp.valid) or 2026 (dreq.valid and not drsp.valid)) 3092 2027 { 3093 // Test if the resquest is accepted 3094 typename iss_t::InstructionResponse _irsp = ISS_IRSP_INITIALIZER; 3095 typename iss_t::DataResponse _drsp = ISS_DRSP_INITIALIZER; 3096 3097 if (ireq_num_cache[num_cpu]<m_nb_icache) 3098 _irsp = irsp[ireq_num_cache[num_cpu]]; 3099 if (dreq_num_cache[num_cpu]<m_nb_dcache) 3100 _drsp = drsp[dreq_num_cache[num_cpu]]; 3101 3102 #if CC_XCACHE_WRAPPER_STOP_SIMULATION or CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3103 typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER; 3104 typename iss_t::DataRequest _dreq = ISS_DREQ_INITIALIZER; 3105 3106 if (ireq_num_cache[num_cpu]<m_nb_icache) 3107 _ireq = ireq[ireq_num_cache[num_cpu]]; 3108 if (dreq_num_cache[num_cpu]<m_nb_dcache) 3109 _dreq = dreq[dreq_num_cache[num_cpu]]; 3110 #endif 3111 3112 #if CC_XCACHE_WRAPPER_DEBUG 3113 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 2028 m_cpt_frz_cycles++; 2029 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 2030 m_stop_simulation_nb_frz_cycles ++; 2031 2032 if (m_stop_simulation and (m_stop_simulation_nb_frz_cycles >= m_stop_simulation_nb_frz_cycles_max)) 3114 2033 { 3115 3116 std::cout << " * CPU : " << num_cpu << std::endl 3117 << " * Instruction Cache : " << ireq_num_cache[num_cpu] << ", valid : " << (ireq_num_cache[num_cpu]<m_nb_icache) << std::endl 3118 << " * Instruction Request : " << _ireq << std::endl 3119 << " * Instruction Response : " << _irsp << std::endl 3120 << " * Data Cache : " << dreq_num_cache[num_cpu] << ", valid : " << (dreq_num_cache[num_cpu]<m_nb_dcache) << std::endl 3121 << " * Data Request : " << _dreq << std::endl 3122 << " * Data Response : " << _drsp << std::endl; 2034 std::cout << std::dec << "CC_XCACHE_WRAPPER \"" << name() << "\" : cycle " << m_cpt_total_cycles << ", the cpu is frozen since " << m_stop_simulation_nb_frz_cycles << " cycles." << std::endl; 2035 ASSERT(false,"CPU : anormal activity"); // exit 3123 2036 } 3124 #endif 3125 3126 if ((_ireq.valid and not _irsp.valid) or 3127 (_dreq.valid and not _drsp.valid)) 3128 { 3129 m_cpt_frz_cycles [num_cpu]++; 3130 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 3131 m_stop_simulation_nb_frz_cycles [num_cpu]++; 3132 3133 if (m_stop_simulation and (m_stop_simulation_nb_frz_cycles [num_cpu]>= m_stop_simulation_nb_frz_cycles_max)) 3134 { 3135 std::cout << std::dec << "CC_XCACHE_WRAPPER \"" << name() << "\" (" << num_cpu << ") : cycle " << m_cpt_total_cycles << ", the cpu is frozen since " << m_stop_simulation_nb_frz_cycles [num_cpu]<< " cycles." << std::endl; 3136 ASSERT(false,"CPU : anormal activity"); // exit 3137 } 3138 } 3139 else 3140 { 3141 m_stop_simulation_nb_frz_cycles [num_cpu] = 0; // reinit counter 2037 } 2038 else 2039 { 2040 m_stop_simulation_nb_frz_cycles = 0; // reinit counter 3142 2041 #endif //CC_XCACHE_WRAPPER_STOP_SIMULATION 3143 } 3144 3145 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3146 if (_ireq.valid and _irsp.valid) 3147 { 3148 log_transaction_file_icache [num_cpu] 3149 << "[" << m_cpt_total_cycles << "]" 3150 << std::hex 3151 << " @ " << std::setw(8) << (uint32_t)_ireq.addr 3152 << " (" << std::setw(8) << (uint32_t)set_num_icache_only(_ireq.addr,ireq_num_cache[num_cpu]) 3153 << " - L " << std::setw(8) <<((uint32_t)set_num_icache_only(_ireq.addr,ireq_num_cache[num_cpu])&m_icache_yzmask) << ")" 3154 << " I " << std::setw(8) << (uint32_t)_irsp.instruction 3155 << " error " << (uint32_t)_irsp.error 3156 << std::dec 3157 << std::endl; 3158 } 3159 3160 if (_dreq.valid and _drsp.valid) 3161 { 3162 log_transaction_file_dcache [num_cpu] 3163 << "[" << m_cpt_total_cycles << "]" 3164 << std::hex 3165 << " @ " << std::setw(8) << (uint32_t)_dreq.addr 3166 << " (" << std::setw(8) << (uint32_t)set_num_dcache_only(_dreq.addr,dreq_num_cache[num_cpu]) 3167 << " - L " << std::setw(8) <<((uint32_t)set_num_dcache_only(_dreq.addr,dreq_num_cache[num_cpu])&m_dcache_yzmask) << ")" 3168 << " be " << std::setw(1) << (uint32_t)_dreq.be 3169 << " W " << std::setw(8) << (uint32_t)_dreq.wdata 3170 << " R " << std::setw(8) << (uint32_t)_drsp.rdata 3171 << " error " << (uint32_t)_drsp.error 3172 << std::dec 3173 << " " << type_str(_dreq.type); 3174 3175 if ((_dreq.type == iss_t::XTN_READ) or 3176 (_dreq.type == iss_t::XTN_WRITE)) 3177 //log_transaction_file_dcache [num_cpu] << xtn_str(_dreq.addr>>2); 3178 switch (_dreq.addr>>2) 3179 { 3180 case iss_t::XTN_DCACHE_INVAL : log_transaction_file_dcache [num_cpu]<< " INVAL"; break; 3181 case iss_t::XTN_SYNC : log_transaction_file_dcache [num_cpu]<< " SYNC"; break; 3182 default : log_transaction_file_dcache [num_cpu]<< " invalid"; break; 3183 } 3184 3185 log_transaction_file_dcache [num_cpu]<< std::endl; 3186 } 3187 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3188 3189 { 3190 uint32_t it = 0; 3191 for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 3192 if(p_irq[num_cpu][i].read()) it |= (1<<i); 3193 3194 m_iss[num_cpu]->executeNCycles(1, _irsp, _drsp, it); 3195 } 3196 }//end num_cpu 2042 } 2043 2044 2045 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 2046 if (dreq.valid and drsp.valid) 2047 { 2048 log_dcache_transaction_file 2049 << "[" << m_cpt_total_cycles << "]" 2050 << std::hex 2051 << " @ " << std::setw(8) << (uint32_t)dreq.addr 2052 << " be " << std::setw(1) << (uint32_t)dreq.be 2053 << " W " << std::setw(8) << (uint32_t)dreq.wdata 2054 << " R " << std::setw(8) << (uint32_t)drsp.rdata 2055 << " error " << (uint32_t)drsp.error 2056 << std::dec 2057 << " " << type_str(dreq.type); 2058 2059 if ((dreq.type == iss_t::XTN_READ) or 2060 (dreq.type == iss_t::XTN_WRITE)) 2061 //log_dcache_transaction_file << xtn_str(dreq.addr>>2); 2062 switch (dreq.addr>>2) 2063 { 2064 case iss_t::XTN_DCACHE_INVAL : log_dcache_transaction_file << " INVAL"; break; 2065 case iss_t::XTN_SYNC : log_dcache_transaction_file << " SYNC"; break; 2066 default : log_dcache_transaction_file << " invalid"; break; 2067 } 2068 2069 log_dcache_transaction_file << std::endl; 2070 2071 // printf("[%d] @ %.8x be %.1x W %.8x R %.8x error %d - %s" 2072 // ,(uint32_t)m_cpt_total_cycles 2073 // ,(uint32_t)dreq.addr 2074 // ,(uint32_t)dreq.be 2075 // ,(uint32_t)dreq.wdata 2076 // ,(uint32_t)drsp.rdata 2077 // ,(uint32_t)drsp.error 2078 // ,type_str(dreq.type)); 2079 // if ((dreq.type == iss_t::XTN_READ) or 2080 // (dreq.type == iss_t::XTN_WRITE)) 2081 // // printf(" %s",xtn_str(dreq.addr>>2)); 2082 // switch (dreq.addr>>2) 2083 // { 2084 // case iss_t::XTN_DCACHE_INVAL : printf(" INVAL"); break; 2085 // case iss_t::XTN_SYNC : printf(" SYNC"); break; 2086 // default : printf(" invalid"); break; 2087 // } 2088 // printf("\n"); 2089 } 2090 #endif //CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 3197 2091 3198 2092 //////////////////////////////////////////////////////////////////////////// … … 3219 2113 3220 2114 case CLEANUP_IDLE: 3221 { 3222 uint32_t num_cache = 0; 3223 bool cleanup_dcache_req = false; 3224 bool cleanup_icache_req = false; 3225 3226 // dcache is prior 3227 for (uint32_t i=0; i<m_nb_dcache; ++i) 3228 { 3229 PRINTF(" * <CLEANUP> dcache_cleanup_req : [%d] %d\n",i,(int)r_dcache_cleanup_req[i]); 3230 cleanup_dcache_req |= r_dcache_cleanup_req[i]; 3231 if (cleanup_dcache_req) 3232 { 3233 PRINTF(" * <CLEANUP> ... find\n"); 3234 num_cache=i; 3235 break; 3236 } 3237 } 3238 3239 if (not cleanup_dcache_req) 3240 for (uint32_t i=0; i<m_nb_icache; ++i) 3241 { 3242 PRINTF(" * <CLEANUP> icache_cleanup_req : [%d] %d\n",i,(int)r_icache_cleanup_req[i]); 3243 3244 cleanup_icache_req |= r_icache_cleanup_req[i]; 3245 if (cleanup_icache_req) 3246 { 3247 PRINTF(" * <CLEANUP> ... find\n"); 3248 num_cache=i; 3249 break; 3250 } 3251 } 3252 3253 PRINTF(" * <CLEANUP> cleanup_icache_req : %d\n",cleanup_icache_req); 3254 PRINTF(" * <CLEANUP> cleanup_dcache_req : %d\n",cleanup_dcache_req); 3255 PRINTF(" * <CLEANUP> num_cache : %d\n",num_cache); 3256 3257 if (cleanup_icache_req or cleanup_dcache_req) 3258 { 3259 r_cleanup_fsm = CLEANUP_REQ; 3260 r_cleanup_icache = cleanup_icache_req; 3261 r_cleanup_num_cache = num_cache; 3262 3263 PRINTF(" * <CLEANUP> address : %llx\n",((cleanup_icache_req)?((blob_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((blob_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache)))); 3264 3265 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3266 log_transaction_file_cleanup 3267 << "[" << m_cpt_total_cycles << "] " 3268 << ((cleanup_icache_req)?("icache "):("dcache ")) 3269 << num_cache << " : " 3270 << std::hex 3271 << " L " << std::setw(10) << ((cleanup_icache_req)?((blob_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((blob_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache))) 3272 // << " (" << std::setw(10) << addr << ")" 3273 << std::dec 3274 << std::endl; 3275 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3276 2115 { 2116 if ( p_vci_ini_c.cmdack ) 2117 { 2118 if (r_dcache_cleanup_req) r_cleanup_fsm = CLEANUP_DCACHE; 2119 else if (r_icache_cleanup_req) r_cleanup_fsm = CLEANUP_ICACHE; 3277 2120 } 3278 2121 break; 3279 2122 } 3280 case CLEANUP_REQ: 3281 { 3282 if ( p_vci_ini_c.cmdack ) 3283 { 3284 if (r_cleanup_icache) 3285 r_cleanup_fsm = CLEANUP_RSP_ICACHE; 3286 else 3287 r_cleanup_fsm = CLEANUP_RSP_DCACHE; 3288 } 3289 break; 3290 } 3291 case CLEANUP_RSP_DCACHE: 2123 case CLEANUP_DCACHE: 3292 2124 { 3293 2125 if ( p_vci_ini_c.rspval ) 3294 2126 { 3295 2127 PRINTF(" * <CLEANUP> rerror : %d (%d)\n",(uint32_t)p_vci_ini_c.rerror.read(),0x2 & ( (1 << vci_param::E) - 1)); 3296 PRINTF(" * <CLEANUP> rpktid : %d, r_cleanup_num_cache : %d\n",(uint32_t)p_vci_ini_c.rpktid.read(), (uint32_t)r_cleanup_num_cache);3297 2128 3298 2129 ASSERT(p_vci_ini_c.reop and (p_vci_ini_c.rtrdid.read() == TYPE_DATA_CLEANUP), 3299 "illegal response packet received for a cleanup transaction");2130 "illegal response packet received for a cleanup transaction"); 3300 2131 ASSERT(p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL, 3301 2132 "error signaled in a cleanup response" ); 3302 ASSERT(p_vci_ini_c.rpktid.read() == (sc_dt::sc_uint<vci_param::P>)r_cleanup_num_cache, 3303 "invalid pktid in a cleanup response"); 3304 2133 3305 2134 r_cleanup_fsm = CLEANUP_IDLE; 3306 r_dcache_cleanup_req [r_cleanup_num_cache]= false;3307 // m_cpt_cc_cleanup_data++; 2135 r_dcache_cleanup_req = false; 2136 // m_cpt_cc_cleanup_data++; TODO 3308 2137 } 3309 2138 break; 3310 2139 } 3311 case CLEANUP_ RSP_ICACHE:2140 case CLEANUP_ICACHE: 3312 2141 { 3313 2142 if ( p_vci_ini_c.rspval ) … … 3321 2150 3322 2151 r_cleanup_fsm = CLEANUP_IDLE; 3323 r_icache_cleanup_req [r_cleanup_num_cache]= false;3324 // m_cpt_cc_cleanup_ins++; 2152 r_icache_cleanup_req = false; 2153 // m_cpt_cc_cleanup_ins++; TODO 3325 2154 } 3326 2155 break; … … 3366 2195 // if (r_vci_rsp_fsm != RSP_IDLE) break; 3367 2196 3368 size_t wbuf_min = 0; 3369 size_t wbuf_max = 0; 3370 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3371 addr_40 wbuf_addr = 0; 3372 size_t wbuf_index = 0; 3373 #endif 2197 size_t min; 2198 size_t max; 2199 3374 2200 r_vci_cmd_cpt = 0; 3375 2201 … … 3378 2204 // multi_write_buffer access is conditionnal with dcache_miss_req and icache_miss_req 3379 2205 3380 bool dcache_miss_req = false;3381 bool icache_miss_req = false;3382 uint32_t dcache_miss_num_cache = 0;3383 uint32_t icache_miss_num_cache = 0;3384 addr_40 addr = 0;3385 3386 {3387 for (; dcache_miss_num_cache<m_nb_dcache; ++dcache_miss_num_cache)3388 {3389 dcache_miss_req = r_dcache_miss_req[dcache_miss_num_cache];3390 if (dcache_miss_req)3391 break;3392 }3393 for (; icache_miss_num_cache<m_nb_icache; ++icache_miss_num_cache)3394 {3395 icache_miss_req = r_icache_miss_req[icache_miss_num_cache];3396 if (icache_miss_req)3397 break;3398 }3399 3400 PRINTF(" * <CMD> icache_miss_req (before) : %d\n",icache_miss_req);3401 PRINTF(" * <CMD> dcache_miss_req (before) : %d\n",dcache_miss_req);3402 3403 2206 #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) 3404 // 1) one access with static priority (dcache prior) 3405 icache_miss_req &= not dcache_miss_req; 2207 // 1) two access authorized 2208 bool dcache_miss_req = r_dcache_miss_req; 2209 bool icache_miss_req = r_icache_miss_req; 3406 2210 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) 3407 // 2) one access with static priority (icache prior) 3408 dcache_miss_req &= not icache_miss_req; 2211 // 2) one access with static priority (dcache prior) 2212 bool dcache_miss_req = r_dcache_miss_req; // dcache prior 2213 bool icache_miss_req = not dcache_miss_req and r_icache_miss_req; 3409 2214 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==3) 3410 // 3) one access with round robin priority3411 dcache_miss_req = ((dcache_miss_req and not icache_miss_req) or // only dcache3412 (dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior3413 icache_miss_req &= not dcache_miss_req; 3414 // #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) 3415 // // 4) two access authorized 3416 // dcache_miss_req = r_dcache_miss_req[cache_miss_num_cache]; 3417 // icache_miss_req = r_icache_miss_req[cache_miss_num_cache];2215 // 3) one access with static priority (icache prior) 2216 bool icache_miss_req = r_icache_miss_req; 2217 bool dcache_miss_req = not icache_miss_req and r_dcache_miss_req; // dcache prior 2218 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) 2219 // 4) one access with round robin priority 2220 bool dcache_miss_req = ((r_dcache_miss_req and not r_icache_miss_req) or // only dcache 2221 (r_dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior 2222 bool icache_miss_req = not dcache_miss_req and r_icache_miss_req; 3418 2223 #else 3419 2224 #error "Invalid value to CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY" 3420 2225 #endif 3421 3422 PRINTF(" * <CMD> icache_miss_req (after ) : %d\n",icache_miss_req);3423 PRINTF(" * <CMD> dcache_miss_req (after ) : %d\n",dcache_miss_req);3424 3425 PRINTF(" * <CMD> icache_miss_num_cache : %d\n",icache_miss_num_cache);3426 PRINTF(" * <CMD> dcache_miss_num_cache : %d\n",dcache_miss_num_cache);3427 3428 if (icache_miss_req or dcache_miss_req)3429 {3430 addr = (icache_miss_req)?r_icache_addr_save[icache_miss_num_cache].read():r_dcache_addr_save[dcache_miss_num_cache].read();3431 3432 PRINTF(" * <CMD> addr : %llx\n",(blob_t)addr);3433 3434 if (icache_miss_req)3435 {3436 // FIXME :3437 // si wbuf contient des addresses partionné, set_num_icache puis get_num_dcache3438 // dcache_miss_num_cache = icache_miss_num_cache;3439 set_num_icache(addr,icache_miss_num_cache);3440 // get_num_dcache(addr,dcache_miss_num_cache);3441 }3442 else3443 set_num_dcache(addr,dcache_miss_num_cache);3444 3445 PRINTF(" * <CMD> addr : %llx\n",(blob_t)addr);3446 }3447 }3448 3449 uint32_t dcache_unc_num_cache = 0;3450 for (; dcache_unc_num_cache<m_nb_dcache; ++dcache_unc_num_cache)3451 if (r_dcache_unc_req[dcache_unc_num_cache])3452 break;3453 uint32_t icache_unc_num_cache = 0;3454 for (; icache_unc_num_cache<m_nb_icache; ++icache_unc_num_cache)3455 if (r_icache_unc_req[icache_unc_num_cache])3456 break;3457 uint32_t dcache_sc_num_cache = 0;3458 for (; dcache_sc_num_cache<m_nb_dcache; ++dcache_sc_num_cache)3459 if (r_dcache_sc_req[dcache_sc_num_cache])3460 break;3461 uint32_t dcache_write_num_cache = 0;3462 for (; dcache_write_num_cache<m_nb_dcache; ++dcache_write_num_cache)3463 {3464 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION3465 if ( r_wbuf[dcache_write_num_cache]->debug_rok(&wbuf_min, &wbuf_max, &wbuf_addr, &wbuf_index))3466 break;3467 #else3468 if ( r_wbuf[dcache_write_num_cache]->rok(&wbuf_min, &wbuf_max))3469 break;3470 #endif3471 }3472 3473 2226 // 1 - Data Read 3474 if (dcache_miss_req and r_wbuf [dcache_miss_num_cache]->miss(addr))2227 if (dcache_miss_req and r_wbuf.miss(r_dcache_addr_save)) 3475 2228 { 3476 r_vci_cmd_fsm = CMD_DATA_MISS; 3477 r_vci_cmd_num_cache = dcache_miss_num_cache; 3478 r_dcache_miss_req[dcache_miss_num_cache] = false; 2229 r_vci_cmd_fsm = CMD_DATA_MISS; 2230 r_dcache_miss_req = false; 3479 2231 m_cpt_dmiss_transaction++; 3480 3481 3482 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION3483 {3484 log_transaction_file_cmd3485 << "[" << m_cpt_total_cycles << "] "3486 << "CMD DATA MISS "3487 << "(" << dcache_miss_num_cache << ") "3488 << std::hex3489 << " @ " << std::setw(10) << (blob_t)addr3490 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")"3491 << std::dec3492 << std::endl;3493 }3494 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION3495 3496 2232 } 3497 2233 3498 2234 // 2 - Data Read Uncachable 3499 else if ( dcache_unc_num_cache < m_nb_dcache) // have r_dcache_unc_req2235 else if ( r_dcache_unc_req ) 3500 2236 { 3501 r_vci_cmd_fsm = CMD_DATA_UNC; 3502 r_vci_cmd_num_cache = dcache_unc_num_cache; 3503 r_dcache_unc_req[dcache_unc_num_cache] = false; 3504 // m_cpt_data_unc_transaction++; 3505 3506 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3507 { 3508 addr_40 addr = (addr_40) r_dcache_addr_save[dcache_unc_num_cache].read() & ~0x3; 3509 set_num_dcache(addr,dcache_unc_num_cache); 3510 3511 log_transaction_file_cmd 3512 << "[" << m_cpt_total_cycles << "] " 3513 << "CMD DATA UNC " 3514 << "(" << dcache_unc_num_cache << ") " 3515 << std::hex 3516 << " @ " << std::setw(10) << (blob_t)addr 3517 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" 3518 << std::dec 3519 << std::endl; 3520 } 3521 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2237 r_vci_cmd_fsm = CMD_DATA_UNC; 2238 r_dcache_unc_req = false; 2239 // m_cpt_data_unc_transaction++; 3522 2240 } 3523 2241 3524 2242 // 3 - Instruction Miss 3525 else if (icache_miss_req and r_wbuf[icache_miss_num_cache]->miss(addr)) 3526 //else if (icache_miss_req and r_wbuf[dcache_miss_num_cache]->miss(addr)) 2243 else if (icache_miss_req and r_wbuf.miss(r_icache_addr_save)) 3527 2244 { 3528 r_vci_cmd_fsm = CMD_INS_MISS; 3529 r_vci_cmd_num_cache = icache_miss_num_cache; 3530 r_icache_miss_req[icache_miss_num_cache] = false; 2245 r_vci_cmd_fsm = CMD_INS_MISS; 2246 r_icache_miss_req = false; 3531 2247 m_cpt_imiss_transaction++; 3532 3533 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION3534 {3535 log_transaction_file_cmd3536 << "[" << m_cpt_total_cycles << "] "3537 << "CMD INS MISS "3538 << "(" << icache_miss_num_cache << ") "3539 << std::hex3540 << " @ " << std::setw(10) << (blob_t)addr3541 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_icache_yzmask) << ")"3542 << std::dec3543 << std::endl;3544 }3545 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION3546 2248 } 3547 2249 3548 2250 // 4 - Instruction Uncachable 3549 else if ( icache_unc_num_cache < m_nb_icache) // have r_icache_unc_req2251 else if ( r_icache_unc_req ) 3550 2252 { 3551 r_vci_cmd_fsm = CMD_INS_UNC; 3552 r_vci_cmd_num_cache = icache_unc_num_cache; 3553 r_icache_unc_req[icache_unc_num_cache] = false; 2253 r_vci_cmd_fsm = CMD_INS_UNC; 2254 r_icache_unc_req = false; 3554 2255 // m_cpt_ins_unc_transaction++; 3555 3556 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION3557 {3558 addr_40 addr = (addr_40) r_icache_addr_save[icache_unc_num_cache].read() & ~0x3;3559 set_num_dcache(addr,icache_unc_num_cache);3560 3561 log_transaction_file_cmd3562 << "[" << m_cpt_total_cycles << "] "3563 << "CMD INS UNC "3564 << "(" << icache_unc_num_cache << ") "3565 << std::hex3566 << " @ " << std::setw(10) << (blob_t)addr3567 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_icache_yzmask) << ")"3568 << std::dec3569 << std::endl;3570 }3571 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION3572 2256 } 3573 2257 3574 2258 // 5 - Data Write 3575 else if ( dcache_write_num_cache < m_nb_dcache) // have r_wbuf.rok(&wbuf_min, &wbuf_max)2259 else if ( r_wbuf.rok(&min, &max) ) 3576 2260 { 3577 r_vci_cmd_num_cache = dcache_write_num_cache; 3578 r_vci_cmd_fsm = CMD_DATA_WRITE; 3579 r_vci_cmd_cpt = wbuf_min; 3580 r_vci_cmd_min = wbuf_min; 3581 r_vci_cmd_max = wbuf_max; 2261 r_vci_cmd_fsm = CMD_DATA_WRITE; 2262 r_vci_cmd_cpt = min; 2263 r_vci_cmd_min = min; 2264 r_vci_cmd_max = max; 3582 2265 m_cpt_data_write_transaction++; 3583 m_length_write_transaction += (wbuf_max-wbuf_min+1); 3584 3585 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3586 { 3587 addr_40 addr = (addr_40) wbuf_addr&~0x3; 3588 3589 log_transaction_file_cmd 3590 << "[" << m_cpt_total_cycles << "] " 3591 << "CMD DATA WRITE " 3592 << "(" << dcache_write_num_cache << ") " 3593 << std::hex 3594 << " @ " << std::setw(10) << (blob_t)addr 3595 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" 3596 << " [" << wbuf_min << ":" << wbuf_max << "]" 3597 << " {" << wbuf_index << "}" 3598 << std::dec 3599 << std::endl; 3600 } 3601 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2266 m_length_write_transaction += (max-min+1); 3602 2267 } 3603 2268 3604 2269 // 6 - Data Store Conditionnal 3605 else if ( dcache_sc_num_cache < m_nb_dcache) // have r_dcache_sc_req2270 else if ( r_dcache_sc_req ) 3606 2271 { 3607 r_vci_cmd_fsm = CMD_DATA_SC; 3608 r_vci_cmd_num_cache = dcache_sc_num_cache; 3609 r_vci_cmd_max = 1; 2272 r_vci_cmd_fsm = CMD_DATA_SC; 2273 r_vci_cmd_max = 1; 3610 2274 m_cpt_unc_transaction++; 3611 r_dcache_sc_req[dcache_sc_num_cache] = false; 3612 3613 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 3614 { 3615 addr_40 addr = (addr_40) r_dcache_addr_save[dcache_sc_num_cache].read() & ~0x3; 3616 set_num_dcache(addr,dcache_sc_num_cache); 3617 3618 log_transaction_file_cmd 3619 << "[" << m_cpt_total_cycles << "] " 3620 << "CMD DATA SC " 3621 << "(" << dcache_sc_num_cache << ") " 3622 << std::hex 3623 << " @ " << std::setw(10) << (blob_t)addr 3624 << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" 3625 << std::dec 3626 << std::endl; 3627 } 3628 #endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 2275 r_dcache_sc_req = false; 3629 2276 } 3630 2277 … … 3636 2283 if (r_vci_cmd_cpt == r_vci_cmd_max) { 3637 2284 r_vci_cmd_fsm = CMD_IDLE ; 3638 r_wbuf [r_vci_cmd_num_cache]->sent() ;2285 r_wbuf.sent() ; 3639 2286 } 3640 2287 } … … 3692 2339 if( p_vci_ini_rw.rspval.read() ) 3693 2340 { 3694 PRINTF(" * <RSP> have rsp - trdid : %x - num_cache : %d\n",(uint32_t)p_vci_ini_rw.rtrdid.read(),(uint32_t)p_vci_ini_rw.rpktid.read()); 3695 3696 ASSERT(p_vci_ini_rw.rpktid.read() <= (1<<vci_param::P), 3697 "invalid pktid in a cleanup response"); 2341 PRINTF(" * <RSP> have rsp - trdid : %x\n",(uint32_t)p_vci_ini_rw.rtrdid.read()); 3698 2342 3699 2343 r_vci_rsp_cpt = 0; 3700 2344 3701 2345 if ((p_vci_ini_rw.rtrdid.read()>>(vci_param::T-1)) != 0 ) 3702 {3703 2346 r_vci_rsp_fsm = RSP_DATA_WRITE; 3704 3705 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION3706 {3707 log_transaction_file_cmd3708 << "[" << m_cpt_total_cycles << "] "3709 << "RSP DATA WRITE "3710 &nbs