Changeset 175 for trunk/modules/vci_cc_xcache_wrapper_v4/caba
- Timestamp:
- Jun 5, 2011, 1:24:11 PM (13 years ago)
- Location:
- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_xcache_wrapper_v4.h (modified) (3 diffs)
-
src/vci_cc_xcache_wrapper_v4.cpp (modified) (20 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r167 r175 92 92 #endif 93 93 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 94 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 472500094 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1013300 95 95 #endif 96 96 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION … … 133 133 DCACHE_CC_CHECK, 134 134 DCACHE_CC_INVAL, 135 DCACHE_CC_UPDT,136 135 DCACHE_CC_CLEANUP, 137 136 }; … … 147 146 ICACHE_CC_CHECK, 148 147 ICACHE_CC_INVAL, 149 ICACHE_CC_UPDT,150 148 }; 151 149 -
trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
r167 r175 88 88 # define set_num_icache( addr,num_cache) set_num_cache (addr,num_cache) 89 89 # define set_num_icache_only(addr,num_cache) set_num_cache_only(addr,num_cache) 90 # define get_num_dcache( addr) get_num_cache (addr)91 # define get_num_dcache_only(addr) get_num_cache_only(addr)92 # define set_num_dcache( addr,num_cache) set_num_cache (addr,num_cache)93 # define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache)94 90 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) 95 91 # define get_num_icache( addr,num_cpu) num_cpu … … 97 93 # define set_num_icache( addr,num_cache) do {} while (0) 98 94 # define set_num_icache_only(addr,num_cache) addr 95 #else 96 #error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE" 97 #endif 99 98 # define get_num_dcache( addr) get_num_cache (addr) 100 99 # define get_num_dcache_only(addr) get_num_cache_only(addr) 101 100 # define set_num_dcache( addr,num_cache) set_num_cache (addr,num_cache) 102 101 # define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache) 103 #else104 #error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE"105 #endif106 102 107 103 const char *dcache_fsm_state_str[] = { … … 118 114 "DCACHE_CC_CHECK", 119 115 "DCACHE_CC_INVAL", 120 "DCACHE_CC_UPDT",121 116 "DCACHE_CC_CLEANUP", 122 117 }; … … 131 126 "ICACHE_CC_CHECK", 132 127 "ICACHE_CC_INVAL", 133 "ICACHE_CC_UPDT",134 128 }; 135 129 const char *cmd_fsm_state_str[] = { … … 300 294 "wbuf_nlines must be a multiple of nb cache."); 301 295 302 // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE 296 // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE, car le type est fournit dans le champs l'adresse 303 297 ASSERT((m_nb_dcache == 1) or (dcache_words >= 16), 304 298 "When multi cache is activated, need 4 bits (16 word) to the cache set ."); … … 576 570 << _dcache_words << std::endl; // cache_nb_words 577 571 } 578 579 572 #endif 580 573 } // end constructor … … 1209 1202 // r_wbuf[num_cache]->printTrace(1); 1210 1203 // #endif 1211 1212 } 1204 } 1205 #if CC_XCACHE_WRAPPER_DEBUG 1206 if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) 1207 { 1208 PRINTF(" * rsp_fifo_icache %s\n",name().c_str()); 1209 r_vci_rsp_fifo_icache_data .print(); 1210 r_vci_rsp_fifo_icache_num_cache.print(); 1211 PRINTF(" * rsp_fifo_dcache %s\n",name().c_str()); 1212 r_vci_rsp_fifo_dcache_data .print(); 1213 r_vci_rsp_fifo_dcache_num_cache.print(); 1214 } 1215 #endif 1213 1216 1214 1217 ///////////////////////////////////////////////////////////////////// … … 2138 2141 m_cpt_icache_data_read += m_icache_ways; 2139 2142 addr_40 ad = r_tgt_iaddr; 2140 data_t icache_rdata = 0;2141 2143 2142 2144 PRINTF(" * <ICACHE [%d]> CC_CHECK\n",num_cache); … … 2157 2159 r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache]; 2158 2160 } else { 2159 bool icache_hit = r_icache[num_cache]->read(ad, &icache_rdata); 2161 uint32_t word = r_cache_word; 2162 data_t mask = vci_param::be2mask(r_tgt_be[word]); 2163 data_t rdata = 0; 2164 bool icache_hit = r_icache[num_cache]->read(ad+word*4,&rdata); 2160 2165 2161 2166 PRINTF(" * <ICACHE [%d]> have no request, hit cache : %d\n",num_cache,icache_hit); … … 2163 2168 if ( icache_hit and r_tgt_update) 2164 2169 { 2165 uint32_t word = r_cache_word; 2166 data_t mask = vci_param::be2mask(r_tgt_be[word]); 2167 data_t rdata = 0; 2168 2169 r_icache[num_cache]->read(ad+word*4,&rdata); 2170 r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); 2170 // Assumption : We have RAM for icache with write enable on byte. 2171 // Consequence : icache_read is only consultation of directory 2172 2173 //if(r_tgt_be[word]) 2174 r_icache[num_cache]->write(ad+word*4, (mask & r_tgt_buf[word]) | (~mask & rdata)); 2171 2175 2172 2176 word ++; … … 2179 2183 if (word==m_icache_words) 2180 2184 { 2181 r_icache_fsm[num_cache] = ICACHE_CC_UPDT; 2182 2183 // find next valid word 2184 for (word=0; word<m_icache_words; ++word) 2185 if (r_tgt_be[word] != 0) 2186 break; 2185 r_tgt_icache_req[num_cache] = false; 2186 r_tgt_icache_rsp[num_cache] = true; 2187 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache].read(); 2188 word = 0; 2187 2189 } 2188 2190 r_cache_word = word; … … 2214 2216 break; 2215 2217 } 2216 /////////////////////2217 case ICACHE_CC_UPDT:2218 {2219 addr_40 ad = r_tgt_iaddr.read();2220 m_cpt_icache_dir_write++;2221 m_cpt_icache_data_write++;2222 2223 uint32_t word = r_cache_word;2224 2225 if(r_tgt_be[word])2226 r_icache[num_cache]->write(ad+word*4, r_tgt_buf[word]);2227 2228 word ++;2229 2230 // find next valid word2231 for (; word<m_icache_words; ++word)2232 if (r_tgt_be[word] != 0)2233 break;2234 2235 if (word==m_icache_words)2236 {2237 r_tgt_icache_req[num_cache] = false;2238 r_tgt_icache_rsp[num_cache] = true;2239 r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache].read();2240 word = 0;2241 }2242 r_cache_word = word;2243 2244 break;2245 }2246 2247 2218 }// end switch r_icache_fsm 2248 2219 … … 2515 2486 if (not dcache_cached) 2516 2487 { 2488 ASSERT(not dcache_hit, 2489 "Request is uncached, but hit in dcache!"); 2490 2517 2491 r_dcache_previous_unc[num_cache] = true; 2518 2492 m_cpt_data_write_uncached++; … … 2520 2494 else if (not dcache_hit) 2521 2495 m_cpt_data_write_miss++; 2522 2496 2523 2497 if (dcache_hit) { 2524 2498 // update data cache … … 2922 2896 { 2923 2897 addr_40 ad = r_tgt_daddr; 2924 data_t dcache_rdata = 0;2925 2898 2926 2899 PRINTF(" * <DCACHE [%d]> CC_CHECK\n",num_cache); … … 2942 2915 r_dcache_fsm[num_cache] = r_dcache_fsm_save[num_cache]; 2943 2916 } else { 2944 bool dcache_hit = r_dcache[num_cache]->read(ad, &dcache_rdata); 2917 uint32_t word = r_cache_word; 2918 data_t mask = vci_param::be2mask(r_tgt_be[word]); 2919 data_t rdata = 0; 2920 bool dcache_hit = r_dcache[num_cache]->read(ad+word*4,&rdata); 2945 2921 2946 2922 PRINTF(" * <DCACHE [%d]> have no request, hit cache : %d, update : %d\n",num_cache,dcache_hit,(uint32_t)r_tgt_update); 2947 2923 2948 m_cpt_dcache_data_ read+= m_dcache_ways;2924 m_cpt_dcache_data_write+= m_dcache_ways; 2949 2925 m_cpt_dcache_dir_read += m_dcache_ways; 2950 2926 2951 2927 if ( dcache_hit and r_tgt_update ) 2952 2928 { 2953 uint32_t word = r_cache_word; 2954 data_t mask = vci_param::be2mask(r_tgt_be[word]); 2955 data_t rdata = 0; 2956 2957 r_dcache[num_cache]->read(ad+word*4,&rdata); 2958 2959 r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); 2929 // Assumption : We have RAM for dcache with write enable on byte. 2930 // Consequence : dcache_read is only consultation of directory 2931 2932 //if(r_tgt_be[word]) 2933 r_dcache[num_cache]->write(ad+word*4, (mask & r_tgt_buf[word]) | (~mask & rdata)); 2960 2934 2961 2935 word ++; … … 2968 2942 if (word==m_dcache_words) 2969 2943 { 2970 r_dcache_fsm[num_cache] = DCACHE_CC_UPDT; 2971 2972 for (word=0; word<m_dcache_words; ++word) 2973 if (r_tgt_be[word] != 0) 2974 break; 2944 r_tgt_dcache_req[num_cache] = false; 2945 r_tgt_dcache_rsp[num_cache] = true; 2946 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; 2947 word = 0; 2975 2948 } 2976 2949 r_cache_word = word; … … 2988 2961 } 2989 2962 } 2990 break;2991 }2992 ///////////////////2993 case DCACHE_CC_UPDT: // update directory and data cache2994 {2995 addr_40 ad = r_tgt_daddr;2996 2997 m_cpt_dcache_dir_write++;2998 m_cpt_dcache_data_write++;2999 3000 uint32_t word = r_cache_word;3001 3002 if(r_tgt_be[word])3003 r_dcache[num_cache]->write(ad+word*4, r_tgt_buf[word]);3004 3005 word ++;3006 3007 for (; word<m_dcache_words; ++word)3008 if (r_tgt_be[word] != 0)3009 break;3010 3011 if (word==m_dcache_words)3012 {3013 r_tgt_dcache_req[num_cache] = false;3014 r_tgt_dcache_rsp[num_cache] = true;3015 r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache];3016 word = 0;3017 }3018 r_cache_word = word;3019 3020 2963 break; 3021 2964 } … … 3898 3841 3899 3842 m_cost_imiss_transaction++; 3900 PRINTF(" * <RSP> rspval : %d \n",(uint32_t)p_vci_ini_rw.rspval.read());3843 PRINTF(" * <RSP> rspval : %d / r_vci_rsp_fifo_icache_data.wok %d\n",(uint32_t)p_vci_ini_rw.rspval.read(),(uint32_t)r_vci_rsp_fifo_icache_data.wok()); 3901 3844 3902 3845 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_fifo_icache_data.wok()) … … 3949 3892 3950 3893 m_cost_dmiss_transaction++; 3894 3895 PRINTF(" * <RSP> rspval : %d / r_vci_rsp_fifo_icache_data.wok %d\n",(uint32_t)p_vci_ini_rw.rspval.read(),(uint32_t)r_vci_rsp_fifo_dcache_data.wok()); 3896 3951 3897 if (p_vci_ini_rw.rspval.read() and r_vci_rsp_fifo_dcache_data.wok()) 3952 3898 { 3953 PRINTF(" * <RSP> have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read());3899 PRINTF(" * <RSP> have rsp - r_vci_rsp_cpt : %d/%d\n",(uint32_t)r_vci_rsp_cpt.read(),(uint32_t)m_icache_words); 3954 3900 3955 3901 ASSERT(r_vci_rsp_cpt.read() < m_dcache_words,
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