Changeset 196 for trunk/modules/vci_cc_vcache_wrapper_v4

Timestamp:

Feb 19, 2012, 5:39:16 PM (13 years ago)

Author:

alain

Message:

Fixing 2 bugs:
1/ The coherence requests must be taken in state DCACHE_XTN_WRITE to avoid dead-locks.
2/ Completion of the ITLB flush was not properly handled in the DCACHE_XTN_SWITCH state.

File:

• trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (modified) (5 diffs)

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

@@ -1229 +1229 @@
     // 
     // In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
-    // to CMD FSM usig the r_icache_unc_req flip-flop, that reset this flip-flop
+    // to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
     // when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
     // the response from the RSP FSM, through the response fifo. The missing instruction
@@ -1240 +1240 @@
     // the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
     //
-    // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop. 
+    // The DCACHE FSM signals XTN processor requests to ICACHE_FSM
+    // using the r_dcache_xtn_req flip-flop. 
     // The request opcode and the address to be invalidated are transmitted
     // in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
@@ -3293 +3294 @@
     case DCACHE_XTN_SWITCH:             // Both itlb and dtlb must be flushed
     {
-        if ( r_dcache_xtn_req.read() )
+        if ( not r_dcache_xtn_req.read() )
         {
             r_dtlb.flush();
@@ -3303 +3304 @@
     /////////////////////
     case DCACHE_XTN_SYNC:               // waiting until write buffer empty
-    {
+                                        // The coherence request must be taken
+                                        // as there is a risk of dead-lock
+    {
+        // external coherence request 
+        if ( r_tgt_dcache_req.read() )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = DCACHE_XTN_SYNC;
+        }        
+
         if ( r_wbuf.empty() )
         {
@@ -3556 +3566 @@
               << " / set = "   << set
               << " / valid = "  << valid
-              << " / line = " << victim << std::endl; 
+              << " / line = " << std::hex << victim << std::endl; 
 }
 #endif