Changeset 197 for trunk/modules/vci_cc_vcache_wrapper_v4
- Timestamp:
- Feb 20, 2012, 7:08:53 PM (13 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
r196 r197 34 34 #define DEBUG_INVAL_ITLB 1 35 35 #define DEBUG_INVAL_DTLB 1 36 37 #define _CMD_INIT_VAL 0x00 38 #define _CMD_ITLB 0x01 39 #define _CMD_DTLB 0x02 40 #define _CMD_USR 0x04 36 41 37 42 namespace soclib { … … 393 398 "icache_words and dcache_words parameters must be equal"); 394 399 395 r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | 396 (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | 397 (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | 398 (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | 399 (uint32_log2(m_icache_words<<2)); 400 401 r_mmu_release = (uint32_t)(1 << 16) | 0x1; 400 { 401 uint32_t val; 402 403 val = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | 404 (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | 405 (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | 406 (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | 407 (uint32_log2(m_icache_words<<2)); 408 409 //r_mmu_params = val; 410 m_mmu_params = val; 411 412 val = (1 << 16) | 0x1; 413 //r_mmu_release = val; 414 m_mmu_release = val; 415 } 416 402 417 403 418 r_tgt_buf = new uint32_t[dcache_words]; … … 405 420 r_dcache_in_itlb = new bool[dcache_ways*dcache_sets]; 406 421 r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets]; 422 423 424 m_proc_id = proc_id; 425 426 m_tm_start = 0; 427 m_tm_end = 0; 428 m_period = 0; 429 430 char *ptr; 431 432 ptr = getenv("TSAR_L1_TM_START"); 433 434 if(ptr != NULL) 435 m_tm_start = (size_t) atol(ptr); 436 437 ptr = getenv("TSAR_L1_TM_END"); 438 439 if(ptr != NULL) 440 m_tm_end = (size_t) atol(ptr); 441 442 ptr = getenv("TSAR_L1_PERIOD"); 443 444 if(ptr != NULL) 445 m_period = (size_t) atol(ptr); 446 447 if(m_period != 0) 448 m_log.open(name, std::ios::out); 449 450 if(m_proc_id == 0) 451 { 452 std::cout << "TSAR_L1_TM_START =" << m_tm_start << std::endl 453 << "TSAR_L1_TM_END =" << m_tm_end << std::endl 454 << "TSAR_L1_PERIOD =" << m_period << std::endl; 455 } 456 407 457 408 458 SC_METHOD(transition); … … 535 585 536 586 537 538 /*539 587 //////////////////////// 540 588 tmpl(void)::print_stats() 541 589 //////////////////////// 542 590 { 591 std::ostream &output = (m_period == 0) ? std::cout : m_log; 592 543 593 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); 544 std::cout << name() << std::endl545 << "- CPI= " << (float)m_cpt_total_cycles/run_cycles << std::endl546 << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl547 << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl548 << "- IMISS_RATE= " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl549 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl550 << "- INS MISS COST= " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl551 << "- DATA MISS COST= " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl552 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl553 << "- UNC COST= " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl554 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl555 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl556 << "- INS TLB MISS RATE= " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl557 << "- DATA TLB MISS RATE= " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl558 << "- ITLB MISS COST= " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl559 << "- DTLB MISS COST= " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl560 << "- ITLB UPDATE ACC COST= " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl561 << "- DTLB UPDATE ACC COST= " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl562 << "- DTLB UPDATE DIRTY COST= " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl563 << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl564 << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl565 << "- DCACHE FROZEN BY ITLB= " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl566 << "- DCACHE FOR TLB %= " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl567 << "- NB CC BROADCAST= " << m_cpt_cc_broadcast << std::endl568 << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data<< std::endl569 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data<< std::endl570 << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins<< std::endl571 << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast<< std::endl572 << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data<< std::endl573 << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data<< std::endl574 << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins<< std::endl575 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data<< std::endl576 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins<< std::endl577 << "- IMISS TRANSACTION= " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl578 << "- DMISS TRANSACTION= " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl579 << "- UNC TRANSACTION= " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl580 << "- WRITE TRANSACTION= " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl581 << "- WRITE LENGTH= " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl582 << "- ITLB MISS TRANSACTION= " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl583 << "- DTLB MISS TRANSACTION= " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;594 output << name() << std::endl 595 << "CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl 596 << "READ_RATE = " << (float)m_cpt_data_read/run_cycles << std::endl 597 << "WRITE_RATE = " << (float)m_cpt_data_write/run_cycles << std::endl 598 << "IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 599 << "DMISS_RATE = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl 600 << "INS_MISS_COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 601 << "DATA_MISS_COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 602 << "WRITE_COST = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl 603 << "UNC_COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 604 << "UNCACHED_READ_RATE = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl 605 << "CACHED_WRITE_RATE = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl 606 << "INS_TLB_MISS_RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 607 << "DATA_TLB_MISS_RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 608 << "ITLB_MISS_COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl 609 << "DTLB_MISS_COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl 610 << "ITLB_UPDATE_ACC_COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl 611 << "DTLB_UPDATE_ACC_COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl 612 << "DTLB_UPDATE_DIRTY_COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 613 << "ITLB_HIT_IN_DCACHE_RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl 614 << "DTLB_HIT_IN_DCACHE_RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl 615 << "DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl 616 << "DCACHE_FOR_TLB_% = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl 617 << "NB_CC_BROADCAST = " << m_cpt_cc_broadcast << std::endl 618 << "NB_CC_UPDATE_DATA = " << m_cpt_cc_update_dcache << std::endl 619 << "NB_CC_INVAL_DATA = " << m_cpt_cc_inval_dcache << std::endl 620 << "NB_CC_INVAL_INS = " << m_cpt_cc_inval_icache << std::endl 621 << "NB_CC_CLEANUP_DATA = " << m_cpt_cc_cleanup_data << std::endl 622 << "NB_CC_CLEANUP_INS = " << m_cpt_cc_cleanup_ins << std::endl 623 << "CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl 624 << "CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl 625 << "CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl 626 << "CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl 627 << "IMISS_TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 628 << "DMISS_TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 629 << "UNC_TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 630 << "WRITE_TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 631 << "WRITE_LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 632 << "ITLB_MISS_TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 633 << "DTLB_MISS_TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; 584 634 } 635 585 636 586 637 //////////////////////// … … 601 652 m_cpt_total_cycles = 0; 602 653 603 m_cpt_ read = 0;604 m_cpt_ write = 0;654 m_cpt_data_read = 0; 655 m_cpt_data_write = 0; 605 656 m_cpt_data_miss = 0; 606 657 m_cpt_ins_miss = 0; … … 630 681 m_cpt_ins_tlb_miss = 0; 631 682 m_cpt_ins_tlb_update_acc = 0; 632 683 m_cpt_ins_tlb_occup_cache = 0; 684 m_cpt_ins_tlb_hit_dcache = 0; 685 633 686 m_cpt_data_tlb_read = 0; 634 687 m_cpt_data_tlb_miss = 0; 635 688 m_cpt_data_tlb_update_acc = 0; 636 689 m_cpt_data_tlb_update_dirty = 0; 637 m_cpt_ins_tlb_hit_dcache = 0;638 690 m_cpt_data_tlb_hit_dcache = 0; 639 m_cpt_ins_tlb_occup_cache = 0;640 691 m_cpt_data_tlb_occup_cache = 0; 641 692 … … 666 717 m_cost_dtlb_sc_dirty_transaction = 0; 667 718 668 m_cpt_cc_update_data = 0; 669 m_cpt_cc_inval_ins = 0; 670 m_cpt_cc_inval_data = 0; 671 m_cpt_cc_broadcast = 0; 719 m_cpt_cc_update_icache = 0; 720 m_cpt_cc_update_dcache = 0; 721 m_cpt_cc_inval_icache = 0; 722 m_cpt_cc_inval_dcache = 0; 723 m_cpt_cc_broadcast = 0; 672 724 673 725 m_cost_updt_data_frz = 0; … … 678 730 m_cpt_cc_cleanup_data = 0; 679 731 m_cpt_cc_cleanup_ins = 0; 732 733 m_cpt_icleanup_transaction = 0; 734 m_cpt_dcleanup_transaction = 0; 735 m_cost_icleanup_transaction = 0; 736 m_cost_dcleanup_transaction = 0; 737 738 m_cpt_ins_tlb_inval = 0; 739 m_cost_data_tlb_inval_frz = 0; 740 m_cost_ins_tlb_inval_frz = 0; 680 741 } 681 742 682 */683 743 684 744 ///////////////////////// … … 716 776 r_mmu_mode = 0x3; 717 777 718 778 // No request from ICACHE FSM to CMD FSM 719 779 r_icache_miss_req = false; 720 780 r_icache_unc_req = false; … … 739 799 740 800 // No LL reservation 741 801 r_dcache_ll_valid = false; 742 802 743 803 // No request from DCACHE FSM to INVAL TLB FSMs … … 771 831 m_debug_inval_dtlb_fsm = false; 772 832 773 /* 774 // activity counters 775 m_cpt_dcache_data_read = 0; 776 m_cpt_dcache_data_write = 0; 777 m_cpt_dcache_dir_read = 0; 778 m_cpt_dcache_dir_write = 0; 779 m_cpt_icache_data_read = 0; 780 m_cpt_icache_data_write = 0; 781 m_cpt_icache_dir_read = 0; 782 m_cpt_icache_dir_write = 0; 783 784 m_cpt_frz_cycles = 0; 785 m_cpt_dcache_frz_cycles = 0; 786 m_cpt_total_cycles = 0; 787 788 m_cpt_read = 0; 789 m_cpt_write = 0; 790 m_cpt_data_miss = 0; 791 m_cpt_ins_miss = 0; 792 m_cpt_unc_read = 0; 793 m_cpt_write_cached = 0; 794 m_cpt_ins_read = 0; 795 796 m_cost_write_frz = 0; 797 m_cost_data_miss_frz = 0; 798 m_cost_unc_read_frz = 0; 799 m_cost_ins_miss_frz = 0; 800 801 m_cpt_imiss_transaction = 0; 802 m_cpt_dmiss_transaction = 0; 803 m_cpt_unc_transaction = 0; 804 m_cpt_write_transaction = 0; 805 m_cpt_icache_unc_transaction = 0; 806 807 m_cost_imiss_transaction = 0; 808 m_cost_dmiss_transaction = 0; 809 m_cost_unc_transaction = 0; 810 m_cost_write_transaction = 0; 811 m_cost_icache_unc_transaction = 0; 812 m_length_write_transaction = 0; 813 814 m_cpt_ins_tlb_read = 0; 815 m_cpt_ins_tlb_miss = 0; 816 m_cpt_ins_tlb_update_acc = 0; 817 818 m_cpt_data_tlb_read = 0; 819 m_cpt_data_tlb_miss = 0; 820 m_cpt_data_tlb_update_acc = 0; 821 m_cpt_data_tlb_update_dirty = 0; 822 m_cpt_ins_tlb_hit_dcache = 0; 823 m_cpt_data_tlb_hit_dcache = 0; 824 m_cpt_ins_tlb_occup_cache = 0; 825 m_cpt_data_tlb_occup_cache = 0; 826 827 m_cost_ins_tlb_miss_frz = 0; 828 m_cost_data_tlb_miss_frz = 0; 829 m_cost_ins_tlb_update_acc_frz = 0; 830 m_cost_data_tlb_update_acc_frz = 0; 831 m_cost_data_tlb_update_dirty_frz = 0; 832 m_cost_ins_tlb_occup_cache_frz = 0; 833 m_cost_data_tlb_occup_cache_frz = 0; 834 835 m_cpt_ins_tlb_inval = 0; 836 m_cpt_data_tlb_inval = 0; 837 m_cost_ins_tlb_inval_frz = 0; 838 m_cost_data_tlb_inval_frz = 0; 839 840 m_cpt_cc_update_data = 0; 841 m_cpt_cc_inval_ins = 0; 842 m_cpt_cc_inval_data = 0; 843 m_cpt_cc_broadcast = 0; 844 845 m_cost_updt_data_frz = 0; 846 m_cost_inval_ins_frz = 0; 847 m_cost_inval_data_frz = 0; 848 m_cost_broadcast_frz = 0; 849 850 m_cpt_cc_cleanup_data = 0; 851 m_cpt_cc_cleanup_ins = 0; 852 853 m_cpt_itlbmiss_transaction = 0; 854 m_cpt_itlb_ll_transaction = 0; 855 m_cpt_itlb_sc_transaction = 0; 856 m_cpt_dtlbmiss_transaction = 0; 857 m_cpt_dtlb_ll_transaction = 0; 858 m_cpt_dtlb_sc_transaction = 0; 859 m_cpt_dtlb_ll_dirty_transaction = 0; 860 m_cpt_dtlb_sc_dirty_transaction = 0; 861 862 m_cost_itlbmiss_transaction = 0; 863 m_cost_itlb_ll_transaction = 0; 864 m_cost_itlb_sc_transaction = 0; 865 m_cost_dtlbmiss_transaction = 0; 866 m_cost_dtlb_ll_transaction = 0; 867 m_cost_dtlb_sc_transaction = 0; 868 m_cost_dtlb_ll_dirty_transaction = 0; 869 m_cost_dtlb_sc_dirty_transaction = 0; 870 833 clear_stats(); 834 835 /* 871 836 for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; 872 837 for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; … … 876 841 for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0; 877 842 for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0; 878 879 */ 843 */ 844 845 //// For instrumentation only 846 r_ireq_isUser_save = false; 847 r_dreq_isUser_save = false; 848 r_tlb_access_type_save = _CMD_INIT_VAL; 880 849 return; 881 850 } … … 900 869 901 870 m_cpt_total_cycles++; 871 872 873 if((m_period != 0) && ((m_cpt_total_cycles % m_period) == 0)) 874 { 875 print_stats(); 876 clear_stats(); 877 } 902 878 903 879 m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; … … 1210 1186 // - Coherence operation => ICACHE_CC_CHEK 1211 1187 // Five configurations corresponding to XTN processor requests sent by DCACHE FSM : 1212 // - Flush TLB => ICACHE_XTN_TLB_FLUSH1213 // - Flush cache => ICACHE_XTN_CACHE_FLUSH1188 // - Flush TLB => ICACHE_XTN_TLB_FLUSH 1189 // - Flush cache => ICACHE_XTN_CACHE_FLUSH 1214 1190 // - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL 1215 1191 // - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@ 1216 1192 // - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA 1217 1193 // three configurations corresponding to instruction processor requests : 1218 // - tlb miss => ICACHE_TLB_WAIT1194 // - tlb miss => ICACHE_TLB_WAIT 1219 1195 // - cacheable read miss => ICACHE_MISS_VICTIM 1220 1196 // - uncacheable read miss => ICACHE_UNC_REQ … … 1264 1240 // for itlb, and with a speculative physical address for icache, 1265 1241 // computed during the previous cycle. 1266 { 1242 { 1243 1244 // For instrumentation: flag reset 1245 r_ireq_isUser_save = false; 1246 1267 1247 // coherence request from the target FSM 1268 1248 if ( r_tgt_icache_req.read() ) … … 1322 1302 uint32_t cache_inst = 0; 1323 1303 bool cache_hit = false; 1304 1305 // For instrumentation: is User access ? 1306 r_ireq_isUser_save = (ireq.mode == iss_t::MODE_USER) ? true : false; 1324 1307 1325 1308 if ( r_mmu_mode.read() & INS_CACHE_MASK ) … … 1439 1422 r_icache_fsm = ICACHE_MISS_VICTIM; 1440 1423 r_icache_miss_req = true; 1424 r_tlb_access_type_save = _CMD_INIT_VAL; 1441 1425 } 1442 1426 } … … 1701 1685 } 1702 1686 1703 1704 1687 if ( r_vci_rsp_ins_error.read() ) // bus error 1688 { 1705 1689 r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; 1706 1690 r_mmu_ibvar = r_icache_vaddr_save.read(); … … 1714 1698 r_icache_miss_word = 0; 1715 1699 r_icache_fsm = ICACHE_MISS_UPDT; 1716 1700 } 1717 1701 break; 1718 1702 } … … 2042 2026 case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state : 2043 2027 // 1) Long write request (DCACHE FSM) => DCACHE_WRITE_*** 2044 // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK2028 // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK 2045 2029 // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS 2046 // 4) XTN request (processor) => DCACHE_XTN_*2047 // 5) DTLB miss (processor) => DCACHE_TLB_MISS2030 // 4) XTN request (processor) => DCACHE_XTN_* 2031 // 5) DTLB miss (processor) => DCACHE_TLB_MISS 2048 2032 // 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM 2049 // 7) Uncacheable read (processor) => DCACHE_UNC_REQ2050 // 8) SC access (processor) => DCACHE_SC2033 // 7) Uncacheable read (processor) => DCACHE_UNC_REQ 2034 // 8) SC access (processor) => DCACHE_SC 2051 2035 // There is 4 configurations to access the cache, 2052 2036 // depending on the pipe-line state, defined … … 2077 2061 bool long_write_set_dirty = false; 2078 2062 bool tlb_inval_frozen = false; 2063 2064 // For instrumentation: flag reset 2065 r_dreq_isUser_save = false; 2079 2066 2080 2067 if ( r_dcache_p1_valid.read() ) // P2 stage activated … … 2141 2128 2142 2129 #if DEBUG_DCACHE 2143 if ( m_debug_dcache_fsm )2144 {2145 if ( cache_updt )2146 std::cout << " <PROC.DCACHE_IDLE> P2 stage: cache update" << std::dec2147 << " / way = " << cache_way2148 << " / set = " << cache_set2149 << " / word = " << cache_word << std::hex2150 << " / wdata = " << wdata2151 << " / be = " << be << std::endl;2152 if ( long_write_set_dirty )2153 std::cout << " <PROC.DCACHE_IDLE> P2 stage: dirty bit update required"2154 << " / pte_paddr = " << std::hex << pte_paddr << std::endl;2155 }2130 if ( m_debug_dcache_fsm ) 2131 { 2132 if ( cache_updt ) 2133 std::cout << " <PROC.DCACHE_IDLE> P2 stage: cache update" << std::dec 2134 << " / way = " << cache_way 2135 << " / set = " << cache_set 2136 << " / word = " << cache_word << std::hex 2137 << " / wdata = " << wdata 2138 << " / be = " << be << std::endl; 2139 if ( long_write_set_dirty ) 2140 std::cout << " <PROC.DCACHE_IDLE> P2 stage: dirty bit update required" 2141 << " / pte_paddr = " << std::hex << pte_paddr << std::endl; 2142 } 2156 2143 #endif 2157 2144 } // end P2 stage … … 2408 2395 2409 2396 case iss_t::XTN_MMU_PARAMS: 2410 drsp.rdata = r_mmu_params.read(); 2397 //drsp.rdata = r_mmu_params.read(); 2398 drsp.rdata = m_mmu_params; 2411 2399 drsp.valid = true; 2412 2400 break; 2413 2401 2414 2402 case iss_t::XTN_MMU_RELEASE: 2415 drsp.rdata = r_mmu_release.read(); 2403 //drsp.rdata = r_mmu_release.read(); 2404 drsp.rdata = m_mmu_release; 2416 2405 drsp.valid = true; 2417 2406 break; … … 2563 2552 else 2564 2553 { 2554 2555 // For instrumentation: is User access ? 2556 r_dreq_isUser_save = (dreq.mode == iss_t::MODE_USER) ? true : false; 2557 2565 2558 bool valid_req = false; 2566 2559 bool cacheable = false; … … 2659 2652 if ( not r_dcache_cleanup_req.read() ) 2660 2653 { 2661 r_dcache_vci_paddr = paddr; 2662 r_dcache_vci_miss_req = true; 2663 r_dcache_miss_type = PROC_MISS; 2664 r_dcache_fsm = DCACHE_MISS_VICTIM; 2654 r_dcache_vci_paddr = paddr; 2655 r_dcache_vci_miss_req = true; 2656 r_dcache_miss_type = PROC_MISS; 2657 r_dcache_fsm = DCACHE_MISS_VICTIM; 2658 r_tlb_access_type_save = _CMD_INIT_VAL; 2665 2659 } 2666 2660 } … … 2838 2832 if ( m_debug_dcache_fsm ) 2839 2833 { 2840 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped:" 2834 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped:" << std::hex 2841 2835 << std::dec << " way = " << way 2842 2836 << std::dec << " / set = " << set … … 2869 2863 if ( m_debug_dcache_fsm ) 2870 2864 { 2871 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache " 2865 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache " << std::hex 2872 2866 << std::dec << " way = " << way 2873 2867 << std::dec << " / set = " << set … … 2892 2886 if ( m_debug_dcache_fsm ) 2893 2887 { 2894 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache:" 2888 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache:" << std::hex 2895 2889 << std::dec << " way = " << way 2896 2890 << std::dec << " / set = " << set … … 2907 2901 r_dcache_fsm = DCACHE_MISS_VICTIM; 2908 2902 r_dcache_vci_miss_req = true; 2903 r_tlb_access_type_save = (r_dcache_tlb_ins.read()) ? _CMD_ITLB : _CMD_DTLB; 2909 2904 2910 2905 #if DEBUG_DCACHE … … 3121 3116 r_dcache_fsm = DCACHE_MISS_VICTIM; 3122 3117 r_dcache_vci_miss_req = true; 3118 r_tlb_access_type_save = (r_dcache_tlb_ins.read()) ? _CMD_ITLB : _CMD_DTLB; 3123 3119 3124 3120 #if DEBUG_DCACHE … … 3271 3267 // we don't analyse the response, because 3272 3268 // we don't care if the L/R bit update is not done 3273 { 3269 // we must take the coherence requests because 3270 // there is a risk of dead-lock 3271 3272 { 3273 // external coherence request 3274 if ( r_tgt_dcache_req ) 3275 { 3276 r_dcache_fsm = DCACHE_CC_CHECK; 3277 r_dcache_fsm_save = r_dcache_fsm; 3278 break; 3279 } 3280 3274 3281 if ( not r_dcache_vci_sc_req.read() ) // response available 3275 3282 { … … 3319 3326 r_dcache_fsm = DCACHE_IDLE; 3320 3327 } 3328 3321 3329 break; 3322 3330 } … … 3368 3376 3369 3377 bool cleanup_req = r_dcache.inval( way, 3370 3371 3378 set, 3379 &nline ); 3372 3380 if ( cleanup_req ) 3373 3381 { … … 3562 3570 if ( m_debug_dcache_fsm ) 3563 3571 { 3564 std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" 3572 std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::hex 3565 3573 << " / way = " << way 3566 3574 << " / set = " << set … … 3573 3581 /////////////////////// 3574 3582 case DCACHE_MISS_INVAL: // invalidate the victim line 3575 3583 // and possibly request itlb or dtlb invalidate 3576 3584 { 3577 3585 paddr_t nline; 3578 3586 size_t way = r_dcache_miss_way.read(); 3579 3587 size_t set = r_dcache_miss_set.read(); 3580 3581 r_dcache.inval( way, 3582 set, 3583 &nline ); 3588 bool isValid; 3589 3590 isValid = r_dcache.inval( way, 3591 set, 3592 &nline ); 3593 3594 3595 std::cout << "DMISS_INVAL: way " << way 3596 << " / set " << set 3597 << " / nline " << std::hex << nline 3598 << " / isValid " << isValid 3599 << std::endl; 3584 3600 3585 3601 // if itlb & dtlb invalidate are required … … 3588 3604 ( r_dcache_in_itlb[way*m_dcache_sets+set] or 3589 3605 r_dcache_in_dtlb[m_dcache_sets*way+set] ) ) 3590 3591 3592 3593 3594 3595 3606 { 3607 r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2); 3608 r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set]; 3609 r_dcache_in_itlb[way*m_dcache_sets+set] = false; 3610 r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set]; 3611 r_dcache_in_dtlb[way*m_dcache_sets+set] = false; 3596 3612 r_dcache_fsm = DCACHE_MISS_INVAL_WAIT; 3597 3613 } 3598 3614 else 3599 3615 { 3600 3616 r_dcache_fsm = DCACHE_MISS_WAIT; 3601 3617 } 3618 3602 3619 break; 3603 3620 } … … 3681 3698 { 3682 3699 r_dcache_miss_word = 0; 3683 3700 r_dcache_fsm = DCACHE_MISS_UPDT; 3684 3701 } 3685 3702 break; … … 3767 3784 else 3768 3785 { 3769 std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:" 3786 std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:" << std::hex 3770 3787 << " address = " << r_dcache_vci_paddr.read() 3771 3788 << " / data = " << r_vci_rsp_fifo_dcache.read() … … 3834 3851 m_cpt_dcache_data_read++; 3835 3852 m_cpt_dcache_dir_read++; 3836 #endif ;3853 #endif 3837 3854 3838 3855 #if DEBUG_DCACHE 3839 3856 if ( m_debug_dcache_fsm ) 3840 3857 { 3841 std::cout << " <PROC.DCACHE_WRITE_TLB_DIRTY> Set PTE dirty bit in dtlb:" 3858 std::cout << " <PROC.DCACHE_WRITE_TLB_DIRTY> Set PTE dirty bit in dtlb:" << std::hex 3842 3859 << " paddr = " << r_dcache_p2_pte_paddr.read() 3843 3860 << " / tlb_way = " << r_dcache_p2_tlb_way.read() … … 3872 3889 if ( m_debug_dcache_fsm ) 3873 3890 { 3874 std::cout << " <PROC.DCACHE_WRITE_CACHE_DIRTY> Set PTE dirty bit in dcache:" 3891 std::cout << " <PROC.DCACHE_WRITE_CACHE_DIRTY> Set PTE dirty bit in dcache:" << std::hex 3875 3892 << " / way = " << r_dcache_p2_pte_way.read() 3876 3893 << " / set = " << r_dcache_p2_pte_set.read() … … 4139 4156 std::cout << " <PROC.DCACHE_CC_UPDT> Update one word :" << std::dec 4140 4157 << " way = " << way 4141 << " / set = " << set 4158 << " / set = " << set 4142 4159 << " / word = " << word 4143 4160 << " / value = " << std::hex << r_tgt_buf[word] << std::endl; … … 4245 4262 { 4246 4263 m_cpt_frz_cycles++; // used for instrumentation 4264 4265 if(dreq.valid and not drsp.valid) 4266 m_cpt_dcache_frz_cycles++; 4267 4247 4268 m_cpt_stop_simulation++; // used for debug 4248 4269 if ( m_cpt_stop_simulation > m_max_frozen_cycles ) … … 4342 4363 r_icache_miss_req = false; 4343 4364 r_vci_cmd_imiss_prio = false; 4344 // 4365 // m_cpt_imiss_transaction++; 4345 4366 } 4346 4367 // 4 - Instruction Uncachable … … 4349 4370 r_vci_cmd_fsm = CMD_INS_UNC; 4350 4371 r_icache_unc_req = false; 4351 // 4372 // m_cpt_iunc_transaction++; 4352 4373 } 4353 4374 // 5 - Data Write … … 4358 4379 r_vci_cmd_min = wbuf_min; 4359 4380 r_vci_cmd_max = wbuf_max; 4360 // 4361 // 4381 // m_cpt_write_transaction++; 4382 // m_length_write_transaction += (wbuf_max-wbuf_min+1); 4362 4383 } 4363 4384 // 6 - Data Store Conditionnal … … 4806 4827 p_vci_ini_d.cmd = vci_param::CMD_READ; 4807 4828 p_vci_ini_d.eop = true; 4829 p_vci_ini_d.pktid = (r_ireq_isUser_save == true) ? _CMD_USR : 0; 4808 4830 break; 4809 4831 … … 4817 4839 p_vci_ini_d.cmd = vci_param::CMD_READ; 4818 4840 p_vci_ini_d.eop = true; 4841 p_vci_ini_d.pktid = (r_ireq_isUser_save == true) ? _CMD_USR : 0; 4819 4842 break; 4820 4843 … … 4828 4851 p_vci_ini_d.cmd = vci_param::CMD_READ; 4829 4852 p_vci_ini_d.eop = true; 4853 p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR | r_tlb_access_type_save.read() : 0; 4830 4854 break; 4831 4855 … … 4839 4863 p_vci_ini_d.cmd = vci_param::CMD_READ; 4840 4864 p_vci_ini_d.eop = true; 4865 p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0; 4841 4866 break; 4842 4867 … … 4850 4875 p_vci_ini_d.cmd = vci_param::CMD_WRITE; 4851 4876 p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); 4877 p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0; 4852 4878 break; 4853 4879 … … 4862 4888 p_vci_ini_d.cmd = vci_param::CMD_STORE_COND; 4863 4889 p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1); 4890 p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0; 4864 4891 break; 4865 4892 } // end switch r_vci_cmd_fsm
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