Changeset 198 for trunk/modules/vci_cc_vcache_wrapper_v4
- Timestamp:
- Feb 20, 2012, 7:25:35 PM (13 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
r197 r198 34 34 #define DEBUG_INVAL_ITLB 1 35 35 #define DEBUG_INVAL_DTLB 1 36 37 #define _CMD_INIT_VAL 0x0038 #define _CMD_ITLB 0x0139 #define _CMD_DTLB 0x0240 #define _CMD_USR 0x0441 36 42 37 namespace soclib { … … 398 393 "icache_words and dcache_words parameters must be equal"); 399 394 400 { 401 uint32_t val; 402 403 val = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | 404 (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | 405 (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | 406 (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | 407 (uint32_log2(m_icache_words<<2)); 408 409 //r_mmu_params = val; 410 m_mmu_params = val; 411 412 val = (1 << 16) | 0x1; 413 //r_mmu_release = val; 414 m_mmu_release = val; 415 } 416 395 r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | 396 (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | 397 (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | 398 (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | 399 (uint32_log2(m_icache_words<<2)); 400 401 r_mmu_release = (uint32_t)(1 << 16) | 0x1; 417 402 418 403 r_tgt_buf = new uint32_t[dcache_words]; … … 420 405 r_dcache_in_itlb = new bool[dcache_ways*dcache_sets]; 421 406 r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets]; 422 423 424 m_proc_id = proc_id;425 426 m_tm_start = 0;427 m_tm_end = 0;428 m_period = 0;429 430 char *ptr;431 432 ptr = getenv("TSAR_L1_TM_START");433 434 if(ptr != NULL)435 m_tm_start = (size_t) atol(ptr);436 437 ptr = getenv("TSAR_L1_TM_END");438 439 if(ptr != NULL)440 m_tm_end = (size_t) atol(ptr);441 442 ptr = getenv("TSAR_L1_PERIOD");443 444 if(ptr != NULL)445 m_period = (size_t) atol(ptr);446 447 if(m_period != 0)448 m_log.open(name, std::ios::out);449 450 if(m_proc_id == 0)451 {452 std::cout << "TSAR_L1_TM_START =" << m_tm_start << std::endl453 << "TSAR_L1_TM_END =" << m_tm_end << std::endl454 << "TSAR_L1_PERIOD =" << m_period << std::endl;455 }456 457 407 458 408 SC_METHOD(transition); … … 585 535 586 536 537 538 /* 587 539 //////////////////////// 588 540 tmpl(void)::print_stats() 589 541 //////////////////////// 590 542 { 591 std::ostream &output = (m_period == 0) ? std::cout : m_log;592 593 543 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); 594 output << name() << std::endl595 << "CPI= " << (float)m_cpt_total_cycles/run_cycles << std::endl596 << "READ_RATE = " << (float)m_cpt_data_read/run_cycles << std::endl597 << "WRITE_RATE = " << (float)m_cpt_data_write/run_cycles << std::endl598 << "IMISS_RATE= " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl599 << "DMISS_RATE = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl600 << "INS_MISS_COST= " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl601 << "DATA_MISS_COST= " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl602 << "WRITE_COST = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl603 << "UNC_COST= " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl604 << "UNCACHED_READ_RATE = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl605 << "CACHED_WRITE_RATE = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl606 << "INS_TLB_MISS_RATE= " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl607 << "DATA_TLB_MISS_RATE= " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl608 << "ITLB_MISS_COST= " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl609 << "DTLB_MISS_COST= " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl610 << "ITLB_UPDATE_ACC_COST= " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl611 << "DTLB_UPDATE_ACC_COST= " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl612 << "DTLB_UPDATE_DIRTY_COST= " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl613 << "ITLB_HIT_IN_DCACHE_RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl614 << "DTLB_HIT_IN_DCACHE_RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl615 << "DCACHE FROZEN BY ITLB= " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl616 << "DCACHE_FOR_TLB_%= " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl617 << "NB_CC_BROADCAST= " << m_cpt_cc_broadcast << std::endl618 << "NB_CC_UPDATE_DATA = " << m_cpt_cc_update_dcache<< std::endl619 << "NB_CC_INVAL_DATA = " << m_cpt_cc_inval_dcache<< std::endl620 << "NB_CC_INVAL_INS = " << m_cpt_cc_inval_icache<< std::endl621 << "NB_CC_CLEANUP_DATA = " << m_cpt_cc_cleanup_data<< std::endl622 << "NB_CC_CLEANUP_INS = " << m_cpt_cc_cleanup_ins<< std::endl623 << "CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast<< std::endl624 << "CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache<< std::endl625 << "CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache<< std::endl626 << "CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache<< std::endl627 << "IMISS_TRANSACTION= " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl628 << "DMISS_TRANSACTION= " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl629 << "UNC_TRANSACTION= " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl630 << "WRITE_TRANSACTION= " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl631 << "WRITE_LENGTH= " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl632 << "ITLB_MISS_TRANSACTION= " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl633 << "DTLB_MISS_TRANSACTION= " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;544 std::cout << name() << std::endl 545 << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl 546 << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl 547 << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl 548 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 549 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 550 << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 551 << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 552 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl 553 << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 554 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 555 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 556 << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 557 << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 558 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl 559 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl 560 << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl 561 << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl 562 << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 563 << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl 564 << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl 565 << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl 566 << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl 567 << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl 568 << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl 569 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl 570 << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl 571 << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl 572 << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl 573 << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl 574 << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl 575 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl 576 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl 577 << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 578 << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 579 << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 580 << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 581 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 582 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 583 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; 634 584 } 635 636 585 637 586 //////////////////////// … … 652 601 m_cpt_total_cycles = 0; 653 602 654 m_cpt_ data_read = 0;655 m_cpt_ data_write = 0;603 m_cpt_read = 0; 604 m_cpt_write = 0; 656 605 m_cpt_data_miss = 0; 657 606 m_cpt_ins_miss = 0; … … 681 630 m_cpt_ins_tlb_miss = 0; 682 631 m_cpt_ins_tlb_update_acc = 0; 683 m_cpt_ins_tlb_occup_cache = 0; 684 m_cpt_ins_tlb_hit_dcache = 0; 685 632 686 633 m_cpt_data_tlb_read = 0; 687 634 m_cpt_data_tlb_miss = 0; 688 635 m_cpt_data_tlb_update_acc = 0; 689 636 m_cpt_data_tlb_update_dirty = 0; 637 m_cpt_ins_tlb_hit_dcache = 0; 690 638 m_cpt_data_tlb_hit_dcache = 0; 639 m_cpt_ins_tlb_occup_cache = 0; 691 640 m_cpt_data_tlb_occup_cache = 0; 692 641 … … 717 666 m_cost_dtlb_sc_dirty_transaction = 0; 718 667 719 m_cpt_cc_update_icache = 0; 720 m_cpt_cc_update_dcache = 0; 721 m_cpt_cc_inval_icache = 0; 722 m_cpt_cc_inval_dcache = 0; 723 m_cpt_cc_broadcast = 0; 668 m_cpt_cc_update_data = 0; 669 m_cpt_cc_inval_ins = 0; 670 m_cpt_cc_inval_data = 0; 671 m_cpt_cc_broadcast = 0; 724 672 725 673 m_cost_updt_data_frz = 0; … … 730 678 m_cpt_cc_cleanup_data = 0; 731 679 m_cpt_cc_cleanup_ins = 0; 732 733 m_cpt_icleanup_transaction = 0;734 m_cpt_dcleanup_transaction = 0;735 m_cost_icleanup_transaction = 0;736 m_cost_dcleanup_transaction = 0;737 738 m_cpt_ins_tlb_inval = 0;739 m_cost_data_tlb_inval_frz = 0;740 m_cost_ins_tlb_inval_frz = 0;741 680 } 742 681 682 */ 743 683 744 684 ///////////////////////// … … 776 716 r_mmu_mode = 0x3; 777 717 778 718 // No request from ICACHE FSM to CMD FSM 779 719 r_icache_miss_req = false; 780 720 r_icache_unc_req = false; … … 799 739 800 740 // No LL reservation 801 741 r_dcache_ll_valid = false; 802 742 803 743 // No request from DCACHE FSM to INVAL TLB FSMs … … 831 771 m_debug_inval_dtlb_fsm = false; 832 772 833 clear_stats(); 834 835 /* 773 /* 774 // activity counters 775 m_cpt_dcache_data_read = 0; 776 m_cpt_dcache_data_write = 0; 777 m_cpt_dcache_dir_read = 0; 778 m_cpt_dcache_dir_write = 0; 779 m_cpt_icache_data_read = 0; 780 m_cpt_icache_data_write = 0; 781 m_cpt_icache_dir_read = 0; 782 m_cpt_icache_dir_write = 0; 783 784 m_cpt_frz_cycles = 0; 785 m_cpt_dcache_frz_cycles = 0; 786 m_cpt_total_cycles = 0; 787 788 m_cpt_read = 0; 789 m_cpt_write = 0; 790 m_cpt_data_miss = 0; 791 m_cpt_ins_miss = 0; 792 m_cpt_unc_read = 0; 793 m_cpt_write_cached = 0; 794 m_cpt_ins_read = 0; 795 796 m_cost_write_frz = 0; 797 m_cost_data_miss_frz = 0; 798 m_cost_unc_read_frz = 0; 799 m_cost_ins_miss_frz = 0; 800 801 m_cpt_imiss_transaction = 0; 802 m_cpt_dmiss_transaction = 0; 803 m_cpt_unc_transaction = 0; 804 m_cpt_write_transaction = 0; 805 m_cpt_icache_unc_transaction = 0; 806 807 m_cost_imiss_transaction = 0; 808 m_cost_dmiss_transaction = 0; 809 m_cost_unc_transaction = 0; 810 m_cost_write_transaction = 0; 811 m_cost_icache_unc_transaction = 0; 812 m_length_write_transaction = 0; 813 814 m_cpt_ins_tlb_read = 0; 815 m_cpt_ins_tlb_miss = 0; 816 m_cpt_ins_tlb_update_acc = 0; 817 818 m_cpt_data_tlb_read = 0; 819 m_cpt_data_tlb_miss = 0; 820 m_cpt_data_tlb_update_acc = 0; 821 m_cpt_data_tlb_update_dirty = 0; 822 m_cpt_ins_tlb_hit_dcache = 0; 823 m_cpt_data_tlb_hit_dcache = 0; 824 m_cpt_ins_tlb_occup_cache = 0; 825 m_cpt_data_tlb_occup_cache = 0; 826 827 m_cost_ins_tlb_miss_frz = 0; 828 m_cost_data_tlb_miss_frz = 0; 829 m_cost_ins_tlb_update_acc_frz = 0; 830 m_cost_data_tlb_update_acc_frz = 0; 831 m_cost_data_tlb_update_dirty_frz = 0; 832 m_cost_ins_tlb_occup_cache_frz = 0; 833 m_cost_data_tlb_occup_cache_frz = 0; 834 835 m_cpt_ins_tlb_inval = 0; 836 m_cpt_data_tlb_inval = 0; 837 m_cost_ins_tlb_inval_frz = 0; 838 m_cost_data_tlb_inval_frz = 0; 839 840 m_cpt_cc_update_data = 0; 841 m_cpt_cc_inval_ins = 0; 842 m_cpt_cc_inval_data = 0; 843 m_cpt_cc_broadcast = 0; 844 845 m_cost_updt_data_frz = 0; 846 m_cost_inval_ins_frz = 0; 847 m_cost_inval_data_frz = 0; 848 m_cost_broadcast_frz = 0; 849 850 m_cpt_cc_cleanup_data = 0; 851 m_cpt_cc_cleanup_ins = 0; 852 853 m_cpt_itlbmiss_transaction = 0; 854 m_cpt_itlb_ll_transaction = 0; 855 m_cpt_itlb_sc_transaction = 0; 856 m_cpt_dtlbmiss_transaction = 0; 857 m_cpt_dtlb_ll_transaction = 0; 858 m_cpt_dtlb_sc_transaction = 0; 859 m_cpt_dtlb_ll_dirty_transaction = 0; 860 m_cpt_dtlb_sc_dirty_transaction = 0; 861 862 m_cost_itlbmiss_transaction = 0; 863 m_cost_itlb_ll_transaction = 0; 864 m_cost_itlb_sc_transaction = 0; 865 m_cost_dtlbmiss_transaction = 0; 866 m_cost_dtlb_ll_transaction = 0; 867 m_cost_dtlb_sc_transaction = 0; 868 m_cost_dtlb_ll_dirty_transaction = 0; 869 m_cost_dtlb_sc_dirty_transaction = 0; 870 836 871 for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; 837 872 for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; … … 841 876 for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0; 842 877 for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0; 843 */ 844 845 //// For instrumentation only 846 r_ireq_isUser_save = false; 847 r_dreq_isUser_save = false; 848 r_tlb_access_type_save = _CMD_INIT_VAL; 878 879 */ 849 880 return; 850 881 } … … 869 900 870 901 m_cpt_total_cycles++; 871 872 873 if((m_period != 0) && ((m_cpt_total_cycles % m_period) == 0))874 {875 print_stats();876 clear_stats();877 }878 902 879 903 m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; … … 1186 1210 // - Coherence operation => ICACHE_CC_CHEK 1187 1211 // Five configurations corresponding to XTN processor requests sent by DCACHE FSM : 1188 // - Flush TLB 1189 // - Flush cache 1212 // - Flush TLB => ICACHE_XTN_TLB_FLUSH 1213 // - Flush cache => ICACHE_XTN_CACHE_FLUSH 1190 1214 // - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL 1191 1215 // - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@ 1192 1216 // - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA 1193 1217 // three configurations corresponding to instruction processor requests : 1194 // - tlb miss 1218 // - tlb miss => ICACHE_TLB_WAIT 1195 1219 // - cacheable read miss => ICACHE_MISS_VICTIM 1196 1220 // - uncacheable read miss => ICACHE_UNC_REQ … … 1240 1264 // for itlb, and with a speculative physical address for icache, 1241 1265 // computed during the previous cycle. 1242 { 1243 1244 // For instrumentation: flag reset 1245 r_ireq_isUser_save = false; 1246 1266 { 1247 1267 // coherence request from the target FSM 1248 1268 if ( r_tgt_icache_req.read() ) … … 1302 1322 uint32_t cache_inst = 0; 1303 1323 bool cache_hit = false; 1304 1305 // For instrumentation: is User access ?1306 r_ireq_isUser_save = (ireq.mode == iss_t::MODE_USER) ? true : false;1307 1324 1308 1325 if ( r_mmu_mode.read() & INS_CACHE_MASK ) … … 1422 1439 r_icache_fsm = ICACHE_MISS_VICTIM; 1423 1440 r_icache_miss_req = true; 1424 r_tlb_access_type_save = _CMD_INIT_VAL;1425 1441 } 1426 1442 } … … 1685 1701 } 1686 1702 1687 1688 1703 if ( r_vci_rsp_ins_error.read() ) // bus error 1704 { 1689 1705 r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; 1690 1706 r_mmu_ibvar = r_icache_vaddr_save.read(); … … 1698 1714 r_icache_miss_word = 0; 1699 1715 r_icache_fsm = ICACHE_MISS_UPDT; 1700 1716 } 1701 1717 break; 1702 1718 } … … 2026 2042 case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state : 2027 2043 // 1) Long write request (DCACHE FSM) => DCACHE_WRITE_*** 2028 // 2) Coherence request (TGT FSM) 2044 // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK 2029 2045 // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS 2030 // 4) XTN request (processor) 2031 // 5) DTLB miss (processor) 2046 // 4) XTN request (processor) => DCACHE_XTN_* 2047 // 5) DTLB miss (processor) => DCACHE_TLB_MISS 2032 2048 // 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM 2033 // 7) Uncacheable read (processor) 2034 // 8) SC access (processor) 2049 // 7) Uncacheable read (processor) => DCACHE_UNC_REQ 2050 // 8) SC access (processor) => DCACHE_SC 2035 2051 // There is 4 configurations to access the cache, 2036 2052 // depending on the pipe-line state, defined … … 2061 2077 bool long_write_set_dirty = false; 2062 2078 bool tlb_inval_frozen = false; 2063 2064 // For instrumentation: flag reset2065 r_dreq_isUser_save = false;2066 2079 2067 2080 if ( r_dcache_p1_valid.read() ) // P2 stage activated … … 2128 2141 2129 2142 #if DEBUG_DCACHE 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 if ( m_debug_dcache_fsm ) 2144 { 2145 if ( cache_updt ) 2146 std::cout << " <PROC.DCACHE_IDLE> P2 stage: cache update" << std::dec 2147 << " / way = " << cache_way 2148 << " / set = " << cache_set 2149 << " / word = " << cache_word << std::hex 2150 << " / wdata = " << wdata 2151 << " / be = " << be << std::endl; 2152 if ( long_write_set_dirty ) 2153 std::cout << " <PROC.DCACHE_IDLE> P2 stage: dirty bit update required" 2154 << " / pte_paddr = " << std::hex << pte_paddr << std::endl; 2155 } 2143 2156 #endif 2144 2157 } // end P2 stage … … 2395 2408 2396 2409 case iss_t::XTN_MMU_PARAMS: 2397 //drsp.rdata = r_mmu_params.read(); 2398 drsp.rdata = m_mmu_params; 2410 drsp.rdata = r_mmu_params.read(); 2399 2411 drsp.valid = true; 2400 2412 break; 2401 2413 2402 2414 case iss_t::XTN_MMU_RELEASE: 2403 //drsp.rdata = r_mmu_release.read(); 2404 drsp.rdata = m_mmu_release; 2415 drsp.rdata = r_mmu_release.read(); 2405 2416 drsp.valid = true; 2406 2417 break; … … 2552 2563 else 2553 2564 { 2554 2555 // For instrumentation: is User access ?2556 r_dreq_isUser_save = (dreq.mode == iss_t::MODE_USER) ? true : false;2557 2558 2565 bool valid_req = false; 2559 2566 bool cacheable = false; … … 2652 2659 if ( not r_dcache_cleanup_req.read() ) 2653 2660 { 2654 r_dcache_vci_paddr = paddr; 2655 r_dcache_vci_miss_req = true; 2656 r_dcache_miss_type = PROC_MISS; 2657 r_dcache_fsm = DCACHE_MISS_VICTIM; 2658 r_tlb_access_type_save = _CMD_INIT_VAL; 2661 r_dcache_vci_paddr = paddr; 2662 r_dcache_vci_miss_req = true; 2663 r_dcache_miss_type = PROC_MISS; 2664 r_dcache_fsm = DCACHE_MISS_VICTIM; 2659 2665 } 2660 2666 } … … 2832 2838 if ( m_debug_dcache_fsm ) 2833 2839 { 2834 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped:" << std::hex2840 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped:" 2835 2841 << std::dec << " way = " << way 2836 2842 << std::dec << " / set = " << set … … 2863 2869 if ( m_debug_dcache_fsm ) 2864 2870 { 2865 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache " << std::hex2871 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache " 2866 2872 << std::dec << " way = " << way 2867 2873 << std::dec << " / set = " << set … … 2886 2892 if ( m_debug_dcache_fsm ) 2887 2893 { 2888 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache:" << std::hex2894 std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache:" 2889 2895 << std::dec << " way = " << way 2890 2896 << std::dec << " / set = " << set … … 2901 2907 r_dcache_fsm = DCACHE_MISS_VICTIM; 2902 2908 r_dcache_vci_miss_req = true; 2903 r_tlb_access_type_save = (r_dcache_tlb_ins.read()) ? _CMD_ITLB : _CMD_DTLB;2904 2909 2905 2910 #if DEBUG_DCACHE … … 3116 3121 r_dcache_fsm = DCACHE_MISS_VICTIM; 3117 3122 r_dcache_vci_miss_req = true; 3118 r_tlb_access_type_save = (r_dcache_tlb_ins.read()) ? _CMD_ITLB : _CMD_DTLB;3119 3123 3120 3124 #if DEBUG_DCACHE … … 3267 3271 // we don't analyse the response, because 3268 3272 // we don't care if the L/R bit update is not done 3269 // we must take the coherence requests because 3270 // there is a risk of dead-lock 3271 3272 { 3273 // external coherence request 3274 if ( r_tgt_dcache_req ) 3275 { 3276 r_dcache_fsm = DCACHE_CC_CHECK; 3277 r_dcache_fsm_save = r_dcache_fsm; 3278 break; 3279 } 3280 3273 { 3281 3274 if ( not r_dcache_vci_sc_req.read() ) // response available 3282 3275 { … … 3326 3319 r_dcache_fsm = DCACHE_IDLE; 3327 3320 } 3328 3329 3321 break; 3330 3322 } … … 3376 3368 3377 3369 bool cleanup_req = r_dcache.inval( way, 3378 set,3379 &nline );3370 set, 3371 &nline ); 3380 3372 if ( cleanup_req ) 3381 3373 { … … 3570 3562 if ( m_debug_dcache_fsm ) 3571 3563 { 3572 std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::hex3564 std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" 3573 3565 << " / way = " << way 3574 3566 << " / set = " << set … … 3581 3573 /////////////////////// 3582 3574 case DCACHE_MISS_INVAL: // invalidate the victim line 3583 // and possibly request itlb or dtlb invalidate3575 // and possibly request itlb or dtlb invalidate 3584 3576 { 3585 3577 paddr_t nline; 3586 3578 size_t way = r_dcache_miss_way.read(); 3587 3579 size_t set = r_dcache_miss_set.read(); 3588 bool isValid; 3589 3590 isValid = r_dcache.inval( way, 3591 set, 3592 &nline ); 3593 3594 3595 std::cout << "DMISS_INVAL: way " << way 3596 << " / set " << set 3597 << " / nline " << std::hex << nline 3598 << " / isValid " << isValid 3599 << std::endl; 3580 3581 r_dcache.inval( way, 3582 set, 3583 &nline ); 3600 3584 3601 3585 // if itlb & dtlb invalidate are required … … 3604 3588 ( r_dcache_in_itlb[way*m_dcache_sets+set] or 3605 3589 r_dcache_in_dtlb[m_dcache_sets*way+set] ) ) 3606 3607 3608 3609 3610 3611 3590 { 3591 r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2); 3592 r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set]; 3593 r_dcache_in_itlb[way*m_dcache_sets+set] = false; 3594 r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set]; 3595 r_dcache_in_dtlb[way*m_dcache_sets+set] = false; 3612 3596 r_dcache_fsm = DCACHE_MISS_INVAL_WAIT; 3613 3597 } 3614 3598 else 3615 3599 { 3616 3600 r_dcache_fsm = DCACHE_MISS_WAIT; 3617 3601 } 3618 3619 3602 break; 3620 3603 } … … 3698 3681 { 3699 3682 r_dcache_miss_word = 0; 3700 3683 r_dcache_fsm = DCACHE_MISS_UPDT; 3701 3684 } 3702 3685 break; … … 3784 3767 else 3785 3768 { 3786 std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:" << std::hex3769 std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:" 3787 3770 << " address = " << r_dcache_vci_paddr.read() 3788 3771 << " / data = " << r_vci_rsp_fifo_dcache.read() … … 3851 3834 m_cpt_dcache_data_read++; 3852 3835 m_cpt_dcache_dir_read++; 3853 #endif 3836 #endif; 3854 3837 3855 3838 #if DEBUG_DCACHE 3856 3839 if ( m_debug_dcache_fsm ) 3857 3840 { 3858 std::cout << " <PROC.DCACHE_WRITE_TLB_DIRTY> Set PTE dirty bit in dtlb:" << std::hex3841 std::cout << " <PROC.DCACHE_WRITE_TLB_DIRTY> Set PTE dirty bit in dtlb:" 3859 3842 << " paddr = " << r_dcache_p2_pte_paddr.read() 3860 3843 << " / tlb_way = " << r_dcache_p2_tlb_way.read() … … 3889 3872 if ( m_debug_dcache_fsm ) 3890 3873 { 3891 std::cout << " <PROC.DCACHE_WRITE_CACHE_DIRTY> Set PTE dirty bit in dcache:" << std::hex3874 std::cout << " <PROC.DCACHE_WRITE_CACHE_DIRTY> Set PTE dirty bit in dcache:" 3892 3875 << " / way = " << r_dcache_p2_pte_way.read() 3893 3876 << " / set = " << r_dcache_p2_pte_set.read() … … 4156 4139 std::cout << " <PROC.DCACHE_CC_UPDT> Update one word :" << std::dec 4157 4140 << " way = " << way 4158 << " / set = " << set 4141 << " / set = " << set 4159 4142 << " / word = " << word 4160 4143 << " / value = " << std::hex << r_tgt_buf[word] << std::endl; … … 4262 4245 { 4263 4246 m_cpt_frz_cycles++; // used for instrumentation 4264 4265 if(dreq.valid and not drsp.valid)4266 m_cpt_dcache_frz_cycles++;4267 4268 4247 m_cpt_stop_simulation++; // used for debug 4269 4248 if ( m_cpt_stop_simulation > m_max_frozen_cycles ) … … 4363 4342 r_icache_miss_req = false; 4364 4343 r_vci_cmd_imiss_prio = false; 4365 // m_cpt_imiss_transaction++;4344 // m_cpt_imiss_transaction++; 4366 4345 } 4367 4346 // 4 - Instruction Uncachable … … 4370 4349 r_vci_cmd_fsm = CMD_INS_UNC; 4371 4350 r_icache_unc_req = false; 4372 // m_cpt_iunc_transaction++;4351 // m_cpt_iunc_transaction++; 4373 4352 } 4374 4353 // 5 - Data Write … … 4379 4358 r_vci_cmd_min = wbuf_min; 4380 4359 r_vci_cmd_max = wbuf_max; 4381 // m_cpt_write_transaction++;4382 // m_length_write_transaction += (wbuf_max-wbuf_min+1);4360 // m_cpt_write_transaction++; 4361 // m_length_write_transaction += (wbuf_max-wbuf_min+1); 4383 4362 } 4384 4363 // 6 - Data Store Conditionnal … … 4827 4806 p_vci_ini_d.cmd = vci_param::CMD_READ; 4828 4807 p_vci_ini_d.eop = true; 4829 p_vci_ini_d.pktid = (r_ireq_isUser_save == true) ? _CMD_USR : 0;4830 4808 break; 4831 4809 … … 4839 4817 p_vci_ini_d.cmd = vci_param::CMD_READ; 4840 4818 p_vci_ini_d.eop = true; 4841 p_vci_ini_d.pktid = (r_ireq_isUser_save == true) ? _CMD_USR : 0;4842 4819 break; 4843 4820 … … 4851 4828 p_vci_ini_d.cmd = vci_param::CMD_READ; 4852 4829 p_vci_ini_d.eop = true; 4853 p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR | r_tlb_access_type_save.read() : 0;4854 4830 break; 4855 4831 … … 4863 4839 p_vci_ini_d.cmd = vci_param::CMD_READ; 4864 4840 p_vci_ini_d.eop = true; 4865 p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0;4866 4841 break; 4867 4842 … … 4875 4850 p_vci_ini_d.cmd = vci_param::CMD_WRITE; 4876 4851 p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); 4877 p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0;4878 4852 break; 4879 4853 … … 4888 4862 p_vci_ini_d.cmd = vci_param::CMD_STORE_COND; 4889 4863 p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1); 4890 p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0;4891 4864 break; 4892 4865 } // end switch r_vci_cmd_fsm
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