Changeset 260 for trunk/modules/vci_block_device_tsar_v4/caba/source/include/vci_block_device_tsar_v4.h
- Timestamp:
- Sep 4, 2012, 6:47:24 PM (12 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_block_device_tsar_v4/caba/source/include/vci_block_device_tsar_v4.h
r187 r260 32 32 // This component can perform data transfers between one single file belonging 33 33 // to the host system and a buffer in the memory of the virtual prototype. 34 // The file name is an argument of the constructor, 35 // as well as the block size (bytes), and the burst size (bytes). 34 // The file name is an argument of the constructor. 36 35 // This component has a DMA capability, and is both a target and an initiator. 36 // The block size (bytes), and the burst size (bytes) must be power of 2. 37 // The burst size is typically a cache line. 38 // If the memory buffer is not constrained to be aligned on a burst boundary. 37 39 // Both read and write transfers are supported. An IRQ is optionally 38 40 // asserted when the transfer is completed. … … 92 94 93 95 // Registers 94 sc_signal<int> r_target_fsm; // target fsm state register 95 sc_signal<int> r_initiator_fsm; // initiator fsm state register 96 sc_signal<bool> r_irq_enable; // default value is true 97 sc_signal<uint32_t> r_nblocks; // number of blocks to be transfered 98 sc_signal<uint32_t> r_buf_address; // memory buffer address 99 sc_signal<uint32_t> r_lba; // first block index 100 sc_signal<bool> r_read; // requested operation 101 sc_signal<uint32_t> r_flit_count; // flit counter (in a burst) 102 sc_signal<uint32_t> r_burst_count; // burst counter (in a block) 103 sc_signal<uint32_t> r_block_count; // block counter (in a transfer) 104 sc_signal<uint32_t> r_latency_count; // latency access (for each block) 105 sc_signal<bool> r_go; // transmit command from T_FSM to M_FSM 96 sc_signal<int> r_target_fsm; // target fsm state register 97 sc_signal<int> r_initiator_fsm; // initiator fsm state register 98 sc_signal<bool> r_irq_enable; // default value is true 99 sc_signal<uint32_t> r_nblocks; // number of blocks in transfer 100 sc_signal<uint32_t> r_buf_address; // memory buffer address 101 sc_signal<uint32_t> r_lba; // first block index 102 sc_signal<bool> r_read; // requested operation 103 sc_signal<uint32_t> r_index; // flit index in local buffer 104 sc_signal<uint32_t> r_latency_count; // latency counter 105 sc_signal<uint32_t> r_flit_count; // flit counter (in a burst) 106 sc_signal<uint32_t> r_burst_count; // burst counter (in a block) 107 sc_signal<uint32_t> r_block_count; // block counter (in a transfer) 108 sc_signal<uint32_t> r_burst_offset; // number of non aligned flits 109 sc_signal<uint32_t> r_burst_nflits; // number of flits in a burst 110 sc_signal<bool> r_go; // command from T_FSM to M_FSM 111 106 112 sc_signal<sc_dt::sc_uint<vci_param::S> > r_srcid; // save srcid 107 113 sc_signal<sc_dt::sc_uint<vci_param::T> > r_trdid; // save trdid 108 114 sc_signal<sc_dt::sc_uint<vci_param::P> > r_pktid; // save pktid 109 115 110 uint32_t* m_local_buffer; // capacity is one block (block_size bytes)116 uint32_t* r_local_buffer; // capacity is one block 111 117 112 118 // structural parameters 113 soclib::common::Segment m_segment;// segment associated to target114 uint32_t m_srcid;// initiator index115 int m_fd;// File descriptor116 uint64_t m_device_size;// Total number of blocks117 const uint32_t m_flits_per_block;// number of flits in a block118 const uint32_t m_flits_per_burst;// number of flits in a burst119 const uint32_t m_bursts_per_block;// number of bursts in a block120 const uint32_t m_latency;// device latency119 soclib::common::Segment m_segment; // segment associated to target 120 uint32_t m_srcid; // initiator index 121 int m_fd; // File descriptor 122 uint64_t m_device_size; // Total number of blocks 123 const uint32_t m_flits_per_block; // number of flits in a block 124 const uint32_t m_flits_per_burst; // number of flits in a burst 125 const uint32_t m_bursts_per_block; // number of bursts in a block 126 const uint32_t m_latency; // device latency 121 127 122 128 // methods … … 127 133 enum { 128 134 M_IDLE = 0, 135 129 136 M_READ_BLOCK = 1, 130 M_READ_ CMD= 2,131 M_READ_ RSP= 3,132 M_READ_ TEST= 4,137 M_READ_BURST = 2, 138 M_READ_CMD = 3, 139 M_READ_RSP = 4, 133 140 M_READ_SUCCESS = 5, 134 141 M_READ_ERROR = 6, 135 M_WRITE_BLOCK = 7, 142 143 M_WRITE_BURST = 7, 136 144 M_WRITE_CMD = 8, 137 145 M_WRITE_RSP = 9, 138 M_WRITE_ TEST= 10,146 M_WRITE_BLOCK = 10, 139 147 M_WRITE_SUCCESS = 11, 140 148 M_WRITE_ERROR = 12, … … 185 193 // Constructor 186 194 VciBlockDeviceTsarV4( 187 sc_module_name 195 sc_module_name name, 188 196 const soclib::common::MappingTable &mt, 189 197 const soclib::common::IntTab &srcid, 190 198 const soclib::common::IntTab &tgtid, 191 const std::string&filename,192 const uint32_tblock_size = 512,193 const uint32_tburst_size = 64,194 const uint32_tlatency = 0);199 const std::string &filename, 200 const uint32_t block_size = 512, 201 const uint32_t burst_size = 64, 202 const uint32_t latency = 0); 195 203 }; 196 204
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