Changeset 284 for trunk/modules/vci_mem_cache_v4/caba/source/include
- Timestamp:
- Dec 11, 2012, 6:19:35 PM (12 years ago)
- Location:
- trunk/modules/vci_mem_cache_v4/caba/source/include
- Files:
-
- 2 edited
-
mem_cache_directory_v4.h (modified) (1 diff)
-
vci_mem_cache_v4.h (modified) (14 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
r283 r284 7 7 #include "arithmetics.h" 8 8 9 // !!! 10 // The L1_MULTI_CACHE mechanism does no longer work with the new pktid encoding 11 // of TSAR. Turning the define below to a non null value will cause the memcache 12 // to behave in an unpredicted way. 13 // TODO Either remove the mechanism from the mem cache or update its behaviour. 9 14 #define L1_MULTI_CACHE 0 15 10 16 //#define RANDOM_EVICTION 11 17 -
trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
r283 r284 27 27 * Maintainers: alain eric.guthmuller@polytechnique.edu 28 28 * cesar.fuguet-tortolero@lip6.fr 29 * alexandre.joannou@lip6.fr 29 30 * 30 31 * Modifications done by Christophe Choichillon on the 7/04/2009: … … 80 81 TGT_CMD_READ, 81 82 TGT_CMD_WRITE, 82 TGT_CMD_ ATOMIC83 TGT_CMD_CAS 83 84 }; 84 85 … … 87 88 TGT_RSP_READ_IDLE, 88 89 TGT_RSP_WRITE_IDLE, 89 TGT_RSP_ SC_IDLE,90 TGT_RSP_CAS_IDLE, 90 91 TGT_RSP_XRAM_IDLE, 91 92 TGT_RSP_INIT_IDLE, … … 93 94 TGT_RSP_READ, 94 95 TGT_RSP_WRITE, 95 TGT_RSP_ SC,96 TGT_RSP_CAS, 96 97 TGT_RSP_XRAM, 97 98 TGT_RSP_INIT, … … 109 110 INIT_CMD_UPDT_INDEX, 110 111 INIT_CMD_UPDT_DATA, 111 INIT_CMD_ SC_UPDT_IDLE,112 INIT_CMD_ SC_BRDCAST,113 INIT_CMD_ SC_UPDT_NLINE,114 INIT_CMD_ SC_UPDT_INDEX,115 INIT_CMD_ SC_UPDT_DATA,116 INIT_CMD_ SC_UPDT_DATA_HIGH112 INIT_CMD_CAS_UPDT_IDLE, 113 INIT_CMD_CAS_BRDCAST, 114 INIT_CMD_CAS_UPDT_NLINE, 115 INIT_CMD_CAS_UPDT_INDEX, 116 INIT_CMD_CAS_UPDT_DATA, 117 INIT_CMD_CAS_UPDT_DATA_HIGH 117 118 }; 118 119 … … 199 200 IXR_CMD_READ_IDLE, 200 201 IXR_CMD_WRITE_IDLE, 201 IXR_CMD_ SC_IDLE,202 IXR_CMD_CAS_IDLE, 202 203 IXR_CMD_XRAM_IDLE, 203 204 IXR_CMD_READ_NLINE, 204 205 IXR_CMD_WRITE_NLINE, 205 IXR_CMD_ SC_NLINE,206 IXR_CMD_CAS_NLINE, 206 207 IXR_CMD_XRAM_DATA 207 208 }; 208 209 209 /* States of the SCfsm */210 enum sc_fsm_state_e{211 SC_IDLE,212 SC_DIR_REQ,213 SC_DIR_LOCK,214 SC_DIR_HIT_READ,215 SC_DIR_HIT_WRITE,216 SC_UPT_LOCK,217 SC_UPT_HEAP_LOCK,218 SC_UPT_REQ,219 SC_UPT_NEXT,220 SC_BC_TRT_LOCK,221 SC_BC_UPT_LOCK,222 SC_BC_DIR_INVAL,223 SC_BC_CC_SEND,224 SC_BC_XRAM_REQ,225 SC_RSP_FAIL,226 SC_RSP_SUCCESS,227 SC_MISS_TRT_LOCK,228 SC_MISS_TRT_SET,229 SC_MISS_XRAM_REQ,230 SC_WAIT210 /* States of the CAS fsm */ 211 enum cas_fsm_state_e{ 212 CAS_IDLE, 213 CAS_DIR_REQ, 214 CAS_DIR_LOCK, 215 CAS_DIR_HIT_READ, 216 CAS_DIR_HIT_WRITE, 217 CAS_UPT_LOCK, 218 CAS_UPT_HEAP_LOCK, 219 CAS_UPT_REQ, 220 CAS_UPT_NEXT, 221 CAS_BC_TRT_LOCK, 222 CAS_BC_UPT_LOCK, 223 CAS_BC_DIR_INVAL, 224 CAS_BC_CC_SEND, 225 CAS_BC_XRAM_REQ, 226 CAS_RSP_FAIL, 227 CAS_RSP_SUCCESS, 228 CAS_MISS_TRT_LOCK, 229 CAS_MISS_TRT_SET, 230 CAS_MISS_XRAM_REQ, 231 CAS_WAIT 231 232 }; 232 233 … … 253 254 ALLOC_DIR_READ, 254 255 ALLOC_DIR_WRITE, 255 ALLOC_DIR_ SC,256 ALLOC_DIR_CAS, 256 257 ALLOC_DIR_CLEANUP, 257 258 ALLOC_DIR_XRAM_RSP … … 262 263 ALLOC_TRT_READ, 263 264 ALLOC_TRT_WRITE, 264 ALLOC_TRT_ SC,265 ALLOC_TRT_CAS, 265 266 ALLOC_TRT_XRAM_RSP, 266 267 ALLOC_TRT_IXR_RSP … … 273 274 ALLOC_UPT_INIT_RSP, 274 275 ALLOC_UPT_CLEANUP, 275 ALLOC_UPT_ SC276 ALLOC_UPT_CAS 276 277 }; 277 278 … … 281 282 ALLOC_HEAP_READ, 282 283 ALLOC_HEAP_WRITE, 283 ALLOC_HEAP_ SC,284 ALLOC_HEAP_CAS, 284 285 ALLOC_HEAP_CLEANUP, 285 286 ALLOC_HEAP_XRAM_RSP 287 }; 288 289 /* transaction type, pktid field */ 290 enum transaction_type_e 291 { 292 // b3 unused 293 // b2 READ / NOT READ 294 // Si READ 295 // b1 DATA / INS 296 // b0 UNC / MISS 297 // Si NOT READ 298 // b1 accÚs table llsc type SW / other 299 // b2 WRITE/CAS/LL/SC 300 TYPE_READ_DATA_UNC = 0x0, 301 TYPE_READ_DATA_MISS = 0x1, 302 TYPE_READ_INS_UNC = 0x2, 303 TYPE_READ_INS_MISS = 0x3, 304 TYPE_WRITE = 0x4, 305 TYPE_CAS = 0x5, 306 TYPE_LL = 0x6, 307 TYPE_SC = 0x7 308 }; 309 310 /* SC return values */ 311 enum sc_status_type_e 312 { 313 SC_SUCCESS = 0x00000000, 314 SC_FAIL = 0x00000001 286 315 }; 287 316 … … 296 325 bool m_debug_read_fsm; 297 326 bool m_debug_write_fsm; 298 bool m_debug_ sc_fsm;327 bool m_debug_cas_fsm; 299 328 bool m_debug_cleanup_fsm; 300 329 bool m_debug_ixr_cmd_fsm; … … 326 355 uint32_t m_cpt_ll; // Number of LL transactions 327 356 uint32_t m_cpt_sc; // Number of SC transactions 357 uint32_t m_cpt_cas; // Number of CAS transactions 328 358 329 359 size_t m_prev_count; … … 429 459 GenericFifo<be_t> m_cmd_write_be_fifo; 430 460 431 // Fifo between TGT_CMD fsm and SCfsm432 GenericFifo<uint64_t> m_cmd_ sc_addr_fifo;433 GenericFifo<bool> m_cmd_ sc_eop_fifo;434 GenericFifo<size_t> m_cmd_ sc_srcid_fifo;435 GenericFifo<size_t> m_cmd_ sc_trdid_fifo;436 GenericFifo<size_t> m_cmd_ sc_pktid_fifo;437 GenericFifo<data_t> m_cmd_ sc_wdata_fifo;461 // Fifo between TGT_CMD fsm and CAS fsm 462 GenericFifo<uint64_t> m_cmd_cas_addr_fifo; 463 GenericFifo<bool> m_cmd_cas_eop_fifo; 464 GenericFifo<size_t> m_cmd_cas_srcid_fifo; 465 GenericFifo<size_t> m_cmd_cas_trdid_fifo; 466 GenericFifo<size_t> m_cmd_cas_pktid_fifo; 467 GenericFifo<data_t> m_cmd_cas_wdata_fifo; 438 468 439 469 sc_signal<int> r_tgt_cmd_fsm; … … 594 624 595 625 /////////////////////////////////////////////////////// 596 // Registers controlled by SCfsm626 // Registers controlled by CAS fsm 597 627 /////////////////////////////////////////////////////// 598 628 599 sc_signal<int> r_ sc_fsm; // FSM state600 sc_signal<data_t> r_ sc_wdata; // write data word601 sc_signal<data_t> * r_ sc_rdata; // read data word602 sc_signal<uint32_t> r_ sc_lfsr; // lfsr for random introducing603 sc_signal<size_t> r_ sc_cpt; // size of command604 sc_signal<copy_t> r_ sc_copy; // Srcid of the first copy605 sc_signal<copy_t> r_ sc_copy_cache; // Srcid of the first copy606 sc_signal<bool> r_ sc_copy_inst; // Type of the first copy607 sc_signal<size_t> r_ sc_count; // number of copies608 sc_signal<size_t> r_ sc_ptr; // pointer to the heap609 sc_signal<size_t> r_ sc_next_ptr; // next pointer to the heap610 sc_signal<bool> r_ sc_is_cnt; // is_cnt bit (in directory)611 sc_signal<bool> r_ sc_dirty; // dirty bit (in directory)612 sc_signal<size_t> r_ sc_way; // way in directory613 sc_signal<size_t> r_ sc_set; // set in directory614 sc_signal<data_t> r_ sc_tag; // cache line tag (in directory)615 sc_signal<size_t> r_ sc_trt_index; // Transaction Table index616 sc_signal<size_t> r_ sc_upt_index; // Update Table index617 618 // Buffer between SCfsm and INIT_CMD fsm (XRAM read)619 sc_signal<bool> r_ sc_to_ixr_cmd_req; // valid request620 sc_signal<addr_t> r_ sc_to_ixr_cmd_nline; // cache line index621 sc_signal<size_t> r_ sc_to_ixr_cmd_trdid; // index in Transaction Table622 sc_signal<bool> r_ sc_to_ixr_cmd_write; // write request623 sc_signal<data_t> * r_ sc_to_ixr_cmd_data; // cache line data624 625 626 // Buffer between SCfsm and TGT_RSP fsm627 sc_signal<bool> r_ sc_to_tgt_rsp_req; // valid request628 sc_signal<data_t> r_ sc_to_tgt_rsp_data; // read data word629 sc_signal<size_t> r_ sc_to_tgt_rsp_srcid; // Transaction srcid630 sc_signal<size_t> r_ sc_to_tgt_rsp_trdid; // Transaction trdid631 sc_signal<size_t> r_ sc_to_tgt_rsp_pktid; // Transaction pktid632 633 // Buffer between SCfsm and INIT_CMD fsm (Update/Invalidate L1 caches)634 sc_signal<bool> r_ sc_to_init_cmd_multi_req; // valid request635 sc_signal<bool> r_ sc_to_init_cmd_brdcast_req; // brdcast request636 sc_signal<addr_t> r_ sc_to_init_cmd_nline; // cache line index637 sc_signal<size_t> r_ sc_to_init_cmd_trdid; // index in Update Table638 sc_signal<data_t> r_ sc_to_init_cmd_wdata; // data (one word)639 sc_signal<bool> r_ sc_to_init_cmd_is_long; // it is a 64 bits SC640 sc_signal<data_t> r_ sc_to_init_cmd_wdata_high; // data high (one word)641 sc_signal<size_t> r_ sc_to_init_cmd_index; // index of the word in line642 GenericFifo<bool> m_ sc_to_init_cmd_inst_fifo; // fifo for the L1 type643 GenericFifo<size_t> m_ sc_to_init_cmd_srcid_fifo; // fifo for srcids629 sc_signal<int> r_cas_fsm; // FSM state 630 sc_signal<data_t> r_cas_wdata; // write data word 631 sc_signal<data_t> * r_cas_rdata; // read data word 632 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing 633 sc_signal<size_t> r_cas_cpt; // size of command 634 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy 635 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy 636 sc_signal<bool> r_cas_copy_inst; // Type of the first copy 637 sc_signal<size_t> r_cas_count; // number of copies 638 sc_signal<size_t> r_cas_ptr; // pointer to the heap 639 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap 640 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) 641 sc_signal<bool> r_cas_dirty; // dirty bit (in directory) 642 sc_signal<size_t> r_cas_way; // way in directory 643 sc_signal<size_t> r_cas_set; // set in directory 644 sc_signal<data_t> r_cas_tag; // cache line tag (in directory) 645 sc_signal<size_t> r_cas_trt_index; // Transaction Table index 646 sc_signal<size_t> r_cas_upt_index; // Update Table index 647 648 // Buffer between CAS fsm and INIT_CMD fsm (XRAM read) 649 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 650 sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index 651 sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table 652 sc_signal<bool> r_cas_to_ixr_cmd_write; // write request 653 sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data 654 655 656 // Buffer between CAS fsm and TGT_RSP fsm 657 sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request 658 sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word 659 sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid 660 sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid 661 sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid 662 663 // Buffer between CAS fsm and INIT_CMD fsm (Update/Invalidate L1 caches) 664 sc_signal<bool> r_cas_to_init_cmd_multi_req; // valid request 665 sc_signal<bool> r_cas_to_init_cmd_brdcast_req; // brdcast request 666 sc_signal<addr_t> r_cas_to_init_cmd_nline; // cache line index 667 sc_signal<size_t> r_cas_to_init_cmd_trdid; // index in Update Table 668 sc_signal<data_t> r_cas_to_init_cmd_wdata; // data (one word) 669 sc_signal<bool> r_cas_to_init_cmd_is_long; // it is a 64 bits CAS 670 sc_signal<data_t> r_cas_to_init_cmd_wdata_high; // data high (one word) 671 sc_signal<size_t> r_cas_to_init_cmd_index; // index of the word in line 672 GenericFifo<bool> m_cas_to_init_cmd_inst_fifo; // fifo for the L1 type 673 GenericFifo<size_t> m_cas_to_init_cmd_srcid_fifo; // fifo for srcids 644 674 #if L1_MULTI_CACHE 645 GenericFifo<size_t> m_ sc_to_init_cmd_cache_id_fifo; // fifo for srcids675 GenericFifo<size_t> m_cas_to_init_cmd_cache_id_fifo; // fifo for srcids 646 676 #endif 647 677 648 // Buffer between SCfsm and INIT_RSP fsm (Decrement UPT entry)649 sc_signal<bool> r_ sc_to_init_rsp_req; // valid request650 sc_signal<size_t> r_ sc_to_init_rsp_upt_index; // index in update table678 // Buffer between CAS fsm and INIT_RSP fsm (Decrement UPT entry) 679 sc_signal<bool> r_cas_to_init_rsp_req; // valid request 680 sc_signal<size_t> r_cas_to_init_rsp_upt_index; // index in update table 651 681 652 682 ////////////////////////////////////////////////////
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