Ignore:
Timestamp:
Dec 17, 2012, 3:49:47 PM (12 years ago)
Author:
alain
Message:

Fixing a bug identified by Hao: there was a dead-lock condition if:

  • DCACHE FSM IDLE and XTN_SWITCH request from processor
  • ICACHE FSM IDLE and ITLB miss following a read from processor

The ICACHE FSM was waiting in TLB_WAIT state
The DCACHE FSM was waiting in XTN_SWITCH state
The solution is: the DCACHE FSM handles the r_icache_tlb_miss_req
with highest priority in the XTN_SWITCH state.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

    r284 r285  
    23502350                    {     
    23512351                    case iss_t::XTN_PTPR:                       // itlb & dtlb must be flushed
    2352                         r_mmu_ptpr       = m_dreq.wdata;
    23532352                        r_dcache_xtn_req = true;
    23542353                        r_dcache_fsm     = DCACHE_XTN_SWITCH;
     
    33683367    }
    33693368    ///////////////////////
    3370     case DCACHE_XTN_SWITCH:             // Both itlb and dtlb must be flushed
    3371     {
     3369    case DCACHE_XTN_SWITCH:             // The r_ptpr registers must be written,
     3370                                // and both itlb and dtlb must be flushed.
     3371                                // Caution : the itlb miss requests must be taken
     3372                                // to avoid dead-lock in case of simultaneous ITLB miss
     3373    {
     3374        // itlb miss request
     3375        if ( r_icache_tlb_miss_req.read() )
     3376        {
     3377            r_dcache_tlb_ins    = true;
     3378            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
     3379            r_dcache_fsm        = DCACHE_TLB_MISS;
     3380            break;
     3381        }
     3382
    33723383        if ( not r_dcache_xtn_req.read() )
    33733384        {
    33743385            r_dtlb.flush();
     3386            r_mmu_ptpr   = m_dreq.wdata;
    33753387            r_dcache_fsm = DCACHE_IDLE;
    33763388            m_drsp.valid = true;
     
    33803392    /////////////////////
    33813393    case DCACHE_XTN_SYNC:               // waiting until write buffer empty
    3382                                         // The coherence request must be taken
    3383                                         // as there is a risk of dead-lock
     3394                                // The coherence request must be taken
     3395                                // as there is a risk of dead-lock
    33843396    {
    33853397        // external coherence request
     
    34013413    case DCACHE_XTN_IC_INVAL_VA:        // Caution : the itlb miss requests must be taken
    34023414    case DCACHE_XTN_IC_INVAL_PA:        // because the XTN_ICACHE_INVAL request to icache
    3403     case DCACHE_XTN_IT_INVAL:           // can generate an itlb miss...
     3415    case DCACHE_XTN_IT_INVAL:           // can generate an itlb miss,
     3416                                    // and because it can exist a simultaneous ITLB miss
    34043417    {
    34053418        // external coherence request
     
    34343447                                // A cleanup request is generated for each valid line
    34353448                                // and we are blocked until the previous cleanup is completed
    3436                                 // Finally, both the itlb and dtlb are flushed
     3449                                                // Finally, both the itlb and dtlb are flushed
    34373450                                // (including global entries)
    34383451    {
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